diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2015-01-27 00:09:39 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-03-16 19:44:22 -0400 |
commit | adc346b133c952ec6988d90f6fa79cbe0a3eb7ef (patch) | |
tree | f408ee3a6dc7116495e4d85344431f408d43d9ab /drivers/gpu | |
parent | 046d669c62f37323ef0329c41d83a03c06b2087d (diff) |
drm/nouveau/fifo/nv04: remove the loop from the interrupt handler
Complete bong hit (and not the last...), the hardware will reassert the
interrupt to PMC if it's necessary.
Also potentially harmful in the face of interrupts such as the non-stall
interrupt, which remain active in NV_PFIFO_INTR even when we don't care
about servicing it.
It appears (hopefully, fdo#87244), that under certain loads, the methods
may pass quickly enough to hit the "100 spins and kill PFIFO" thing that
we had going on. Not ideal ;)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | 85 |
1 files changed, 35 insertions, 50 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c index b038b6eb51db..043e4296084c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c | |||
@@ -502,72 +502,57 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) | |||
502 | { | 502 | { |
503 | struct nvkm_device *device = nv_device(subdev); | 503 | struct nvkm_device *device = nv_device(subdev); |
504 | struct nv04_fifo_priv *priv = (void *)subdev; | 504 | struct nv04_fifo_priv *priv = (void *)subdev; |
505 | uint32_t status, reassign; | 505 | u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0); |
506 | int cnt = 0; | 506 | u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask; |
507 | u32 reassign, chid, get, sem; | ||
507 | 508 | ||
508 | reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; | 509 | reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; |
509 | while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { | 510 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); |
510 | uint32_t chid, get; | ||
511 | |||
512 | nv_wr32(priv, NV03_PFIFO_CACHES, 0); | ||
513 | |||
514 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; | ||
515 | get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); | ||
516 | 511 | ||
517 | if (status & NV_PFIFO_INTR_CACHE_ERROR) { | 512 | chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; |
518 | nv04_fifo_cache_error(device, priv, chid, get); | 513 | get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); |
519 | status &= ~NV_PFIFO_INTR_CACHE_ERROR; | ||
520 | } | ||
521 | 514 | ||
522 | if (status & NV_PFIFO_INTR_DMA_PUSHER) { | 515 | if (stat & NV_PFIFO_INTR_CACHE_ERROR) { |
523 | nv04_fifo_dma_pusher(device, priv, chid); | 516 | nv04_fifo_cache_error(device, priv, chid, get); |
524 | status &= ~NV_PFIFO_INTR_DMA_PUSHER; | 517 | stat &= ~NV_PFIFO_INTR_CACHE_ERROR; |
525 | } | 518 | } |
526 | 519 | ||
527 | if (status & NV_PFIFO_INTR_SEMAPHORE) { | 520 | if (stat & NV_PFIFO_INTR_DMA_PUSHER) { |
528 | uint32_t sem; | 521 | nv04_fifo_dma_pusher(device, priv, chid); |
522 | stat &= ~NV_PFIFO_INTR_DMA_PUSHER; | ||
523 | } | ||
529 | 524 | ||
530 | status &= ~NV_PFIFO_INTR_SEMAPHORE; | 525 | if (stat & NV_PFIFO_INTR_SEMAPHORE) { |
531 | nv_wr32(priv, NV03_PFIFO_INTR_0, | 526 | stat &= ~NV_PFIFO_INTR_SEMAPHORE; |
532 | NV_PFIFO_INTR_SEMAPHORE); | 527 | nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); |
533 | 528 | ||
534 | sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); | 529 | sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); |
535 | nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); | 530 | nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); |
536 | 531 | ||
537 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); | 532 | nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); |
538 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); | 533 | nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); |
539 | } | 534 | } |
540 | 535 | ||
541 | if (device->card_type == NV_50) { | 536 | if (device->card_type == NV_50) { |
542 | if (status & 0x00000010) { | 537 | if (stat & 0x00000010) { |
543 | status &= ~0x00000010; | 538 | stat &= ~0x00000010; |
544 | nv_wr32(priv, 0x002100, 0x00000010); | 539 | nv_wr32(priv, 0x002100, 0x00000010); |
545 | } | ||
546 | |||
547 | if (status & 0x40000000) { | ||
548 | nv_wr32(priv, 0x002100, 0x40000000); | ||
549 | nvkm_fifo_uevent(&priv->base); | ||
550 | status &= ~0x40000000; | ||
551 | } | ||
552 | } | 540 | } |
553 | 541 | ||
554 | if (status) { | 542 | if (stat & 0x40000000) { |
555 | nv_warn(priv, "unknown intr 0x%08x, ch %d\n", | 543 | nv_wr32(priv, 0x002100, 0x40000000); |
556 | status, chid); | 544 | nvkm_fifo_uevent(&priv->base); |
557 | nv_wr32(priv, NV03_PFIFO_INTR_0, status); | 545 | stat &= ~0x40000000; |
558 | status = 0; | ||
559 | } | 546 | } |
560 | |||
561 | nv_wr32(priv, NV03_PFIFO_CACHES, reassign); | ||
562 | } | 547 | } |
563 | 548 | ||
564 | if (status) { | 549 | if (stat) { |
565 | nv_error(priv, "still angry after %d spins, halt\n", cnt); | 550 | nv_warn(priv, "unknown intr 0x%08x\n", stat); |
566 | nv_wr32(priv, 0x002140, 0); | 551 | nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); |
567 | nv_wr32(priv, 0x000140, 0); | 552 | nv_wr32(priv, NV03_PFIFO_INTR_0, stat); |
568 | } | 553 | } |
569 | 554 | ||
570 | nv_wr32(priv, 0x000100, 0x00000100); | 555 | nv_wr32(priv, NV03_PFIFO_CACHES, reassign); |
571 | } | 556 | } |
572 | 557 | ||
573 | static int | 558 | static int |