diff options
author | Dave Airlie <airlied@redhat.com> | 2013-02-23 21:39:02 -0500 |
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committer | Dave Airlie <airlied@redhat.com> | 2013-02-23 21:39:02 -0500 |
commit | a497bfe9dbbc0fbacd61295986372a626e73f452 (patch) | |
tree | 9b568e1fecfe8e471fd5606de461374471cc7ec8 /drivers/gpu | |
parent | a3b1097c037ae992510fe8f1e933072280ef19b0 (diff) | |
parent | 202adf4b9f5957b26a1cb97267d78e0edb319c5e (diff) |
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Two regressions fixes from snowboarding land
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: Revert hdmi HDP pin checks
drm/i915: Handle untiled planes when computing their offsets
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 41 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 7 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sprite.c | 8 |
4 files changed, 34 insertions, 51 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6337196b7931..a05ac2c91ba2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -2001,18 +2001,29 @@ void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) | |||
2001 | 2001 | ||
2002 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel | 2002 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2003 | * is assumed to be a power-of-two. */ | 2003 | * is assumed to be a power-of-two. */ |
2004 | unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, | 2004 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2005 | unsigned int bpp, | 2005 | unsigned int tiling_mode, |
2006 | unsigned int pitch) | 2006 | unsigned int cpp, |
2007 | unsigned int pitch) | ||
2007 | { | 2008 | { |
2008 | int tile_rows, tiles; | 2009 | if (tiling_mode != I915_TILING_NONE) { |
2010 | unsigned int tile_rows, tiles; | ||
2009 | 2011 | ||
2010 | tile_rows = *y / 8; | 2012 | tile_rows = *y / 8; |
2011 | *y %= 8; | 2013 | *y %= 8; |
2012 | tiles = *x / (512/bpp); | ||
2013 | *x %= 512/bpp; | ||
2014 | 2014 | ||
2015 | return tile_rows * pitch * 8 + tiles * 4096; | 2015 | tiles = *x / (512/cpp); |
2016 | *x %= 512/cpp; | ||
2017 | |||
2018 | return tile_rows * pitch * 8 + tiles * 4096; | ||
2019 | } else { | ||
2020 | unsigned int offset; | ||
2021 | |||
2022 | offset = *y * pitch + *x * cpp; | ||
2023 | *y = 0; | ||
2024 | *x = (offset & 4095) / cpp; | ||
2025 | return offset & -4096; | ||
2026 | } | ||
2016 | } | 2027 | } |
2017 | 2028 | ||
2018 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, | 2029 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
@@ -2089,9 +2100,9 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |||
2089 | 2100 | ||
2090 | if (INTEL_INFO(dev)->gen >= 4) { | 2101 | if (INTEL_INFO(dev)->gen >= 4) { |
2091 | intel_crtc->dspaddr_offset = | 2102 | intel_crtc->dspaddr_offset = |
2092 | intel_gen4_compute_offset_xtiled(&x, &y, | 2103 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2093 | fb->bits_per_pixel / 8, | 2104 | fb->bits_per_pixel / 8, |
2094 | fb->pitches[0]); | 2105 | fb->pitches[0]); |
2095 | linear_offset -= intel_crtc->dspaddr_offset; | 2106 | linear_offset -= intel_crtc->dspaddr_offset; |
2096 | } else { | 2107 | } else { |
2097 | intel_crtc->dspaddr_offset = linear_offset; | 2108 | intel_crtc->dspaddr_offset = linear_offset; |
@@ -2182,9 +2193,9 @@ static int ironlake_update_plane(struct drm_crtc *crtc, | |||
2182 | 2193 | ||
2183 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); | 2194 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
2184 | intel_crtc->dspaddr_offset = | 2195 | intel_crtc->dspaddr_offset = |
2185 | intel_gen4_compute_offset_xtiled(&x, &y, | 2196 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2186 | fb->bits_per_pixel / 8, | 2197 | fb->bits_per_pixel / 8, |
2187 | fb->pitches[0]); | 2198 | fb->pitches[0]); |
2188 | linear_offset -= intel_crtc->dspaddr_offset; | 2199 | linear_offset -= intel_crtc->dspaddr_offset; |
2189 | 2200 | ||
2190 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | 2201 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d282052aadd4..07ebac6fe8ca 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -648,9 +648,10 @@ extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, | |||
648 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, | 648 | extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, |
649 | struct drm_display_mode *mode); | 649 | struct drm_display_mode *mode); |
650 | 650 | ||
651 | extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, | 651 | extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
652 | unsigned int bpp, | 652 | unsigned int tiling_mode, |
653 | unsigned int pitch); | 653 | unsigned int bpp, |
654 | unsigned int pitch); | ||
654 | 655 | ||
655 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, | 656 | extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, |
656 | struct drm_file *file_priv); | 657 | struct drm_file *file_priv); |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 3ea0c8b6a00f..83d66602414b 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -793,28 +793,6 @@ bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |||
793 | return true; | 793 | return true; |
794 | } | 794 | } |
795 | 795 | ||
796 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) | ||
797 | { | ||
798 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); | ||
799 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
800 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); | ||
801 | uint32_t bit; | ||
802 | |||
803 | switch (intel_dig_port->port) { | ||
804 | case PORT_B: | ||
805 | bit = PORTB_HOTPLUG_LIVE_STATUS; | ||
806 | break; | ||
807 | case PORT_C: | ||
808 | bit = PORTC_HOTPLUG_LIVE_STATUS; | ||
809 | break; | ||
810 | default: | ||
811 | bit = 0; | ||
812 | break; | ||
813 | } | ||
814 | |||
815 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | ||
816 | } | ||
817 | |||
818 | static enum drm_connector_status | 796 | static enum drm_connector_status |
819 | intel_hdmi_detect(struct drm_connector *connector, bool force) | 797 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
820 | { | 798 | { |
@@ -827,13 +805,6 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) | |||
827 | struct edid *edid; | 805 | struct edid *edid; |
828 | enum drm_connector_status status = connector_status_disconnected; | 806 | enum drm_connector_status status = connector_status_disconnected; |
829 | 807 | ||
830 | |||
831 | if (IS_G4X(dev) && !g4x_hdmi_connected(intel_hdmi)) | ||
832 | return status; | ||
833 | else if (HAS_PCH_SPLIT(dev) && | ||
834 | !ibx_digital_port_connected(dev_priv, intel_dig_port)) | ||
835 | return status; | ||
836 | |||
837 | intel_hdmi->has_hdmi_sink = false; | 808 | intel_hdmi->has_hdmi_sink = false; |
838 | intel_hdmi->has_audio = false; | 809 | intel_hdmi->has_audio = false; |
839 | intel_hdmi->rgb_quant_range_selectable = false; | 810 | intel_hdmi->rgb_quant_range_selectable = false; |
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index d086e48a831a..1b6eb76beb7c 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c | |||
@@ -122,8 +122,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
122 | 122 | ||
123 | linear_offset = y * fb->pitches[0] + x * pixel_size; | 123 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
124 | sprsurf_offset = | 124 | sprsurf_offset = |
125 | intel_gen4_compute_offset_xtiled(&x, &y, | 125 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
126 | pixel_size, fb->pitches[0]); | 126 | pixel_size, fb->pitches[0]); |
127 | linear_offset -= sprsurf_offset; | 127 | linear_offset -= sprsurf_offset; |
128 | 128 | ||
129 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET | 129 | /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET |
@@ -295,8 +295,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb, | |||
295 | 295 | ||
296 | linear_offset = y * fb->pitches[0] + x * pixel_size; | 296 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
297 | dvssurf_offset = | 297 | dvssurf_offset = |
298 | intel_gen4_compute_offset_xtiled(&x, &y, | 298 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
299 | pixel_size, fb->pitches[0]); | 299 | pixel_size, fb->pitches[0]); |
300 | linear_offset -= dvssurf_offset; | 300 | linear_offset -= dvssurf_offset; |
301 | 301 | ||
302 | if (obj->tiling_mode != I915_TILING_NONE) | 302 | if (obj->tiling_mode != I915_TILING_NONE) |