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authorBen Skeggs <bskeggs@redhat.com>2013-07-03 22:58:16 -0400
committerBen Skeggs <bskeggs@redhat.com>2013-07-04 23:44:09 -0400
commit960b4381c5fff0b0f16f4b812082811dde1ab7ab (patch)
treeaebe8ffdf27be25baea19213151b9f5790c0a5e9 /drivers/gpu
parent0085a60524aeb743c15bbdf7354f4e4f6623243e (diff)
drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c17
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 34ed87f1ff16..118b54b1b83f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1014,13 +1014,14 @@ nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv)
1014void 1014void
1015nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) 1015nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
1016{ 1016{
1017 u32 tpc_mask = 0, tpc_set = 0; 1017 u64 tpc_mask = 0, tpc_set = 0;
1018 u8 tpcnr[GPC_MAX], a, b; 1018 u8 tpcnr[GPC_MAX];
1019 int gpc, tpc, i; 1019 int gpc, tpc;
1020 int i, a, b;
1020 1021
1021 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); 1022 memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
1022 for (gpc = 0; gpc < priv->gpc_nr; gpc++) 1023 for (gpc = 0; gpc < priv->gpc_nr; gpc++)
1023 tpc_mask |= ((1 << priv->tpc_nr[gpc]) - 1) << (gpc * 8); 1024 tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8);
1024 1025
1025 for (i = 0, gpc = -1, b = -1; i < 32; i++) { 1026 for (i = 0, gpc = -1, b = -1; i < 32; i++) {
1026 a = (i * (priv->tpc_total - 1)) / 32; 1027 a = (i * (priv->tpc_total - 1)) / 32;
@@ -1034,8 +1035,12 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
1034 tpc_set |= 1 << ((gpc * 8) + tpc); 1035 tpc_set |= 1 << ((gpc * 8) + tpc);
1035 } 1036 }
1036 1037
1037 nv_wr32(priv, 0x406800 + (i * 0x20), tpc_set); 1038 nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
1038 nv_wr32(priv, 0x406c00 + (i * 0x20), tpc_set ^ tpc_mask); 1039 nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask));
1040 if (priv->gpc_nr > 4) {
1041 nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set));
1042 nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask));
1043 }
1039 } 1044 }
1040} 1045}
1041 1046