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authorDave Airlie <airlied@redhat.com>2012-08-27 02:22:20 -0400
committerDave Airlie <airlied@redhat.com>2012-08-27 02:22:20 -0400
commit93bb70e0c00f1be4cc857e4d8375c44058cce71e (patch)
tree7b6a11844e00b3f4bf8281c7a799e61494220819 /drivers/gpu
parent6f314ebbaa2667d67a7206ba78f28e46cf47eda5 (diff)
parentc182ae42cc3611f7b3fa803c0bcab6e5d29bea63 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next
There was some merge conflicts in -next and they weren't so pretty, so backmerge now to avoid them. Conflicts: drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/intel_modes.c
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/Kconfig1
-rw-r--r--drivers/gpu/drm/drm_modes.c3
-rw-r--r--drivers/gpu/drm/drm_proc.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c4
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c5
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c36
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h2
-rw-r--r--drivers/gpu/drm/i915/intel_modes.c29
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c15
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_acpi.c6
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c25
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c105
-rw-r--r--drivers/gpu/drm/radeon/r600d.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon.h15
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_atpx_handler.c56
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c138
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c1
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r6008
-rw-r--r--drivers/gpu/drm/udl/Kconfig1
-rw-r--r--drivers/gpu/drm/udl/udl_modeset.c3
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_kms.c6
-rw-r--r--drivers/gpu/vga/vga_switcheroo.c61
26 files changed, 381 insertions, 169 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 45536db74d8c..3a8c68345fe2 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -22,6 +22,7 @@ menuconfig DRM
22config DRM_USB 22config DRM_USB
23 tristate 23 tristate
24 depends on DRM 24 depends on DRM
25 depends on USB_ARCH_HAS_HCD
25 select USB 26 select USB
26 select USB_SUPPORT 27 select USB_SUPPORT
27 28
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index b7adb4a967fd..28637c181b15 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -706,9 +706,6 @@ void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
706 p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal); 706 p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
707 p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay); 707 p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
708 p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal); 708 p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
709
710 p->crtc_hadjusted = false;
711 p->crtc_vadjusted = false;
712} 709}
713EXPORT_SYMBOL(drm_mode_set_crtcinfo); 710EXPORT_SYMBOL(drm_mode_set_crtcinfo);
714 711
diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
index 371c695322d9..da457b18eaaf 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -89,7 +89,7 @@ static const struct file_operations drm_proc_fops = {
89 * Create a given set of proc files represented by an array of 89 * Create a given set of proc files represented by an array of
90 * gdm_proc_lists in the given root directory. 90 * gdm_proc_lists in the given root directory.
91 */ 91 */
92int drm_proc_create_files(struct drm_info_list *files, int count, 92static int drm_proc_create_files(struct drm_info_list *files, int count,
93 struct proc_dir_entry *root, struct drm_minor *minor) 93 struct proc_dir_entry *root, struct drm_minor *minor)
94{ 94{
95 struct drm_device *dev = minor->dev; 95 struct drm_device *dev = minor->dev;
@@ -172,7 +172,7 @@ int drm_proc_init(struct drm_minor *minor, int minor_id,
172 return 0; 172 return 0;
173} 173}
174 174
175int drm_proc_remove_files(struct drm_info_list *files, int count, 175static int drm_proc_remove_files(struct drm_info_list *files, int count,
176 struct drm_minor *minor) 176 struct drm_minor *minor)
177{ 177{
178 struct list_head *pos, *q; 178 struct list_head *pos, *q;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 051459324826..31054fa44c47 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2273,11 +2273,11 @@ int i915_gpu_idle(struct drm_device *dev)
2273 2273
2274 /* Flush everything onto the inactive list. */ 2274 /* Flush everything onto the inactive list. */
2275 for_each_ring(ring, dev_priv, i) { 2275 for_each_ring(ring, dev_priv, i) {
2276 ret = i915_ring_idle(ring); 2276 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2277 if (ret) 2277 if (ret)
2278 return ret; 2278 return ret;
2279 2279
2280 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); 2280 ret = i915_ring_idle(ring);
2281 if (ret) 2281 if (ret)
2282 return ret; 2282 return ret;
2283 } 2283 }
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 3b3b731a17c3..804d65345e2c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -261,7 +261,10 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
261 pte_flags |= GEN6_PTE_CACHE_LLC; 261 pte_flags |= GEN6_PTE_CACHE_LLC;
262 break; 262 break;
263 case I915_CACHE_NONE: 263 case I915_CACHE_NONE:
264 pte_flags |= GEN6_PTE_UNCACHED; 264 if (IS_HASWELL(dev))
265 pte_flags |= HSW_PTE_UNCACHED;
266 else
267 pte_flags |= GEN6_PTE_UNCACHED;
265 break; 268 break;
266 default: 269 default:
267 BUG(); 270 BUG();
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 321ae7261320..ab8cffe193cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -115,6 +115,7 @@
115 115
116#define GEN6_PTE_VALID (1 << 0) 116#define GEN6_PTE_VALID (1 << 0)
117#define GEN6_PTE_UNCACHED (1 << 1) 117#define GEN6_PTE_UNCACHED (1 << 1)
118#define HSW_PTE_UNCACHED (0)
118#define GEN6_PTE_CACHE_LLC (2 << 1) 119#define GEN6_PTE_CACHE_LLC (2 << 1)
119#define GEN6_PTE_CACHE_LLC_MLC (3 << 1) 120#define GEN6_PTE_CACHE_LLC_MLC (3 << 1)
120#define GEN6_PTE_CACHE_BITS (3 << 1) 121#define GEN6_PTE_CACHE_BITS (3 << 1)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index bc5e2c97db61..80bf3112dc1f 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -328,6 +328,36 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
328 return ret; 328 return ret;
329} 329}
330 330
331static struct edid *intel_crt_get_edid(struct drm_connector *connector,
332 struct i2c_adapter *i2c)
333{
334 struct edid *edid;
335
336 edid = drm_get_edid(connector, i2c);
337
338 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
339 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
340 intel_gmbus_force_bit(i2c, true);
341 edid = drm_get_edid(connector, i2c);
342 intel_gmbus_force_bit(i2c, false);
343 }
344
345 return edid;
346}
347
348/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
349static int intel_crt_ddc_get_modes(struct drm_connector *connector,
350 struct i2c_adapter *adapter)
351{
352 struct edid *edid;
353
354 edid = intel_crt_get_edid(connector, adapter);
355 if (!edid)
356 return 0;
357
358 return intel_connector_update_modes(connector, edid);
359}
360
331static bool intel_crt_detect_ddc(struct drm_connector *connector) 361static bool intel_crt_detect_ddc(struct drm_connector *connector)
332{ 362{
333 struct intel_crt *crt = intel_attached_crt(connector); 363 struct intel_crt *crt = intel_attached_crt(connector);
@@ -338,7 +368,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
338 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 368 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
339 369
340 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); 370 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
341 edid = drm_get_edid(connector, i2c); 371 edid = intel_crt_get_edid(connector, i2c);
342 372
343 if (edid) { 373 if (edid) {
344 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 374 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
@@ -546,13 +576,13 @@ static int intel_crt_get_modes(struct drm_connector *connector)
546 struct i2c_adapter *i2c; 576 struct i2c_adapter *i2c;
547 577
548 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin); 578 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
549 ret = intel_ddc_get_modes(connector, i2c); 579 ret = intel_crt_ddc_get_modes(connector, i2c);
550 if (ret || !IS_G4X(dev)) 580 if (ret || !IS_G4X(dev))
551 return ret; 581 return ret;
552 582
553 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 583 /* Try to probe digital port for output in DVI-I -> VGA mode. */
554 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); 584 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
555 return intel_ddc_get_modes(connector, i2c); 585 return intel_crt_ddc_get_modes(connector, i2c);
556} 586}
557 587
558static int intel_crt_set_property(struct drm_connector *connector, 588static int intel_crt_set_property(struct drm_connector *connector,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6920bc26a2e9..e86b3a20d70b 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -358,6 +358,8 @@ struct intel_fbc_work {
358 int interval; 358 int interval;
359}; 359};
360 360
361int intel_connector_update_modes(struct drm_connector *connector,
362 struct edid *edid);
361int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); 363int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
362 364
363extern void intel_attach_force_audio_property(struct drm_connector *connector); 365extern void intel_attach_force_audio_property(struct drm_connector *connector);
diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c
index 7a5238fc1a02..4bc1c0fc342a 100644
--- a/drivers/gpu/drm/i915/intel_modes.c
+++ b/drivers/gpu/drm/i915/intel_modes.c
@@ -33,6 +33,24 @@
33#include "i915_drv.h" 33#include "i915_drv.h"
34 34
35/** 35/**
36 * intel_connector_update_modes - update connector from edid
37 * @connector: DRM connector device to use
38 * @edid: previously read EDID information
39 */
40int intel_connector_update_modes(struct drm_connector *connector,
41 struct edid *edid)
42{
43 int ret;
44
45 drm_mode_connector_update_edid_property(connector, edid);
46 ret = drm_add_edid_modes(connector, edid);
47 drm_edid_to_eld(connector, edid);
48 kfree(edid);
49
50 return ret;
51}
52
53/**
36 * intel_ddc_get_modes - get modelist from monitor 54 * intel_ddc_get_modes - get modelist from monitor
37 * @connector: DRM connector device to use 55 * @connector: DRM connector device to use
38 * @adapter: i2c adapter 56 * @adapter: i2c adapter
@@ -43,17 +61,12 @@ int intel_ddc_get_modes(struct drm_connector *connector,
43 struct i2c_adapter *adapter) 61 struct i2c_adapter *adapter)
44{ 62{
45 struct edid *edid; 63 struct edid *edid;
46 int ret = 0;
47 64
48 edid = drm_get_edid(connector, adapter); 65 edid = drm_get_edid(connector, adapter);
49 if (edid) { 66 if (!edid)
50 drm_mode_connector_update_edid_property(connector, edid); 67 return 0;
51 ret = drm_add_edid_modes(connector, edid);
52 drm_edid_to_eld(connector, edid);
53 kfree(edid);
54 }
55 68
56 return ret; 69 return intel_connector_update_modes(connector, edid);
57} 70}
58 71
59static const struct drm_prop_enum_list force_audio_names[] = { 72static const struct drm_prop_enum_list force_audio_names[] = {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c0407aa5baac..9b05f7832dc2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2482,17 +2482,10 @@ static void gen6_enable_rps(struct drm_device *dev)
2482 dev_priv->rps.max_delay << 24 | 2482 dev_priv->rps.max_delay << 24 |
2483 dev_priv->rps.min_delay << 16); 2483 dev_priv->rps.min_delay << 16);
2484 2484
2485 if (IS_HASWELL(dev)) { 2485 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2486 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 2486 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2487 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 2487 I915_WRITE(GEN6_RP_UP_EI, 66000);
2488 I915_WRITE(GEN6_RP_UP_EI, 66000); 2488 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2489 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2490 } else {
2491 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
2492 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
2493 I915_WRITE(GEN6_RP_UP_EI, 100000);
2494 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
2495 }
2496 2489
2497 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2490 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2498 I915_WRITE(GEN6_RP_CONTROL, 2491 I915_WRITE(GEN6_RP_CONTROL,
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index fc841e87b343..26ebffebe710 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -211,11 +211,6 @@ static int nouveau_dsm_power_state(enum vga_switcheroo_client_id id,
211 return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dhandle, state); 211 return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dhandle, state);
212} 212}
213 213
214static int nouveau_dsm_init(void)
215{
216 return 0;
217}
218
219static int nouveau_dsm_get_client_id(struct pci_dev *pdev) 214static int nouveau_dsm_get_client_id(struct pci_dev *pdev)
220{ 215{
221 /* easy option one - intel vendor ID means Integrated */ 216 /* easy option one - intel vendor ID means Integrated */
@@ -232,7 +227,6 @@ static int nouveau_dsm_get_client_id(struct pci_dev *pdev)
232static struct vga_switcheroo_handler nouveau_dsm_handler = { 227static struct vga_switcheroo_handler nouveau_dsm_handler = {
233 .switchto = nouveau_dsm_switchto, 228 .switchto = nouveau_dsm_switchto,
234 .power_state = nouveau_dsm_power_state, 229 .power_state = nouveau_dsm_power_state,
235 .init = nouveau_dsm_init,
236 .get_client_id = nouveau_dsm_get_client_id, 230 .get_client_id = nouveau_dsm_get_client_id,
237}; 231};
238 232
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index c6fcb5b86a45..f4d4505fe831 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -444,11 +444,28 @@ union atom_enable_ss {
444static void atombios_crtc_program_ss(struct radeon_device *rdev, 444static void atombios_crtc_program_ss(struct radeon_device *rdev,
445 int enable, 445 int enable,
446 int pll_id, 446 int pll_id,
447 int crtc_id,
447 struct radeon_atom_ss *ss) 448 struct radeon_atom_ss *ss)
448{ 449{
450 unsigned i;
449 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 451 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
450 union atom_enable_ss args; 452 union atom_enable_ss args;
451 453
454 if (!enable) {
455 for (i = 0; i < rdev->num_crtc; i++) {
456 if (rdev->mode_info.crtcs[i] &&
457 rdev->mode_info.crtcs[i]->enabled &&
458 i != crtc_id &&
459 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
460 /* one other crtc is using this pll don't turn
461 * off spread spectrum as it might turn off
462 * display on active crtc
463 */
464 return;
465 }
466 }
467 }
468
452 memset(&args, 0, sizeof(args)); 469 memset(&args, 0, sizeof(args));
453 470
454 if (ASIC_IS_DCE5(rdev)) { 471 if (ASIC_IS_DCE5(rdev)) {
@@ -1028,7 +1045,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1028 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 1045 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1029 &ref_div, &post_div); 1046 &ref_div, &post_div);
1030 1047
1031 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, &ss); 1048 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1032 1049
1033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1050 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1034 encoder_mode, radeon_encoder->encoder_id, mode->clock, 1051 encoder_mode, radeon_encoder->encoder_id, mode->clock,
@@ -1051,7 +1068,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
1051 ss.step = step_size; 1068 ss.step = step_size;
1052 } 1069 }
1053 1070
1054 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, &ss); 1071 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1055 } 1072 }
1056} 1073}
1057 1074
@@ -1572,11 +1589,11 @@ void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1572 ASIC_INTERNAL_SS_ON_DCPLL, 1589 ASIC_INTERNAL_SS_ON_DCPLL,
1573 rdev->clock.default_dispclk); 1590 rdev->clock.default_dispclk);
1574 if (ss_enabled) 1591 if (ss_enabled)
1575 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss); 1592 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1576 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 1593 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1577 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 1594 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1578 if (ss_enabled) 1595 if (ss_enabled)
1579 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss); 1596 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1580 } 1597 }
1581 1598
1582} 1599}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 3dab49cb1d4a..ab74e6b149e7 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -47,13 +47,17 @@ struct r600_cs_track {
47 u32 npipes; 47 u32 npipes;
48 /* value we track */ 48 /* value we track */
49 u32 sq_config; 49 u32 sq_config;
50 u32 log_nsamples;
50 u32 nsamples; 51 u32 nsamples;
51 u32 cb_color_base_last[8]; 52 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8]; 53 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8]; 54 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8]; 55 u64 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8]; /* unused */ 56 struct radeon_bo *cb_color_frag_bo[8];
56 struct radeon_bo *cb_color_tile_bo[8]; /* unused */ 57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
57 u32 cb_color_info[8]; 61 u32 cb_color_info[8];
58 u32 cb_color_view[8]; 62 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; /* unused */ 63 u32 cb_color_size_idx[8]; /* unused */
@@ -349,10 +353,6 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
349 unsigned array_mode; 353 unsigned array_mode;
350 u32 format; 354 u32 format;
351 355
352 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
353 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
354 return -EINVAL;
355 }
356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357 format = G_0280A0_FORMAT(track->cb_color_info[i]); 357 format = G_0280A0_FORMAT(track->cb_color_info[i]);
358 if (!r600_fmt_is_valid_color(format)) { 358 if (!r600_fmt_is_valid_color(format)) {
@@ -420,7 +420,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
420 } 420 }
421 421
422 /* check offset */ 422 /* check offset */
423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format); 423 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
424 r600_fmt_get_blocksize(format) * track->nsamples;
424 switch (array_mode) { 425 switch (array_mode) {
425 default: 426 default:
426 case V_0280A0_ARRAY_LINEAR_GENERAL: 427 case V_0280A0_ARRAY_LINEAR_GENERAL:
@@ -441,7 +442,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
441 * broken userspace. 442 * broken userspace.
442 */ 443 */
443 } else { 444 } else {
444 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n", 445 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
445 __func__, i, array_mode, 446 __func__, i, array_mode,
446 track->cb_color_bo_offset[i], tmp, 447 track->cb_color_bo_offset[i], tmp,
447 radeon_bo_size(track->cb_color_bo[i]), 448 radeon_bo_size(track->cb_color_bo[i]),
@@ -458,6 +459,51 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 459 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
459 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 460 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
460 ib[track->cb_color_size_idx[i]] = tmp; 461 ib[track->cb_color_size_idx[i]] = tmp;
462
463 /* FMASK/CMASK */
464 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
465 case V_0280A0_TILE_DISABLE:
466 break;
467 case V_0280A0_FRAG_ENABLE:
468 if (track->nsamples > 1) {
469 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
470 /* the tile size is 8x8, but the size is in units of bits.
471 * for bytes, do just * 8. */
472 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
473
474 if (bytes + track->cb_color_frag_offset[i] >
475 radeon_bo_size(track->cb_color_frag_bo[i])) {
476 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
477 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
478 __func__, tile_max, bytes,
479 track->cb_color_frag_offset[i],
480 radeon_bo_size(track->cb_color_frag_bo[i]));
481 return -EINVAL;
482 }
483 }
484 /* fall through */
485 case V_0280A0_CLEAR_ENABLE:
486 {
487 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
488 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
489 * (128*128) / (8*8) / 2 = 128 bytes per block. */
490 uint32_t bytes = (block_max + 1) * 128;
491
492 if (bytes + track->cb_color_tile_offset[i] >
493 radeon_bo_size(track->cb_color_tile_bo[i])) {
494 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
495 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
496 __func__, block_max, bytes,
497 track->cb_color_tile_offset[i],
498 radeon_bo_size(track->cb_color_tile_bo[i]));
499 return -EINVAL;
500 }
501 break;
502 }
503 default:
504 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
505 return -EINVAL;
506 }
461 return 0; 507 return 0;
462} 508}
463 509
@@ -566,7 +612,7 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
566 612
567 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1; 613 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
568 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; 614 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
569 tmp = ntiles * bpe * 64 * nviews; 615 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
570 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { 616 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
571 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", 617 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
572 array_mode, 618 array_mode,
@@ -1231,6 +1277,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1231 break; 1277 break;
1232 case R_028C04_PA_SC_AA_CONFIG: 1278 case R_028C04_PA_SC_AA_CONFIG:
1233 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1279 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1280 track->log_nsamples = tmp;
1234 track->nsamples = 1 << tmp; 1281 track->nsamples = 1 << tmp;
1235 track->cb_dirty = true; 1282 track->cb_dirty = true;
1236 break; 1283 break;
@@ -1312,16 +1359,21 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1312 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1359 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1313 return -EINVAL; 1360 return -EINVAL;
1314 } 1361 }
1315 ib[idx] = track->cb_color_base_last[tmp];
1316 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1362 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1363 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1364 ib[idx] = track->cb_color_base_last[tmp];
1317 } else { 1365 } else {
1318 r = r600_cs_packet_next_reloc(p, &reloc); 1366 r = r600_cs_packet_next_reloc(p, &reloc);
1319 if (r) { 1367 if (r) {
1320 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1368 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1321 return -EINVAL; 1369 return -EINVAL;
1322 } 1370 }
1323 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1324 track->cb_color_frag_bo[tmp] = reloc->robj; 1371 track->cb_color_frag_bo[tmp] = reloc->robj;
1372 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1373 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1374 }
1375 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1376 track->cb_dirty = true;
1325 } 1377 }
1326 break; 1378 break;
1327 case R_0280C0_CB_COLOR0_TILE: 1379 case R_0280C0_CB_COLOR0_TILE:
@@ -1338,16 +1390,35 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1338 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1390 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1339 return -EINVAL; 1391 return -EINVAL;
1340 } 1392 }
1341 ib[idx] = track->cb_color_base_last[tmp];
1342 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1393 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1394 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1395 ib[idx] = track->cb_color_base_last[tmp];
1343 } else { 1396 } else {
1344 r = r600_cs_packet_next_reloc(p, &reloc); 1397 r = r600_cs_packet_next_reloc(p, &reloc);
1345 if (r) { 1398 if (r) {
1346 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1399 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1347 return -EINVAL; 1400 return -EINVAL;
1348 } 1401 }
1349 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1350 track->cb_color_tile_bo[tmp] = reloc->robj; 1402 track->cb_color_tile_bo[tmp] = reloc->robj;
1403 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1404 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1405 }
1406 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1407 track->cb_dirty = true;
1408 }
1409 break;
1410 case R_028100_CB_COLOR0_MASK:
1411 case R_028104_CB_COLOR1_MASK:
1412 case R_028108_CB_COLOR2_MASK:
1413 case R_02810C_CB_COLOR3_MASK:
1414 case R_028110_CB_COLOR4_MASK:
1415 case R_028114_CB_COLOR5_MASK:
1416 case R_028118_CB_COLOR6_MASK:
1417 case R_02811C_CB_COLOR7_MASK:
1418 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1419 track->cb_color_mask[tmp] = ib[idx];
1420 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1421 track->cb_dirty = true;
1351 } 1422 }
1352 break; 1423 break;
1353 case CB_COLOR0_BASE: 1424 case CB_COLOR0_BASE:
@@ -1492,7 +1563,7 @@ unsigned r600_mip_minify(unsigned size, unsigned level)
1492} 1563}
1493 1564
1494static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, 1565static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1495 unsigned w0, unsigned h0, unsigned d0, unsigned format, 1566 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1496 unsigned block_align, unsigned height_align, unsigned base_align, 1567 unsigned block_align, unsigned height_align, unsigned base_align,
1497 unsigned *l0_size, unsigned *mipmap_size) 1568 unsigned *l0_size, unsigned *mipmap_size)
1498{ 1569{
@@ -1520,7 +1591,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1520 1591
1521 depth = r600_mip_minify(d0, i); 1592 depth = r600_mip_minify(d0, i);
1522 1593
1523 size = nbx * nby * blocksize; 1594 size = nbx * nby * blocksize * nsamples;
1524 if (nfaces) 1595 if (nfaces)
1525 size *= nfaces; 1596 size *= nfaces;
1526 else 1597 else
@@ -1672,7 +1743,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1672 1743
1673 nfaces = larray - barray + 1; 1744 nfaces = larray - barray + 1;
1674 } 1745 }
1675 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format, 1746 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1676 pitch_align, height_align, base_align, 1747 pitch_align, height_align, base_align,
1677 &l0_size, &mipmap_size); 1748 &l0_size, &mipmap_size);
1678 /* using get ib will give us the offset into the texture bo */ 1749 /* using get ib will give us the offset into the texture bo */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index fd328f4c3ea8..bdb69a63062f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -92,6 +92,20 @@
92#define R_028094_CB_COLOR5_VIEW 0x028094 92#define R_028094_CB_COLOR5_VIEW 0x028094
93#define R_028098_CB_COLOR6_VIEW 0x028098 93#define R_028098_CB_COLOR6_VIEW 0x028098
94#define R_02809C_CB_COLOR7_VIEW 0x02809C 94#define R_02809C_CB_COLOR7_VIEW 0x02809C
95#define R_028100_CB_COLOR0_MASK 0x028100
96#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
97#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
98#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
99#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
100#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
101#define C_028100_FMASK_TILE_MAX 0x00000FFF
102#define R_028104_CB_COLOR1_MASK 0x028104
103#define R_028108_CB_COLOR2_MASK 0x028108
104#define R_02810C_CB_COLOR3_MASK 0x02810C
105#define R_028110_CB_COLOR4_MASK 0x028110
106#define R_028114_CB_COLOR5_MASK 0x028114
107#define R_028118_CB_COLOR6_MASK 0x028118
108#define R_02811C_CB_COLOR7_MASK 0x02811C
95#define CB_COLOR0_INFO 0x280a0 109#define CB_COLOR0_INFO 0x280a0
96# define CB_FORMAT(x) ((x) << 2) 110# define CB_FORMAT(x) ((x) << 2)
97# define CB_ARRAY_MODE(x) ((x) << 8) 111# define CB_ARRAY_MODE(x) ((x) << 8)
@@ -1400,6 +1414,9 @@
1400#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1414#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1401#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1415#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1402#define C_0280A0_TILE_MODE 0xFFF3FFFF 1416#define C_0280A0_TILE_MODE 0xFFF3FFFF
1417#define V_0280A0_TILE_DISABLE 0
1418#define V_0280A0_CLEAR_ENABLE 1
1419#define V_0280A0_FRAG_ENABLE 2
1403#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1420#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1404#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1421#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1405#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1422#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 99304194a65c..59a15315ae9f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -142,21 +142,6 @@ struct radeon_device;
142/* 142/*
143 * BIOS. 143 * BIOS.
144 */ 144 */
145#define ATRM_BIOS_PAGE 4096
146
147#if defined(CONFIG_VGA_SWITCHEROO)
148bool radeon_atrm_supported(struct pci_dev *pdev);
149int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
150#else
151static inline bool radeon_atrm_supported(struct pci_dev *pdev)
152{
153 return false;
154}
155
156static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
157 return -EINVAL;
158}
159#endif
160bool radeon_get_bios(struct radeon_device *rdev); 145bool radeon_get_bios(struct radeon_device *rdev);
161 146
162/* 147/*
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f9c21f9d16bc..d67d4f3eb6f4 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -452,7 +452,7 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
452 } 452 }
453 453
454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */ 454 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
455 if ((dev->pdev->device == 0x9802) && 455 if (((dev->pdev->device == 0x9802) || (dev->pdev->device == 0x9806)) &&
456 (dev->pdev->subsystem_vendor == 0x1734) && 456 (dev->pdev->subsystem_vendor == 0x1734) &&
457 (dev->pdev->subsystem_device == 0x11bd)) { 457 (dev->pdev->subsystem_device == 0x11bd)) {
458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) { 458 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 98724fcb0088..2a2cf0b88a28 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -30,57 +30,8 @@ static struct radeon_atpx_priv {
30 /* handle for device - and atpx */ 30 /* handle for device - and atpx */
31 acpi_handle dhandle; 31 acpi_handle dhandle;
32 acpi_handle atpx_handle; 32 acpi_handle atpx_handle;
33 acpi_handle atrm_handle;
34} radeon_atpx_priv; 33} radeon_atpx_priv;
35 34
36/* retrieve the ROM in 4k blocks */
37static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
38 int offset, int len)
39{
40 acpi_status status;
41 union acpi_object atrm_arg_elements[2], *obj;
42 struct acpi_object_list atrm_arg;
43 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
44
45 atrm_arg.count = 2;
46 atrm_arg.pointer = &atrm_arg_elements[0];
47
48 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
49 atrm_arg_elements[0].integer.value = offset;
50
51 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
52 atrm_arg_elements[1].integer.value = len;
53
54 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
55 if (ACPI_FAILURE(status)) {
56 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
57 return -ENODEV;
58 }
59
60 obj = (union acpi_object *)buffer.pointer;
61 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
62 len = obj->buffer.length;
63 kfree(buffer.pointer);
64 return len;
65}
66
67bool radeon_atrm_supported(struct pci_dev *pdev)
68{
69 /* get the discrete ROM only via ATRM */
70 if (!radeon_atpx_priv.atpx_detected)
71 return false;
72
73 if (radeon_atpx_priv.dhandle == DEVICE_ACPI_HANDLE(&pdev->dev))
74 return false;
75 return true;
76}
77
78
79int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len)
80{
81 return radeon_atrm_call(radeon_atpx_priv.atrm_handle, bios, offset, len);
82}
83
84static int radeon_atpx_get_version(acpi_handle handle) 35static int radeon_atpx_get_version(acpi_handle handle)
85{ 36{
86 acpi_status status; 37 acpi_status status;
@@ -198,7 +149,7 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
198 149
199static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev) 150static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
200{ 151{
201 acpi_handle dhandle, atpx_handle, atrm_handle; 152 acpi_handle dhandle, atpx_handle;
202 acpi_status status; 153 acpi_status status;
203 154
204 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); 155 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
@@ -209,13 +160,8 @@ static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
209 if (ACPI_FAILURE(status)) 160 if (ACPI_FAILURE(status))
210 return false; 161 return false;
211 162
212 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
213 if (ACPI_FAILURE(status))
214 return false;
215
216 radeon_atpx_priv.dhandle = dhandle; 163 radeon_atpx_priv.dhandle = dhandle;
217 radeon_atpx_priv.atpx_handle = atpx_handle; 164 radeon_atpx_priv.atpx_handle = atpx_handle;
218 radeon_atpx_priv.atrm_handle = atrm_handle;
219 return true; 165 return true;
220} 166}
221 167
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 501f4881e5aa..d306cc8fdeaa 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -32,6 +32,7 @@
32 32
33#include <linux/vga_switcheroo.h> 33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h> 34#include <linux/slab.h>
35#include <linux/acpi.h>
35/* 36/*
36 * BIOS. 37 * BIOS.
37 */ 38 */
@@ -98,16 +99,81 @@ static bool radeon_read_bios(struct radeon_device *rdev)
98 return true; 99 return true;
99} 100}
100 101
102#ifdef CONFIG_ACPI
101/* ATRM is used to get the BIOS on the discrete cards in 103/* ATRM is used to get the BIOS on the discrete cards in
102 * dual-gpu systems. 104 * dual-gpu systems.
103 */ 105 */
106/* retrieve the ROM in 4k blocks */
107#define ATRM_BIOS_PAGE 4096
108/**
109 * radeon_atrm_call - fetch a chunk of the vbios
110 *
111 * @atrm_handle: acpi ATRM handle
112 * @bios: vbios image pointer
113 * @offset: offset of vbios image data to fetch
114 * @len: length of vbios image data to fetch
115 *
116 * Executes ATRM to fetch a chunk of the discrete
117 * vbios image on PX systems (all asics).
118 * Returns the length of the buffer fetched.
119 */
120static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
121 int offset, int len)
122{
123 acpi_status status;
124 union acpi_object atrm_arg_elements[2], *obj;
125 struct acpi_object_list atrm_arg;
126 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
127
128 atrm_arg.count = 2;
129 atrm_arg.pointer = &atrm_arg_elements[0];
130
131 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
132 atrm_arg_elements[0].integer.value = offset;
133
134 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
135 atrm_arg_elements[1].integer.value = len;
136
137 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
138 if (ACPI_FAILURE(status)) {
139 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
140 return -ENODEV;
141 }
142
143 obj = (union acpi_object *)buffer.pointer;
144 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
145 len = obj->buffer.length;
146 kfree(buffer.pointer);
147 return len;
148}
149
104static bool radeon_atrm_get_bios(struct radeon_device *rdev) 150static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{ 151{
106 int ret; 152 int ret;
107 int size = 256 * 1024; 153 int size = 256 * 1024;
108 int i; 154 int i;
155 struct pci_dev *pdev = NULL;
156 acpi_handle dhandle, atrm_handle;
157 acpi_status status;
158 bool found = false;
159
160 /* ATRM is for the discrete card only */
161 if (rdev->flags & RADEON_IS_IGP)
162 return false;
163
164 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
165 dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
166 if (!dhandle)
167 continue;
168
169 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
170 if (!ACPI_FAILURE(status)) {
171 found = true;
172 break;
173 }
174 }
109 175
110 if (!radeon_atrm_supported(rdev->pdev)) 176 if (!found)
111 return false; 177 return false;
112 178
113 rdev->bios = kmalloc(size, GFP_KERNEL); 179 rdev->bios = kmalloc(size, GFP_KERNEL);
@@ -117,9 +183,10 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
117 } 183 }
118 184
119 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) { 185 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
120 ret = radeon_atrm_get_bios_chunk(rdev->bios, 186 ret = radeon_atrm_call(atrm_handle,
121 (i * ATRM_BIOS_PAGE), 187 rdev->bios,
122 ATRM_BIOS_PAGE); 188 (i * ATRM_BIOS_PAGE),
189 ATRM_BIOS_PAGE);
123 if (ret < ATRM_BIOS_PAGE) 190 if (ret < ATRM_BIOS_PAGE)
124 break; 191 break;
125 } 192 }
@@ -130,6 +197,12 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
130 } 197 }
131 return true; 198 return true;
132} 199}
200#else
201static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
202{
203 return false;
204}
205#endif
133 206
134static bool ni_read_disabled_bios(struct radeon_device *rdev) 207static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{ 208{
@@ -476,6 +549,61 @@ static bool radeon_read_disabled_bios(struct radeon_device *rdev)
476 return legacy_read_disabled_bios(rdev); 549 return legacy_read_disabled_bios(rdev);
477} 550}
478 551
552#ifdef CONFIG_ACPI
553static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
554{
555 bool ret = false;
556 struct acpi_table_header *hdr;
557 acpi_size tbl_size;
558 UEFI_ACPI_VFCT *vfct;
559 GOP_VBIOS_CONTENT *vbios;
560 VFCT_IMAGE_HEADER *vhdr;
561
562 if (!ACPI_SUCCESS(acpi_get_table_with_size("VFCT", 1, &hdr, &tbl_size)))
563 return false;
564 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
565 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
566 goto out_unmap;
567 }
568
569 vfct = (UEFI_ACPI_VFCT *)hdr;
570 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) > tbl_size) {
571 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
572 goto out_unmap;
573 }
574
575 vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + vfct->VBIOSImageOffset);
576 vhdr = &vbios->VbiosHeader;
577 DRM_INFO("ACPI VFCT contains a BIOS for %02x:%02x.%d %04x:%04x, size %d\n",
578 vhdr->PCIBus, vhdr->PCIDevice, vhdr->PCIFunction,
579 vhdr->VendorID, vhdr->DeviceID, vhdr->ImageLength);
580
581 if (vhdr->PCIBus != rdev->pdev->bus->number ||
582 vhdr->PCIDevice != PCI_SLOT(rdev->pdev->devfn) ||
583 vhdr->PCIFunction != PCI_FUNC(rdev->pdev->devfn) ||
584 vhdr->VendorID != rdev->pdev->vendor ||
585 vhdr->DeviceID != rdev->pdev->device) {
586 DRM_INFO("ACPI VFCT table is not for this card\n");
587 goto out_unmap;
588 };
589
590 if (vfct->VBIOSImageOffset + sizeof(VFCT_IMAGE_HEADER) + vhdr->ImageLength > tbl_size) {
591 DRM_ERROR("ACPI VFCT image truncated\n");
592 goto out_unmap;
593 }
594
595 rdev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
596 ret = !!rdev->bios;
597
598out_unmap:
599 return ret;
600}
601#else
602static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
603{
604 return false;
605}
606#endif
479 607
480bool radeon_get_bios(struct radeon_device *rdev) 608bool radeon_get_bios(struct radeon_device *rdev)
481{ 609{
@@ -484,6 +612,8 @@ bool radeon_get_bios(struct radeon_device *rdev)
484 612
485 r = radeon_atrm_get_bios(rdev); 613 r = radeon_atrm_get_bios(rdev);
486 if (r == false) 614 if (r == false)
615 r = radeon_acpi_vfct_bios(rdev);
616 if (r == false)
487 r = igp_read_bios_from_vram(rdev); 617 r = igp_read_bios_from_vram(rdev);
488 if (r == false) 618 if (r == false)
489 r = radeon_read_bios(rdev); 619 r = radeon_read_bios(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index d7269f48d37c..27d22d709c90 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -62,9 +62,10 @@
62 * 2.18.0 - r600-eg: allow "invalid" DB formats 62 * 2.18.0 - r600-eg: allow "invalid" DB formats
63 * 2.19.0 - r600-eg: MSAA textures 63 * 2.19.0 - r600-eg: MSAA textures
64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
65 * 2.21.0 - r600-r700: FMASK and CMASK
65 */ 66 */
66#define KMS_DRIVER_MAJOR 2 67#define KMS_DRIVER_MAJOR 2
67#define KMS_DRIVER_MINOR 20 68#define KMS_DRIVER_MINOR 21
68#define KMS_DRIVER_PATCHLEVEL 0 69#define KMS_DRIVER_PATCHLEVEL 0
69int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 70int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
70int radeon_driver_unload_kms(struct drm_device *dev); 71int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 1cb014b571ab..9024e7222839 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -132,6 +132,7 @@ int radeon_bo_create(struct radeon_device *rdev,
132 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size, 132 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
133 sizeof(struct radeon_bo)); 133 sizeof(struct radeon_bo));
134 134
135retry:
135 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 136 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
136 if (bo == NULL) 137 if (bo == NULL)
137 return -ENOMEM; 138 return -ENOMEM;
@@ -145,8 +146,6 @@ int radeon_bo_create(struct radeon_device *rdev,
145 bo->surface_reg = -1; 146 bo->surface_reg = -1;
146 INIT_LIST_HEAD(&bo->list); 147 INIT_LIST_HEAD(&bo->list);
147 INIT_LIST_HEAD(&bo->va); 148 INIT_LIST_HEAD(&bo->va);
148
149retry:
150 radeon_ttm_placement_from_domain(bo, domain); 149 radeon_ttm_placement_from_domain(bo, domain);
151 /* Kernel allocation are uninterruptible */ 150 /* Kernel allocation are uninterruptible */
152 down_read(&rdev->pm.mclk_lock); 151 down_read(&rdev->pm.mclk_lock);
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index ec79b3750430..43c431a2686d 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -706,6 +706,7 @@ int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsig
706 if (radeon_debugfs_ring_init(rdev, ring)) { 706 if (radeon_debugfs_ring_init(rdev, ring)) {
707 DRM_ERROR("Failed to register debugfs file for rings !\n"); 707 DRM_ERROR("Failed to register debugfs file for rings !\n");
708 } 708 }
709 radeon_ring_lockup_update(ring);
709 return 0; 710 return 0;
710} 711}
711 712
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 5e659b034d9a..f93e45d869f4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -744,14 +744,6 @@ r600 0x9400
7440x00028C38 CB_CLRCMP_DST 7440x00028C38 CB_CLRCMP_DST
7450x00028C3C CB_CLRCMP_MSK 7450x00028C3C CB_CLRCMP_MSK
7460x00028C34 CB_CLRCMP_SRC 7460x00028C34 CB_CLRCMP_SRC
7470x00028100 CB_COLOR0_MASK
7480x00028104 CB_COLOR1_MASK
7490x00028108 CB_COLOR2_MASK
7500x0002810C CB_COLOR3_MASK
7510x00028110 CB_COLOR4_MASK
7520x00028114 CB_COLOR5_MASK
7530x00028118 CB_COLOR6_MASK
7540x0002811C CB_COLOR7_MASK
7550x00028808 CB_COLOR_CONTROL 7470x00028808 CB_COLOR_CONTROL
7560x0002842C CB_FOG_BLUE 7480x0002842C CB_FOG_BLUE
7570x00028428 CB_FOG_GREEN 7490x00028428 CB_FOG_GREEN
diff --git a/drivers/gpu/drm/udl/Kconfig b/drivers/gpu/drm/udl/Kconfig
index 0b5e096d39a6..56e0bf31d425 100644
--- a/drivers/gpu/drm/udl/Kconfig
+++ b/drivers/gpu/drm/udl/Kconfig
@@ -1,6 +1,7 @@
1config DRM_UDL 1config DRM_UDL
2 tristate "DisplayLink" 2 tristate "DisplayLink"
3 depends on DRM && EXPERIMENTAL 3 depends on DRM && EXPERIMENTAL
4 depends on USB_ARCH_HAS_HCD
4 select DRM_USB 5 select DRM_USB
5 select FB_SYS_FILLRECT 6 select FB_SYS_FILLRECT
6 select FB_SYS_COPYAREA 7 select FB_SYS_COPYAREA
diff --git a/drivers/gpu/drm/udl/udl_modeset.c b/drivers/gpu/drm/udl/udl_modeset.c
index f5dd89e891de..9159d48d1dfd 100644
--- a/drivers/gpu/drm/udl/udl_modeset.c
+++ b/drivers/gpu/drm/udl/udl_modeset.c
@@ -354,8 +354,7 @@ static int udl_crtc_mode_set(struct drm_crtc *crtc,
354 354
355static void udl_crtc_disable(struct drm_crtc *crtc) 355static void udl_crtc_disable(struct drm_crtc *crtc)
356{ 356{
357 357 udl_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
358
359} 358}
360 359
361static void udl_crtc_destroy(struct drm_crtc *crtc) 360static void udl_crtc_destroy(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 6b0078ffa763..c50724bd30f6 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -1688,15 +1688,19 @@ int vmw_du_page_flip(struct drm_crtc *crtc,
1688 struct vmw_private *dev_priv = vmw_priv(crtc->dev); 1688 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1689 struct drm_framebuffer *old_fb = crtc->fb; 1689 struct drm_framebuffer *old_fb = crtc->fb;
1690 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(fb); 1690 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(fb);
1691 struct drm_file *file_priv = event->base.file_priv; 1691 struct drm_file *file_priv ;
1692 struct vmw_fence_obj *fence = NULL; 1692 struct vmw_fence_obj *fence = NULL;
1693 struct drm_clip_rect clips; 1693 struct drm_clip_rect clips;
1694 int ret; 1694 int ret;
1695 1695
1696 if (event == NULL)
1697 return -EINVAL;
1698
1696 /* require ScreenObject support for page flipping */ 1699 /* require ScreenObject support for page flipping */
1697 if (!dev_priv->sou_priv) 1700 if (!dev_priv->sou_priv)
1698 return -ENOSYS; 1701 return -ENOSYS;
1699 1702
1703 file_priv = event->base.file_priv;
1700 if (!vmw_kms_screen_object_flippable(dev_priv, crtc)) 1704 if (!vmw_kms_screen_object_flippable(dev_priv, crtc))
1701 return -EINVAL; 1705 return -EINVAL;
1702 1706
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 5b3c7d135dc9..e25cf31faab2 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -70,27 +70,12 @@ static struct vgasr_priv vgasr_priv = {
70 .clients = LIST_HEAD_INIT(vgasr_priv.clients), 70 .clients = LIST_HEAD_INIT(vgasr_priv.clients),
71}; 71};
72 72
73int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler) 73static bool vga_switcheroo_ready(void)
74{
75 mutex_lock(&vgasr_mutex);
76 if (vgasr_priv.handler) {
77 mutex_unlock(&vgasr_mutex);
78 return -EINVAL;
79 }
80
81 vgasr_priv.handler = handler;
82 mutex_unlock(&vgasr_mutex);
83 return 0;
84}
85EXPORT_SYMBOL(vga_switcheroo_register_handler);
86
87void vga_switcheroo_unregister_handler(void)
88{ 74{
89 mutex_lock(&vgasr_mutex); 75 /* we're ready if we get two clients + handler */
90 vgasr_priv.handler = NULL; 76 return !vgasr_priv.active &&
91 mutex_unlock(&vgasr_mutex); 77 vgasr_priv.registered_clients == 2 && vgasr_priv.handler;
92} 78}
93EXPORT_SYMBOL(vga_switcheroo_unregister_handler);
94 79
95static void vga_switcheroo_enable(void) 80static void vga_switcheroo_enable(void)
96{ 81{
@@ -98,7 +83,8 @@ static void vga_switcheroo_enable(void)
98 struct vga_switcheroo_client *client; 83 struct vga_switcheroo_client *client;
99 84
100 /* call the handler to init */ 85 /* call the handler to init */
101 vgasr_priv.handler->init(); 86 if (vgasr_priv.handler->init)
87 vgasr_priv.handler->init();
102 88
103 list_for_each_entry(client, &vgasr_priv.clients, list) { 89 list_for_each_entry(client, &vgasr_priv.clients, list) {
104 if (client->id != -1) 90 if (client->id != -1)
@@ -113,6 +99,37 @@ static void vga_switcheroo_enable(void)
113 vgasr_priv.active = true; 99 vgasr_priv.active = true;
114} 100}
115 101
102int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler)
103{
104 mutex_lock(&vgasr_mutex);
105 if (vgasr_priv.handler) {
106 mutex_unlock(&vgasr_mutex);
107 return -EINVAL;
108 }
109
110 vgasr_priv.handler = handler;
111 if (vga_switcheroo_ready()) {
112 printk(KERN_INFO "vga_switcheroo: enabled\n");
113 vga_switcheroo_enable();
114 }
115 mutex_unlock(&vgasr_mutex);
116 return 0;
117}
118EXPORT_SYMBOL(vga_switcheroo_register_handler);
119
120void vga_switcheroo_unregister_handler(void)
121{
122 mutex_lock(&vgasr_mutex);
123 vgasr_priv.handler = NULL;
124 if (vgasr_priv.active) {
125 pr_info("vga_switcheroo: disabled\n");
126 vga_switcheroo_debugfs_fini(&vgasr_priv);
127 vgasr_priv.active = false;
128 }
129 mutex_unlock(&vgasr_mutex);
130}
131EXPORT_SYMBOL(vga_switcheroo_unregister_handler);
132
116static int register_client(struct pci_dev *pdev, 133static int register_client(struct pci_dev *pdev,
117 const struct vga_switcheroo_client_ops *ops, 134 const struct vga_switcheroo_client_ops *ops,
118 int id, bool active) 135 int id, bool active)
@@ -134,9 +151,7 @@ static int register_client(struct pci_dev *pdev,
134 if (client_is_vga(client)) 151 if (client_is_vga(client))
135 vgasr_priv.registered_clients++; 152 vgasr_priv.registered_clients++;
136 153
137 /* if we get two clients + handler */ 154 if (vga_switcheroo_ready()) {
138 if (!vgasr_priv.active &&
139 vgasr_priv.registered_clients == 2 && vgasr_priv.handler) {
140 printk(KERN_INFO "vga_switcheroo: enabled\n"); 155 printk(KERN_INFO "vga_switcheroo: enabled\n");
141 vga_switcheroo_enable(); 156 vga_switcheroo_enable();
142 } 157 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-19 11:47:38 -0500