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authorJens Axboe <axboe@kernel.dk>2012-07-30 03:03:10 -0400
committerJens Axboe <axboe@kernel.dk>2012-07-30 03:03:10 -0400
commit72ea1f74fcdf874cca6d2c0962379523bbd99e2c (patch)
tree4c67be6c73356086ff44ef1b8b1c9479702689ca /drivers/gpu
parentb1af9be5ef77898c05667bb9dbf3b180d91d3292 (diff)
parenta73ff3231df59a4b92ccd0dd4e73897c5822489b (diff)
Merge branch 'for-jens' of git://git.drbd.org/linux-drbd into for-3.6/drivers
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/drm_edid.c29
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.c4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_encoder.c7
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fb.c19
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fb.h4
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gem.c9
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c12
-rw-r--r--drivers/gpu/drm/gma500/cdv_device.c35
-rw-r--r--drivers/gpu/drm/gma500/opregion.c8
-rw-r--r--drivers/gpu/drm/gma500/opregion.h5
-rw-r--r--drivers/gpu/drm/gma500/psb_device.c12
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.c1
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c37
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c13
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c39
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h43
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c37
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c60
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c21
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fbcon.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_prime.c23
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c10
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c4
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c49
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c3
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
-rw-r--r--drivers/gpu/drm/radeon/ni.c26
-rw-r--r--drivers/gpu/drm/radeon/r600.c16
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c7
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c42
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c8
-rw-r--r--drivers/gpu/drm/radeon/r600d.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c32
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_prime.c10
-rw-r--r--drivers/gpu/drm/radeon/rs600.c12
-rw-r--r--drivers/gpu/drm/radeon/rs690.c12
-rw-r--r--drivers/gpu/drm/radeon/rv770.c23
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h3
-rw-r--r--drivers/gpu/drm/radeon/si.c481
-rw-r--r--drivers/gpu/drm/radeon/si_reg.h72
-rw-r--r--drivers/gpu/drm/radeon/sid.h19
-rw-r--r--drivers/gpu/drm/sis/sis_drv.c2
-rw-r--r--drivers/gpu/drm/ttm/ttm_bo.c13
-rw-r--r--drivers/gpu/drm/udl/udl_drv.c15
-rw-r--r--drivers/gpu/drm/udl/udl_main.c2
-rw-r--r--drivers/gpu/drm/via/via_map.c3
-rw-r--r--drivers/gpu/vga/vga_switcheroo.c27
55 files changed, 831 insertions, 525 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index eb92fe257a39..a8743c399e83 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -610,7 +610,7 @@ static bool
610drm_monitor_supports_rb(struct edid *edid) 610drm_monitor_supports_rb(struct edid *edid)
611{ 611{
612 if (edid->revision >= 4) { 612 if (edid->revision >= 4) {
613 bool ret; 613 bool ret = false;
614 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 614 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
615 return ret; 615 return ret;
616 } 616 }
@@ -1039,6 +1039,24 @@ mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
1039 return true; 1039 return true;
1040} 1040}
1041 1041
1042static bool valid_inferred_mode(const struct drm_connector *connector,
1043 const struct drm_display_mode *mode)
1044{
1045 struct drm_display_mode *m;
1046 bool ok = false;
1047
1048 list_for_each_entry(m, &connector->probed_modes, head) {
1049 if (mode->hdisplay == m->hdisplay &&
1050 mode->vdisplay == m->vdisplay &&
1051 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
1052 return false; /* duplicated */
1053 if (mode->hdisplay <= m->hdisplay &&
1054 mode->vdisplay <= m->vdisplay)
1055 ok = true;
1056 }
1057 return ok;
1058}
1059
1042static int 1060static int
1043drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1061drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
1044 struct detailed_timing *timing) 1062 struct detailed_timing *timing)
@@ -1048,7 +1066,8 @@ drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
1048 struct drm_device *dev = connector->dev; 1066 struct drm_device *dev = connector->dev;
1049 1067
1050 for (i = 0; i < drm_num_dmt_modes; i++) { 1068 for (i = 0; i < drm_num_dmt_modes; i++) {
1051 if (mode_in_range(drm_dmt_modes + i, edid, timing)) { 1069 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
1070 valid_inferred_mode(connector, drm_dmt_modes + i)) {
1052 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1071 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
1053 if (newmode) { 1072 if (newmode) {
1054 drm_mode_probed_add(connector, newmode); 1073 drm_mode_probed_add(connector, newmode);
@@ -1088,7 +1107,8 @@ drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
1088 return modes; 1107 return modes;
1089 1108
1090 fixup_mode_1366x768(newmode); 1109 fixup_mode_1366x768(newmode);
1091 if (!mode_in_range(newmode, edid, timing)) { 1110 if (!mode_in_range(newmode, edid, timing) ||
1111 !valid_inferred_mode(connector, newmode)) {
1092 drm_mode_destroy(dev, newmode); 1112 drm_mode_destroy(dev, newmode);
1093 continue; 1113 continue;
1094 } 1114 }
@@ -1116,7 +1136,8 @@ drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
1116 return modes; 1136 return modes;
1117 1137
1118 fixup_mode_1366x768(newmode); 1138 fixup_mode_1366x768(newmode);
1119 if (!mode_in_range(newmode, edid, timing)) { 1139 if (!mode_in_range(newmode, edid, timing) ||
1140 !valid_inferred_mode(connector, newmode)) {
1120 drm_mode_destroy(dev, newmode); 1141 drm_mode_destroy(dev, newmode);
1121 continue; 1142 continue;
1122 } 1143 }
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 420953197d0a..d6de2e07fa03 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -244,8 +244,8 @@ static const struct file_operations exynos_drm_driver_fops = {
244}; 244};
245 245
246static struct drm_driver exynos_drm_driver = { 246static struct drm_driver exynos_drm_driver = {
247 .driver_features = DRIVER_HAVE_IRQ | DRIVER_BUS_PLATFORM | 247 .driver_features = DRIVER_HAVE_IRQ | DRIVER_MODESET |
248 DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME, 248 DRIVER_GEM | DRIVER_PRIME,
249 .load = exynos_drm_load, 249 .load = exynos_drm_load,
250 .unload = exynos_drm_unload, 250 .unload = exynos_drm_unload,
251 .open = exynos_drm_open, 251 .open = exynos_drm_open,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
index 6e9ac7bd1dcf..23d5ad379f86 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c
@@ -172,19 +172,12 @@ static void exynos_drm_encoder_commit(struct drm_encoder *encoder)
172 manager_ops->commit(manager->dev); 172 manager_ops->commit(manager->dev);
173} 173}
174 174
175static struct drm_crtc *
176exynos_drm_encoder_get_crtc(struct drm_encoder *encoder)
177{
178 return encoder->crtc;
179}
180
181static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = { 175static struct drm_encoder_helper_funcs exynos_encoder_helper_funcs = {
182 .dpms = exynos_drm_encoder_dpms, 176 .dpms = exynos_drm_encoder_dpms,
183 .mode_fixup = exynos_drm_encoder_mode_fixup, 177 .mode_fixup = exynos_drm_encoder_mode_fixup,
184 .mode_set = exynos_drm_encoder_mode_set, 178 .mode_set = exynos_drm_encoder_mode_set,
185 .prepare = exynos_drm_encoder_prepare, 179 .prepare = exynos_drm_encoder_prepare,
186 .commit = exynos_drm_encoder_commit, 180 .commit = exynos_drm_encoder_commit,
187 .get_crtc = exynos_drm_encoder_get_crtc,
188}; 181};
189 182
190static void exynos_drm_encoder_destroy(struct drm_encoder *encoder) 183static void exynos_drm_encoder_destroy(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c
index f82a299553fb..4ccfe4328fab 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c
@@ -51,11 +51,22 @@ struct exynos_drm_fb {
51static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) 51static void exynos_drm_fb_destroy(struct drm_framebuffer *fb)
52{ 52{
53 struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); 53 struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb);
54 unsigned int i;
54 55
55 DRM_DEBUG_KMS("%s\n", __FILE__); 56 DRM_DEBUG_KMS("%s\n", __FILE__);
56 57
57 drm_framebuffer_cleanup(fb); 58 drm_framebuffer_cleanup(fb);
58 59
60 for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem_obj); i++) {
61 struct drm_gem_object *obj;
62
63 if (exynos_fb->exynos_gem_obj[i] == NULL)
64 continue;
65
66 obj = &exynos_fb->exynos_gem_obj[i]->base;
67 drm_gem_object_unreference_unlocked(obj);
68 }
69
59 kfree(exynos_fb); 70 kfree(exynos_fb);
60 exynos_fb = NULL; 71 exynos_fb = NULL;
61} 72}
@@ -134,11 +145,11 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
134 return ERR_PTR(-ENOENT); 145 return ERR_PTR(-ENOENT);
135 } 146 }
136 147
137 drm_gem_object_unreference_unlocked(obj);
138
139 fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj); 148 fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj);
140 if (IS_ERR(fb)) 149 if (IS_ERR(fb)) {
150 drm_gem_object_unreference_unlocked(obj);
141 return fb; 151 return fb;
152 }
142 153
143 exynos_fb = to_exynos_fb(fb); 154 exynos_fb = to_exynos_fb(fb);
144 nr = exynos_drm_format_num_buffers(fb->pixel_format); 155 nr = exynos_drm_format_num_buffers(fb->pixel_format);
@@ -152,8 +163,6 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv,
152 return ERR_PTR(-ENOENT); 163 return ERR_PTR(-ENOENT);
153 } 164 }
154 165
155 drm_gem_object_unreference_unlocked(obj);
156
157 exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj); 166 exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj);
158 } 167 }
159 168
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h
index 3ecb30d93552..50823756cdea 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fb.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h
@@ -31,10 +31,10 @@
31static inline int exynos_drm_format_num_buffers(uint32_t format) 31static inline int exynos_drm_format_num_buffers(uint32_t format)
32{ 32{
33 switch (format) { 33 switch (format) {
34 case DRM_FORMAT_NV12M: 34 case DRM_FORMAT_NV12:
35 case DRM_FORMAT_NV12MT: 35 case DRM_FORMAT_NV12MT:
36 return 2; 36 return 2;
37 case DRM_FORMAT_YUV420M: 37 case DRM_FORMAT_YUV420:
38 return 3; 38 return 3;
39 default: 39 default:
40 return 1; 40 return 1;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c
index fc91293c4560..5c8b683029ea 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gem.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c
@@ -689,7 +689,6 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
689 struct drm_device *dev, uint32_t handle, 689 struct drm_device *dev, uint32_t handle,
690 uint64_t *offset) 690 uint64_t *offset)
691{ 691{
692 struct exynos_drm_gem_obj *exynos_gem_obj;
693 struct drm_gem_object *obj; 692 struct drm_gem_object *obj;
694 int ret = 0; 693 int ret = 0;
695 694
@@ -710,15 +709,13 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv,
710 goto unlock; 709 goto unlock;
711 } 710 }
712 711
713 exynos_gem_obj = to_exynos_gem_obj(obj); 712 if (!obj->map_list.map) {
714 713 ret = drm_gem_create_mmap_offset(obj);
715 if (!exynos_gem_obj->base.map_list.map) {
716 ret = drm_gem_create_mmap_offset(&exynos_gem_obj->base);
717 if (ret) 714 if (ret)
718 goto out; 715 goto out;
719 } 716 }
720 717
721 *offset = (u64)exynos_gem_obj->base.map_list.hash.key << PAGE_SHIFT; 718 *offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
722 DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset); 719 DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset);
723 720
724out: 721out:
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 68ef01028375..e2147a2ddcec 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -365,7 +365,7 @@ static void vp_video_buffer(struct mixer_context *ctx, int win)
365 switch (win_data->pixel_format) { 365 switch (win_data->pixel_format) {
366 case DRM_FORMAT_NV12MT: 366 case DRM_FORMAT_NV12MT:
367 tiled_mode = true; 367 tiled_mode = true;
368 case DRM_FORMAT_NV12M: 368 case DRM_FORMAT_NV12:
369 crcb_mode = false; 369 crcb_mode = false;
370 buf_num = 2; 370 buf_num = 2;
371 break; 371 break;
@@ -601,18 +601,20 @@ static void mixer_win_reset(struct mixer_context *ctx)
601 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080); 601 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
602 602
603 /* setting graphical layers */ 603 /* setting graphical layers */
604
605 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */ 604 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
606 val |= MXR_GRP_CFG_WIN_BLEND_EN; 605 val |= MXR_GRP_CFG_WIN_BLEND_EN;
606 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
607 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
607 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */ 608 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
608 609
609 /* the same configuration for both layers */ 610 /* the same configuration for both layers */
610 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val); 611 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
611
612 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
613 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
614 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val); 612 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
615 613
614 /* setting video layers */
615 val = MXR_GRP_CFG_ALPHA_VAL(0);
616 mixer_reg_write(res, MXR_VIDEO_CFG, val);
617
616 /* configuration of Video Processor Registers */ 618 /* configuration of Video Processor Registers */
617 vp_win_reset(ctx); 619 vp_win_reset(ctx);
618 vp_default_filter(res); 620 vp_default_filter(res);
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
index 9764045428ce..b7e7b49d8f62 100644
--- a/drivers/gpu/drm/gma500/cdv_device.c
+++ b/drivers/gpu/drm/gma500/cdv_device.c
@@ -78,21 +78,6 @@ static int cdv_backlight_combination_mode(struct drm_device *dev)
78 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; 78 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
79} 79}
80 80
81static int cdv_get_brightness(struct backlight_device *bd)
82{
83 struct drm_device *dev = bl_get_data(bd);
84 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
85
86 if (cdv_backlight_combination_mode(dev)) {
87 u8 lbpc;
88
89 val &= ~1;
90 pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
91 val *= lbpc;
92 }
93 return val;
94}
95
96static u32 cdv_get_max_backlight(struct drm_device *dev) 81static u32 cdv_get_max_backlight(struct drm_device *dev)
97{ 82{
98 u32 max = REG_READ(BLC_PWM_CTL); 83 u32 max = REG_READ(BLC_PWM_CTL);
@@ -110,6 +95,22 @@ static u32 cdv_get_max_backlight(struct drm_device *dev)
110 return max; 95 return max;
111} 96}
112 97
98static int cdv_get_brightness(struct backlight_device *bd)
99{
100 struct drm_device *dev = bl_get_data(bd);
101 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
102
103 if (cdv_backlight_combination_mode(dev)) {
104 u8 lbpc;
105
106 val &= ~1;
107 pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
108 val *= lbpc;
109 }
110 return (val * 100)/cdv_get_max_backlight(dev);
111
112}
113
113static int cdv_set_brightness(struct backlight_device *bd) 114static int cdv_set_brightness(struct backlight_device *bd)
114{ 115{
115 struct drm_device *dev = bl_get_data(bd); 116 struct drm_device *dev = bl_get_data(bd);
@@ -120,6 +121,9 @@ static int cdv_set_brightness(struct backlight_device *bd)
120 if (level < 1) 121 if (level < 1)
121 level = 1; 122 level = 1;
122 123
124 level *= cdv_get_max_backlight(dev);
125 level /= 100;
126
123 if (cdv_backlight_combination_mode(dev)) { 127 if (cdv_backlight_combination_mode(dev)) {
124 u32 max = cdv_get_max_backlight(dev); 128 u32 max = cdv_get_max_backlight(dev);
125 u8 lbpc; 129 u8 lbpc;
@@ -157,7 +161,6 @@ static int cdv_backlight_init(struct drm_device *dev)
157 161
158 cdv_backlight_device->props.brightness = 162 cdv_backlight_device->props.brightness =
159 cdv_get_brightness(cdv_backlight_device); 163 cdv_get_brightness(cdv_backlight_device);
160 cdv_backlight_device->props.max_brightness = cdv_get_max_backlight(dev);
161 backlight_update_status(cdv_backlight_device); 164 backlight_update_status(cdv_backlight_device);
162 dev_priv->backlight_device = cdv_backlight_device; 165 dev_priv->backlight_device = cdv_backlight_device;
163 return 0; 166 return 0;
diff --git a/drivers/gpu/drm/gma500/opregion.c b/drivers/gpu/drm/gma500/opregion.c
index 4f186eca3a30..c430bd424681 100644
--- a/drivers/gpu/drm/gma500/opregion.c
+++ b/drivers/gpu/drm/gma500/opregion.c
@@ -144,6 +144,8 @@ struct opregion_asle {
144 144
145#define ASLE_CBLV_VALID (1<<31) 145#define ASLE_CBLV_VALID (1<<31)
146 146
147static struct psb_intel_opregion *system_opregion;
148
147static u32 asle_set_backlight(struct drm_device *dev, u32 bclp) 149static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
148{ 150{
149 struct drm_psb_private *dev_priv = dev->dev_private; 151 struct drm_psb_private *dev_priv = dev->dev_private;
@@ -205,7 +207,7 @@ void psb_intel_opregion_enable_asle(struct drm_device *dev)
205 struct drm_psb_private *dev_priv = dev->dev_private; 207 struct drm_psb_private *dev_priv = dev->dev_private;
206 struct opregion_asle *asle = dev_priv->opregion.asle; 208 struct opregion_asle *asle = dev_priv->opregion.asle;
207 209
208 if (asle) { 210 if (asle && system_opregion ) {
209 /* Don't do this on Medfield or other non PC like devices, they 211 /* Don't do this on Medfield or other non PC like devices, they
210 use the bit for something different altogether */ 212 use the bit for something different altogether */
211 psb_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE); 213 psb_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
@@ -221,7 +223,6 @@ void psb_intel_opregion_enable_asle(struct drm_device *dev)
221#define ACPI_EV_LID (1<<1) 223#define ACPI_EV_LID (1<<1)
222#define ACPI_EV_DOCK (1<<2) 224#define ACPI_EV_DOCK (1<<2)
223 225
224static struct psb_intel_opregion *system_opregion;
225 226
226static int psb_intel_opregion_video_event(struct notifier_block *nb, 227static int psb_intel_opregion_video_event(struct notifier_block *nb,
227 unsigned long val, void *data) 228 unsigned long val, void *data)
@@ -266,9 +267,6 @@ void psb_intel_opregion_init(struct drm_device *dev)
266 system_opregion = opregion; 267 system_opregion = opregion;
267 register_acpi_notifier(&psb_intel_opregion_notifier); 268 register_acpi_notifier(&psb_intel_opregion_notifier);
268 } 269 }
269
270 if (opregion->asle)
271 psb_intel_opregion_enable_asle(dev);
272} 270}
273 271
274void psb_intel_opregion_fini(struct drm_device *dev) 272void psb_intel_opregion_fini(struct drm_device *dev)
diff --git a/drivers/gpu/drm/gma500/opregion.h b/drivers/gpu/drm/gma500/opregion.h
index 72dc6b921265..4a90f8b0e16c 100644
--- a/drivers/gpu/drm/gma500/opregion.h
+++ b/drivers/gpu/drm/gma500/opregion.h
@@ -27,6 +27,7 @@ extern void psb_intel_opregion_asle_intr(struct drm_device *dev);
27extern void psb_intel_opregion_init(struct drm_device *dev); 27extern void psb_intel_opregion_init(struct drm_device *dev);
28extern void psb_intel_opregion_fini(struct drm_device *dev); 28extern void psb_intel_opregion_fini(struct drm_device *dev);
29extern int psb_intel_opregion_setup(struct drm_device *dev); 29extern int psb_intel_opregion_setup(struct drm_device *dev);
30extern void psb_intel_opregion_enable_asle(struct drm_device *dev);
30 31
31#else 32#else
32 33
@@ -46,4 +47,8 @@ extern inline int psb_intel_opregion_setup(struct drm_device *dev)
46{ 47{
47 return 0; 48 return 0;
48} 49}
50
51extern inline void psb_intel_opregion_enable_asle(struct drm_device *dev)
52{
53}
49#endif 54#endif
diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c
index eff039bf92d4..5971bc82b765 100644
--- a/drivers/gpu/drm/gma500/psb_device.c
+++ b/drivers/gpu/drm/gma500/psb_device.c
@@ -144,6 +144,10 @@ static int psb_backlight_init(struct drm_device *dev)
144 psb_backlight_device->props.max_brightness = 100; 144 psb_backlight_device->props.max_brightness = 100;
145 backlight_update_status(psb_backlight_device); 145 backlight_update_status(psb_backlight_device);
146 dev_priv->backlight_device = psb_backlight_device; 146 dev_priv->backlight_device = psb_backlight_device;
147
148 /* This must occur after the backlight is properly initialised */
149 psb_lid_timer_init(dev_priv);
150
147 return 0; 151 return 0;
148} 152}
149 153
@@ -354,13 +358,6 @@ static int psb_chip_setup(struct drm_device *dev)
354 return 0; 358 return 0;
355} 359}
356 360
357/* Not exactly an erratum more an irritation */
358static void psb_chip_errata(struct drm_device *dev)
359{
360 struct drm_psb_private *dev_priv = dev->dev_private;
361 psb_lid_timer_init(dev_priv);
362}
363
364static void psb_chip_teardown(struct drm_device *dev) 361static void psb_chip_teardown(struct drm_device *dev)
365{ 362{
366 struct drm_psb_private *dev_priv = dev->dev_private; 363 struct drm_psb_private *dev_priv = dev->dev_private;
@@ -379,7 +376,6 @@ const struct psb_ops psb_chip_ops = {
379 .sgx_offset = PSB_SGX_OFFSET, 376 .sgx_offset = PSB_SGX_OFFSET,
380 .chip_setup = psb_chip_setup, 377 .chip_setup = psb_chip_setup,
381 .chip_teardown = psb_chip_teardown, 378 .chip_teardown = psb_chip_teardown,
382 .errata = psb_chip_errata,
383 379
384 .crtc_helper = &psb_intel_helper_funcs, 380 .crtc_helper = &psb_intel_helper_funcs,
385 .crtc_funcs = &psb_intel_crtc_funcs, 381 .crtc_funcs = &psb_intel_crtc_funcs,
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index caba6e08693c..a8858a907f47 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -374,6 +374,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
374 374
375 if (ret) 375 if (ret)
376 return ret; 376 return ret;
377 psb_intel_opregion_enable_asle(dev);
377#if 0 378#if 0
378 /*enable runtime pm at last*/ 379 /*enable runtime pm at last*/
379 pm_runtime_enable(&dev->pdev->dev); 380 pm_runtime_enable(&dev->pdev->dev);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f94792626b94..36822b924eb1 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1401,6 +1401,27 @@ i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base,
1401 } 1401 }
1402} 1402}
1403 1403
1404static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1405{
1406 struct apertures_struct *ap;
1407 struct pci_dev *pdev = dev_priv->dev->pdev;
1408 bool primary;
1409
1410 ap = alloc_apertures(1);
1411 if (!ap)
1412 return;
1413
1414 ap->ranges[0].base = dev_priv->dev->agp->base;
1415 ap->ranges[0].size =
1416 dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1417 primary =
1418 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1419
1420 remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1421
1422 kfree(ap);
1423}
1424
1404/** 1425/**
1405 * i915_driver_load - setup chip and create an initial config 1426 * i915_driver_load - setup chip and create an initial config
1406 * @dev: DRM device 1427 * @dev: DRM device
@@ -1446,6 +1467,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1446 goto free_priv; 1467 goto free_priv;
1447 } 1468 }
1448 1469
1470 dev_priv->mm.gtt = intel_gtt_get();
1471 if (!dev_priv->mm.gtt) {
1472 DRM_ERROR("Failed to initialize GTT\n");
1473 ret = -ENODEV;
1474 goto put_bridge;
1475 }
1476
1477 i915_kick_out_firmware_fb(dev_priv);
1478
1449 pci_set_master(dev->pdev); 1479 pci_set_master(dev->pdev);
1450 1480
1451 /* overlay on gen2 is broken and can't address above 1G */ 1481 /* overlay on gen2 is broken and can't address above 1G */
@@ -1471,13 +1501,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1471 goto put_bridge; 1501 goto put_bridge;
1472 } 1502 }
1473 1503
1474 dev_priv->mm.gtt = intel_gtt_get();
1475 if (!dev_priv->mm.gtt) {
1476 DRM_ERROR("Failed to initialize GTT\n");
1477 ret = -ENODEV;
1478 goto out_rmmap;
1479 }
1480
1481 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; 1504 aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1482 1505
1483 dev_priv->mm.gtt_mapping = 1506 dev_priv->mm.gtt_mapping =
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 238a52165833..9fe9ebe52a7a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -233,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_d_info = {
233 .has_blt_ring = 1, 233 .has_blt_ring = 1,
234 .has_llc = 1, 234 .has_llc = 1,
235 .has_pch_split = 1, 235 .has_pch_split = 1,
236 .has_force_wake = 1,
236}; 237};
237 238
238static const struct intel_device_info intel_sandybridge_m_info = { 239static const struct intel_device_info intel_sandybridge_m_info = {
@@ -243,6 +244,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
243 .has_blt_ring = 1, 244 .has_blt_ring = 1,
244 .has_llc = 1, 245 .has_llc = 1,
245 .has_pch_split = 1, 246 .has_pch_split = 1,
247 .has_force_wake = 1,
246}; 248};
247 249
248static const struct intel_device_info intel_ivybridge_d_info = { 250static const struct intel_device_info intel_ivybridge_d_info = {
@@ -252,6 +254,7 @@ static const struct intel_device_info intel_ivybridge_d_info = {
252 .has_blt_ring = 1, 254 .has_blt_ring = 1,
253 .has_llc = 1, 255 .has_llc = 1,
254 .has_pch_split = 1, 256 .has_pch_split = 1,
257 .has_force_wake = 1,
255}; 258};
256 259
257static const struct intel_device_info intel_ivybridge_m_info = { 260static const struct intel_device_info intel_ivybridge_m_info = {
@@ -262,6 +265,7 @@ static const struct intel_device_info intel_ivybridge_m_info = {
262 .has_blt_ring = 1, 265 .has_blt_ring = 1,
263 .has_llc = 1, 266 .has_llc = 1,
264 .has_pch_split = 1, 267 .has_pch_split = 1,
268 .has_force_wake = 1,
265}; 269};
266 270
267static const struct intel_device_info intel_valleyview_m_info = { 271static const struct intel_device_info intel_valleyview_m_info = {
@@ -289,6 +293,7 @@ static const struct intel_device_info intel_haswell_d_info = {
289 .has_blt_ring = 1, 293 .has_blt_ring = 1,
290 .has_llc = 1, 294 .has_llc = 1,
291 .has_pch_split = 1, 295 .has_pch_split = 1,
296 .has_force_wake = 1,
292}; 297};
293 298
294static const struct intel_device_info intel_haswell_m_info = { 299static const struct intel_device_info intel_haswell_m_info = {
@@ -298,6 +303,7 @@ static const struct intel_device_info intel_haswell_m_info = {
298 .has_blt_ring = 1, 303 .has_blt_ring = 1,
299 .has_llc = 1, 304 .has_llc = 1,
300 .has_pch_split = 1, 305 .has_pch_split = 1,
306 .has_force_wake = 1,
301}; 307};
302 308
303static const struct pci_device_id pciidlist[] = { /* aka */ 309static const struct pci_device_id pciidlist[] = { /* aka */
@@ -1139,10 +1145,9 @@ MODULE_LICENSE("GPL and additional rights");
1139 1145
1140/* We give fast paths for the really cool registers */ 1146/* We give fast paths for the really cool registers */
1141#define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1147#define NEEDS_FORCE_WAKE(dev_priv, reg) \
1142 (((dev_priv)->info->gen >= 6) && \ 1148 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1143 ((reg) < 0x40000) && \ 1149 ((reg) < 0x40000) && \
1144 ((reg) != FORCEWAKE)) && \ 1150 ((reg) != FORCEWAKE))
1145 (!IS_VALLEYVIEW((dev_priv)->dev))
1146 1151
1147#define __i915_read(x, y) \ 1152#define __i915_read(x, y) \
1148u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ 1153u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c9cfc67c2cf5..b0b676abde0d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -285,6 +285,7 @@ struct intel_device_info {
285 u8 is_ivybridge:1; 285 u8 is_ivybridge:1;
286 u8 is_valleyview:1; 286 u8 is_valleyview:1;
287 u8 has_pch_split:1; 287 u8 has_pch_split:1;
288 u8 has_force_wake:1;
288 u8 is_haswell:1; 289 u8 is_haswell:1;
289 u8 has_fbc:1; 290 u8 has_fbc:1;
290 u8 has_pipe_cxsr:1; 291 u8 has_pipe_cxsr:1;
@@ -1101,6 +1102,8 @@ struct drm_i915_file_private {
1101#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1102#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1102#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1103#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1103 1104
1105#define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1106
1104#include "i915_trace.h" 1107#include "i915_trace.h"
1105 1108
1106/** 1109/**
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 1417660a93ec..ed3224c37423 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -412,7 +412,6 @@ static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
412 */ 412 */
413 413
414 spin_lock_irqsave(&dev_priv->rps_lock, flags); 414 spin_lock_irqsave(&dev_priv->rps_lock, flags);
415 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
416 dev_priv->pm_iir |= pm_iir; 415 dev_priv->pm_iir |= pm_iir;
417 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 416 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
418 POSTING_READ(GEN6_PMIMR); 417 POSTING_READ(GEN6_PMIMR);
@@ -510,7 +509,7 @@ out:
510 return ret; 509 return ret;
511} 510}
512 511
513static void pch_irq_handler(struct drm_device *dev, u32 pch_iir) 512static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
514{ 513{
515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 514 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
516 int pipe; 515 int pipe;
@@ -550,6 +549,35 @@ static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
550 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 549 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
551} 550}
552 551
552static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
553{
554 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
555 int pipe;
556
557 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
558 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
559 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
560 SDE_AUDIO_POWER_SHIFT_CPT);
561
562 if (pch_iir & SDE_AUX_MASK_CPT)
563 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
564
565 if (pch_iir & SDE_GMBUS_CPT)
566 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
567
568 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
569 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
570
571 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
572 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
573
574 if (pch_iir & SDE_FDI_MASK_CPT)
575 for_each_pipe(pipe)
576 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
577 pipe_name(pipe),
578 I915_READ(FDI_RX_IIR(pipe)));
579}
580
553static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) 581static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
554{ 582{
555 struct drm_device *dev = (struct drm_device *) arg; 583 struct drm_device *dev = (struct drm_device *) arg;
@@ -591,7 +619,7 @@ static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
591 619
592 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 620 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
593 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 621 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
594 pch_irq_handler(dev, pch_iir); 622 cpt_irq_handler(dev, pch_iir);
595 623
596 /* clear PCH hotplug event before clear CPU irq */ 624 /* clear PCH hotplug event before clear CPU irq */
597 I915_WRITE(SDEIIR, pch_iir); 625 I915_WRITE(SDEIIR, pch_iir);
@@ -684,7 +712,10 @@ static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
684 if (de_iir & DE_PCH_EVENT) { 712 if (de_iir & DE_PCH_EVENT) {
685 if (pch_iir & hotplug_mask) 713 if (pch_iir & hotplug_mask)
686 queue_work(dev_priv->wq, &dev_priv->hotplug_work); 714 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
687 pch_irq_handler(dev, pch_iir); 715 if (HAS_PCH_CPT(dev))
716 cpt_irq_handler(dev, pch_iir);
717 else
718 ibx_irq_handler(dev, pch_iir);
688 } 719 }
689 720
690 if (de_iir & DE_PCU_EVENT) { 721 if (de_iir & DE_PCU_EVENT) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2d49b9507ed0..48d5e8e051cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -210,6 +210,14 @@
210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 210#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 211#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 212#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
213/* IVB has funny definitions for which plane to flip. */
214#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
215#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
216#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
217#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
218#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
219#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
220
213#define MI_SET_CONTEXT MI_INSTR(0x18, 0) 221#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
214#define MI_MM_SPACE_GTT (1<<8) 222#define MI_MM_SPACE_GTT (1<<8)
215#define MI_MM_SPACE_PHYSICAL (0<<8) 223#define MI_MM_SPACE_PHYSICAL (0<<8)
@@ -3313,7 +3321,7 @@
3313 3321
3314/* PCH */ 3322/* PCH */
3315 3323
3316/* south display engine interrupt */ 3324/* south display engine interrupt: IBX */
3317#define SDE_AUDIO_POWER_D (1 << 27) 3325#define SDE_AUDIO_POWER_D (1 << 27)
3318#define SDE_AUDIO_POWER_C (1 << 26) 3326#define SDE_AUDIO_POWER_C (1 << 26)
3319#define SDE_AUDIO_POWER_B (1 << 25) 3327#define SDE_AUDIO_POWER_B (1 << 25)
@@ -3349,15 +3357,44 @@
3349#define SDE_TRANSA_CRC_ERR (1 << 1) 3357#define SDE_TRANSA_CRC_ERR (1 << 1)
3350#define SDE_TRANSA_FIFO_UNDER (1 << 0) 3358#define SDE_TRANSA_FIFO_UNDER (1 << 0)
3351#define SDE_TRANS_MASK (0x3f) 3359#define SDE_TRANS_MASK (0x3f)
3352/* CPT */ 3360
3353#define SDE_CRT_HOTPLUG_CPT (1 << 19) 3361/* south display engine interrupt: CPT/PPT */
3362#define SDE_AUDIO_POWER_D_CPT (1 << 31)
3363#define SDE_AUDIO_POWER_C_CPT (1 << 30)
3364#define SDE_AUDIO_POWER_B_CPT (1 << 29)
3365#define SDE_AUDIO_POWER_SHIFT_CPT 29
3366#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
3367#define SDE_AUXD_CPT (1 << 27)
3368#define SDE_AUXC_CPT (1 << 26)
3369#define SDE_AUXB_CPT (1 << 25)
3370#define SDE_AUX_MASK_CPT (7 << 25)
3354#define SDE_PORTD_HOTPLUG_CPT (1 << 23) 3371#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
3355#define SDE_PORTC_HOTPLUG_CPT (1 << 22) 3372#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
3356#define SDE_PORTB_HOTPLUG_CPT (1 << 21) 3373#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
3374#define SDE_CRT_HOTPLUG_CPT (1 << 19)
3357#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \ 3375#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
3358 SDE_PORTD_HOTPLUG_CPT | \ 3376 SDE_PORTD_HOTPLUG_CPT | \
3359 SDE_PORTC_HOTPLUG_CPT | \ 3377 SDE_PORTC_HOTPLUG_CPT | \
3360 SDE_PORTB_HOTPLUG_CPT) 3378 SDE_PORTB_HOTPLUG_CPT)
3379#define SDE_GMBUS_CPT (1 << 17)
3380#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
3381#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
3382#define SDE_FDI_RXC_CPT (1 << 8)
3383#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
3384#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
3385#define SDE_FDI_RXB_CPT (1 << 4)
3386#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
3387#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
3388#define SDE_FDI_RXA_CPT (1 << 0)
3389#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
3390 SDE_AUDIO_CP_REQ_B_CPT | \
3391 SDE_AUDIO_CP_REQ_A_CPT)
3392#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
3393 SDE_AUDIO_CP_CHG_B_CPT | \
3394 SDE_AUDIO_CP_CHG_A_CPT)
3395#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
3396 SDE_FDI_RXB_CPT | \
3397 SDE_FDI_RXA_CPT)
3361 3398
3362#define SDEISR 0xc4000 3399#define SDEISR 0xc4000
3363#define SDEIMR 0xc4004 3400#define SDEIMR 0xc4004
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 0ede02a99d91..a748e5cabe14 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -740,8 +740,11 @@ static void i915_restore_display(struct drm_device *dev)
740 if (HAS_PCH_SPLIT(dev)) { 740 if (HAS_PCH_SPLIT(dev)) {
741 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL); 741 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
742 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2); 742 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
743 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL); 743 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
744 * otherwise we get blank eDP screen after S3 on some machines
745 */
744 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2); 746 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
747 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
745 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 748 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
746 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 749 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
747 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR); 750 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 914789420906..a8538ac0299d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6158,17 +6158,34 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
6158 struct drm_i915_private *dev_priv = dev->dev_private; 6158 struct drm_i915_private *dev_priv = dev->dev_private;
6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 6160 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6161 uint32_t plane_bit = 0;
6161 int ret; 6162 int ret;
6162 6163
6163 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 6164 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6164 if (ret) 6165 if (ret)
6165 goto err; 6166 goto err;
6166 6167
6168 switch(intel_crtc->plane) {
6169 case PLANE_A:
6170 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6171 break;
6172 case PLANE_B:
6173 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6174 break;
6175 case PLANE_C:
6176 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6177 break;
6178 default:
6179 WARN_ONCE(1, "unknown plane in flip command\n");
6180 ret = -ENODEV;
6181 goto err;
6182 }
6183
6167 ret = intel_ring_begin(ring, 4); 6184 ret = intel_ring_begin(ring, 4);
6168 if (ret) 6185 if (ret)
6169 goto err_unpin; 6186 goto err_unpin;
6170 6187
6171 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); 6188 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6172 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 6189 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6173 intel_ring_emit(ring, (obj->gtt_offset)); 6190 intel_ring_emit(ring, (obj->gtt_offset));
6174 intel_ring_emit(ring, (MI_NOOP)); 6191 intel_ring_emit(ring, (MI_NOOP));
@@ -6541,7 +6558,7 @@ static void intel_setup_outputs(struct drm_device *dev)
6541 if (I915_READ(HDMIC) & PORT_DETECTED) 6558 if (I915_READ(HDMIC) & PORT_DETECTED)
6542 intel_hdmi_init(dev, HDMIC); 6559 intel_hdmi_init(dev, HDMIC);
6543 6560
6544 if (I915_READ(HDMID) & PORT_DETECTED) 6561 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6545 intel_hdmi_init(dev, HDMID); 6562 intel_hdmi_init(dev, HDMID);
6546 6563
6547 if (I915_READ(PCH_DP_C) & DP_DETECTED) 6564 if (I915_READ(PCH_DP_C) & DP_DETECTED)
@@ -6904,19 +6921,6 @@ static void i915_disable_vga(struct drm_device *dev)
6904 POSTING_READ(vga_reg); 6921 POSTING_READ(vga_reg);
6905} 6922}
6906 6923
6907static void ivb_pch_pwm_override(struct drm_device *dev)
6908{
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910
6911 /*
6912 * IVB has CPU eDP backlight regs too, set things up to let the
6913 * PCH regs control the backlight
6914 */
6915 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6916 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6917 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6918}
6919
6920void intel_modeset_init_hw(struct drm_device *dev) 6924void intel_modeset_init_hw(struct drm_device *dev)
6921{ 6925{
6922 struct drm_i915_private *dev_priv = dev->dev_private; 6926 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -6933,9 +6937,6 @@ void intel_modeset_init_hw(struct drm_device *dev)
6933 gen6_enable_rps(dev_priv); 6937 gen6_enable_rps(dev_priv);
6934 gen6_update_ring_freq(dev_priv); 6938 gen6_update_ring_freq(dev_priv);
6935 } 6939 }
6936
6937 if (IS_IVYBRIDGE(dev))
6938 ivb_pch_pwm_override(dev);
6939} 6940}
6940 6941
6941void intel_modeset_init(struct drm_device *dev) 6942void intel_modeset_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 296cfc201a81..c0449324143c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -32,6 +32,7 @@
32#include "drm.h" 32#include "drm.h"
33#include "drm_crtc.h" 33#include "drm_crtc.h"
34#include "drm_crtc_helper.h" 34#include "drm_crtc_helper.h"
35#include "drm_edid.h"
35#include "intel_drv.h" 36#include "intel_drv.h"
36#include "i915_drm.h" 37#include "i915_drm.h"
37#include "i915_drv.h" 38#include "i915_drv.h"
@@ -67,6 +68,8 @@ struct intel_dp {
67 struct drm_display_mode *panel_fixed_mode; /* for eDP */ 68 struct drm_display_mode *panel_fixed_mode; /* for eDP */
68 struct delayed_work panel_vdd_work; 69 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd; 70 bool want_panel_vdd;
71 struct edid *edid; /* cached EDID for eDP */
72 int edid_mode_count;
70}; 73};
71 74
72/** 75/**
@@ -371,7 +374,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
371 int recv_bytes; 374 int recv_bytes;
372 uint32_t status; 375 uint32_t status;
373 uint32_t aux_clock_divider; 376 uint32_t aux_clock_divider;
374 int try, precharge = 5; 377 int try, precharge;
375 378
376 intel_dp_check_edp(intel_dp); 379 intel_dp_check_edp(intel_dp);
377 /* The clock divider is based off the hrawclk, 380 /* The clock divider is based off the hrawclk,
@@ -391,6 +394,11 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
391 else 394 else
392 aux_clock_divider = intel_hrawclk(dev) / 2; 395 aux_clock_divider = intel_hrawclk(dev) / 2;
393 396
397 if (IS_GEN6(dev))
398 precharge = 3;
399 else
400 precharge = 5;
401
394 /* Try to wait for any previous AUX channel activity */ 402 /* Try to wait for any previous AUX channel activity */
395 for (try = 0; try < 3; try++) { 403 for (try = 0; try < 3; try++) {
396 status = I915_READ(ch_ctl); 404 status = I915_READ(ch_ctl);
@@ -1973,6 +1981,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
1973 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 1981 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1974 return; 1982 return;
1975 1983
1984 ironlake_edp_panel_vdd_on(intel_dp);
1985
1976 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 1986 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1977 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 1987 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1978 buf[0], buf[1], buf[2]); 1988 buf[0], buf[1], buf[2]);
@@ -1980,6 +1990,8 @@ intel_dp_probe_oui(struct intel_dp *intel_dp)
1980 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 1990 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1981 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 1991 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1982 buf[0], buf[1], buf[2]); 1992 buf[0], buf[1], buf[2]);
1993
1994 ironlake_edp_panel_vdd_off(intel_dp, false);
1983} 1995}
1984 1996
1985static bool 1997static bool
@@ -2116,10 +2128,22 @@ intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2116{ 2128{
2117 struct intel_dp *intel_dp = intel_attached_dp(connector); 2129 struct intel_dp *intel_dp = intel_attached_dp(connector);
2118 struct edid *edid; 2130 struct edid *edid;
2131 int size;
2132
2133 if (is_edp(intel_dp)) {
2134 if (!intel_dp->edid)
2135 return NULL;
2136
2137 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2138 edid = kmalloc(size, GFP_KERNEL);
2139 if (!edid)
2140 return NULL;
2141
2142 memcpy(edid, intel_dp->edid, size);
2143 return edid;
2144 }
2119 2145
2120 ironlake_edp_panel_vdd_on(intel_dp);
2121 edid = drm_get_edid(connector, adapter); 2146 edid = drm_get_edid(connector, adapter);
2122 ironlake_edp_panel_vdd_off(intel_dp, false);
2123 return edid; 2147 return edid;
2124} 2148}
2125 2149
@@ -2129,9 +2153,17 @@ intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *ada
2129 struct intel_dp *intel_dp = intel_attached_dp(connector); 2153 struct intel_dp *intel_dp = intel_attached_dp(connector);
2130 int ret; 2154 int ret;
2131 2155
2132 ironlake_edp_panel_vdd_on(intel_dp); 2156 if (is_edp(intel_dp)) {
2157 drm_mode_connector_update_edid_property(connector,
2158 intel_dp->edid);
2159 ret = drm_add_edid_modes(connector, intel_dp->edid);
2160 drm_edid_to_eld(connector,
2161 intel_dp->edid);
2162 connector->display_info.raw_edid = NULL;
2163 return intel_dp->edid_mode_count;
2164 }
2165
2133 ret = intel_ddc_get_modes(connector, adapter); 2166 ret = intel_ddc_get_modes(connector, adapter);
2134 ironlake_edp_panel_vdd_off(intel_dp, false);
2135 return ret; 2167 return ret;
2136} 2168}
2137 2169
@@ -2321,6 +2353,7 @@ static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2321 i2c_del_adapter(&intel_dp->adapter); 2353 i2c_del_adapter(&intel_dp->adapter);
2322 drm_encoder_cleanup(encoder); 2354 drm_encoder_cleanup(encoder);
2323 if (is_edp(intel_dp)) { 2355 if (is_edp(intel_dp)) {
2356 kfree(intel_dp->edid);
2324 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 2357 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2325 ironlake_panel_vdd_off_sync(intel_dp); 2358 ironlake_panel_vdd_off_sync(intel_dp);
2326 } 2359 }
@@ -2504,11 +2537,14 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2504 break; 2537 break;
2505 } 2538 }
2506 2539
2540 intel_dp_i2c_init(intel_dp, intel_connector, name);
2541
2507 /* Cache some DPCD data in the eDP case */ 2542 /* Cache some DPCD data in the eDP case */
2508 if (is_edp(intel_dp)) { 2543 if (is_edp(intel_dp)) {
2509 bool ret; 2544 bool ret;
2510 struct edp_power_seq cur, vbt; 2545 struct edp_power_seq cur, vbt;
2511 u32 pp_on, pp_off, pp_div; 2546 u32 pp_on, pp_off, pp_div;
2547 struct edid *edid;
2512 2548
2513 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2549 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2514 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2550 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
@@ -2576,9 +2612,19 @@ intel_dp_init(struct drm_device *dev, int output_reg)
2576 intel_dp_destroy(&intel_connector->base); 2612 intel_dp_destroy(&intel_connector->base);
2577 return; 2613 return;
2578 } 2614 }
2579 }
2580 2615
2581 intel_dp_i2c_init(intel_dp, intel_connector, name); 2616 ironlake_edp_panel_vdd_on(intel_dp);
2617 edid = drm_get_edid(connector, &intel_dp->adapter);
2618 if (edid) {
2619 drm_mode_connector_update_edid_property(connector,
2620 edid);
2621 intel_dp->edid_mode_count =
2622 drm_add_edid_modes(connector, edid);
2623 drm_edid_to_eld(connector, edid);
2624 intel_dp->edid = edid;
2625 }
2626 ironlake_edp_panel_vdd_off(intel_dp, false);
2627 }
2582 2628
2583 intel_encoder->hot_plug = intel_dp_hot_plug; 2629 intel_encoder->hot_plug = intel_dp_hot_plug;
2584 2630
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b59b6d5b7583..e5b84ff89ca5 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -266,10 +266,15 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
266 266
267static int init_ring_common(struct intel_ring_buffer *ring) 267static int init_ring_common(struct intel_ring_buffer *ring)
268{ 268{
269 drm_i915_private_t *dev_priv = ring->dev->dev_private; 269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
270 struct drm_i915_gem_object *obj = ring->obj; 271 struct drm_i915_gem_object *obj = ring->obj;
272 int ret = 0;
271 u32 head; 273 u32 head;
272 274
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
277
273 /* Stop the ring if it's running. */ 278 /* Stop the ring if it's running. */
274 I915_WRITE_CTL(ring, 0); 279 I915_WRITE_CTL(ring, 0);
275 I915_WRITE_HEAD(ring, 0); 280 I915_WRITE_HEAD(ring, 0);
@@ -317,7 +322,8 @@ static int init_ring_common(struct intel_ring_buffer *ring)
317 I915_READ_HEAD(ring), 322 I915_READ_HEAD(ring),
318 I915_READ_TAIL(ring), 323 I915_READ_TAIL(ring),
319 I915_READ_START(ring)); 324 I915_READ_START(ring));
320 return -EIO; 325 ret = -EIO;
326 goto out;
321 } 327 }
322 328
323 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) 329 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
@@ -326,9 +332,14 @@ static int init_ring_common(struct intel_ring_buffer *ring)
326 ring->head = I915_READ_HEAD(ring); 332 ring->head = I915_READ_HEAD(ring);
327 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; 333 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
328 ring->space = ring_space(ring); 334 ring->space = ring_space(ring);
335 ring->last_retired_head = -1;
329 } 336 }
330 337
331 return 0; 338out:
339 if (HAS_FORCE_WAKE(dev))
340 gen6_gt_force_wake_put(dev_priv);
341
342 return ret;
332} 343}
333 344
334static int 345static int
@@ -987,6 +998,10 @@ static int intel_init_ring_buffer(struct drm_device *dev,
987 if (ret) 998 if (ret)
988 goto err_unref; 999 goto err_unref;
989 1000
1001 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1002 if (ret)
1003 goto err_unpin;
1004
990 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset, 1005 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
991 ring->size); 1006 ring->size);
992 if (ring->virtual_start == NULL) { 1007 if (ring->virtual_start == NULL) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index 153b9a15469b..1074bc5dd418 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -467,7 +467,7 @@ int nouveau_fbcon_init(struct drm_device *dev)
467 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs; 467 nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
468 468
469 ret = drm_fb_helper_init(dev, &nfbdev->helper, 469 ret = drm_fb_helper_init(dev, &nfbdev->helper,
470 nv_two_heads(dev) ? 2 : 1, 4); 470 dev->mode_config.num_crtc, 4);
471 if (ret) { 471 if (ret) {
472 kfree(nfbdev); 472 kfree(nfbdev);
473 return ret; 473 return ret;
diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c
index a89240e5fb29..a25cf2cb931f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_prime.c
+++ b/drivers/gpu/drm/nouveau/nouveau_prime.c
@@ -1,3 +1,26 @@
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Dave Airlie
23 */
1 24
2#include "drmP.h" 25#include "drmP.h"
3#include "drm.h" 26#include "drm.h"
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f4..3904d7964a4b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1149 } 1149 }
1150 1150
1151 if (tiling_flags & RADEON_TILING_MACRO) { 1151 if (tiling_flags & RADEON_TILING_MACRO) {
1152 if (rdev->family >= CHIP_CAYMAN) 1152 if (rdev->family >= CHIP_TAHITI)
1153 tmp = rdev->config.si.tile_config;
1154 else if (rdev->family >= CHIP_CAYMAN)
1153 tmp = rdev->config.cayman.tile_config; 1155 tmp = rdev->config.cayman.tile_config;
1154 else 1156 else
1155 tmp = rdev->config.evergreen.tile_config; 1157 tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1177 } else if (tiling_flags & RADEON_TILING_MICRO) 1179 } else if (tiling_flags & RADEON_TILING_MICRO)
1178 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1180 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1179 1181
1182 if ((rdev->family == CHIP_TAHITI) ||
1183 (rdev->family == CHIP_PITCAIRN))
1184 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1185 else if (rdev->family == CHIP_VERDE)
1186 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1187
1180 switch (radeon_crtc->crtc_id) { 1188 switch (radeon_crtc->crtc_id) {
1181 case 0: 1189 case 0:
1182 WREG32(AVIVO_D1VGA_CONTROL, 0); 1190 WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index e7b1ec5ae8c6..486ccdf4aacd 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1926,7 +1926,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1926 1926
1927 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 1927 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1928 r600_hdmi_enable(encoder); 1928 r600_hdmi_enable(encoder);
1929 if (ASIC_IS_DCE4(rdev)) 1929 if (ASIC_IS_DCE6(rdev))
1930 ; /* TODO (use pointers instead of if-s?) */
1931 else if (ASIC_IS_DCE4(rdev))
1930 evergreen_hdmi_setmode(encoder, adjusted_mode); 1932 evergreen_hdmi_setmode(encoder, adjusted_mode);
1931 else 1933 else
1932 r600_hdmi_setmode(encoder, adjusted_mode); 1934 r600_hdmi_setmode(encoder, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 01550d05e273..7fb3d2e0434c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1932 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); 1932 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1933 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 1933 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1934 1934
1935 if (rdev->family <= CHIP_SUMO2)
1936 WREG32(SMX_SAR_CTL0, 0x00010000);
1937
1935 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | 1938 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1936 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | 1939 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1937 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); 1940 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b4843d..c16554122ccd 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
52 u32 cb_color_view[12]; 52 u32 cb_color_view[12];
53 u32 cb_color_pitch[12]; 53 u32 cb_color_pitch[12];
54 u32 cb_color_slice[12]; 54 u32 cb_color_slice[12];
55 u32 cb_color_slice_idx[12];
55 u32 cb_color_attrib[12]; 56 u32 cb_color_attrib[12];
56 u32 cb_color_cmask_slice[8];/* unused */ 57 u32 cb_color_cmask_slice[8];/* unused */
57 u32 cb_color_fmask_slice[8];/* unused */ 58 u32 cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
127 track->cb_color_info[i] = 0; 128 track->cb_color_info[i] = 0;
128 track->cb_color_view[i] = 0xFFFFFFFF; 129 track->cb_color_view[i] = 0xFFFFFFFF;
129 track->cb_color_pitch[i] = 0; 130 track->cb_color_pitch[i] = 0;
130 track->cb_color_slice[i] = 0; 131 track->cb_color_slice[i] = 0xfffffff;
132 track->cb_color_slice_idx[i] = 0;
131 } 133 }
132 track->cb_target_mask = 0xFFFFFFFF; 134 track->cb_target_mask = 0xFFFFFFFF;
133 track->cb_shader_mask = 0xFFFFFFFF; 135 track->cb_shader_mask = 0xFFFFFFFF;
134 track->cb_dirty = true; 136 track->cb_dirty = true;
135 137
138 track->db_depth_slice = 0xffffffff;
136 track->db_depth_view = 0xFFFFC000; 139 track->db_depth_view = 0xFFFFC000;
137 track->db_depth_size = 0xFFFFFFFF; 140 track->db_depth_size = 0xFFFFFFFF;
138 track->db_depth_control = 0xFFFFFFFF; 141 track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
250{ 253{
251 struct evergreen_cs_track *track = p->track; 254 struct evergreen_cs_track *track = p->track;
252 unsigned palign, halign, tileb, slice_pt; 255 unsigned palign, halign, tileb, slice_pt;
256 unsigned mtile_pr, mtile_ps, mtileb;
253 257
254 tileb = 64 * surf->bpe * surf->nsamples; 258 tileb = 64 * surf->bpe * surf->nsamples;
255 palign = track->group_size / (8 * surf->bpe * surf->nsamples);
256 palign = MAX(8, palign);
257 slice_pt = 1; 259 slice_pt = 1;
258 if (tileb > surf->tsplit) { 260 if (tileb > surf->tsplit) {
259 slice_pt = tileb / surf->tsplit; 261 slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
262 /* macro tile width & height */ 264 /* macro tile width & height */
263 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; 265 palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
264 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; 266 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
265 surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt; 267 mtileb = (palign / 8) * (halign / 8) * tileb;;
268 mtile_pr = surf->nbx / palign;
269 mtile_ps = (mtile_pr * surf->nby) / halign;
270 surf->layer_size = mtile_ps * mtileb * slice_pt;
266 surf->base_align = (palign / 8) * (halign / 8) * tileb; 271 surf->base_align = (palign / 8) * (halign / 8) * tileb;
267 surf->palign = palign; 272 surf->palign = palign;
268 surf->halign = halign; 273 surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
434 439
435 offset += surf.layer_size * mslice; 440 offset += surf.layer_size * mslice;
436 if (offset > radeon_bo_size(track->cb_color_bo[id])) { 441 if (offset > radeon_bo_size(track->cb_color_bo[id])) {
442 /* old ddx are broken they allocate bo with w*h*bpp but
443 * program slice with ALIGN(h, 8), catch this and patch
444 * command stream.
445 */
446 if (!surf.mode) {
447 volatile u32 *ib = p->ib.ptr;
448 unsigned long tmp, nby, bsize, size, min = 0;
449
450 /* find the height the ddx wants */
451 if (surf.nby > 8) {
452 min = surf.nby - 8;
453 }
454 bsize = radeon_bo_size(track->cb_color_bo[id]);
455 tmp = track->cb_color_bo_offset[id] << 8;
456 for (nby = surf.nby; nby > min; nby--) {
457 size = nby * surf.nbx * surf.bpe * surf.nsamples;
458 if ((tmp + size * mslice) <= bsize) {
459 break;
460 }
461 }
462 if (nby > min) {
463 surf.nby = nby;
464 slice = ((nby * surf.nbx) / 64) - 1;
465 if (!evergreen_surface_check(p, &surf, "cb")) {
466 /* check if this one works */
467 tmp += surf.layer_size * mslice;
468 if (tmp <= bsize) {
469 ib[track->cb_color_slice_idx[id]] = slice;
470 goto old_ddx_ok;
471 }
472 }
473 }
474 }
437 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " 475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
438 "offset %d, max layer %d, bo size %ld, slice %d)\n", 476 "offset %d, max layer %d, bo size %ld, slice %d)\n",
439 __func__, __LINE__, id, surf.layer_size, 477 __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
446 surf.tsplit, surf.mtilea); 484 surf.tsplit, surf.mtilea);
447 return -EINVAL; 485 return -EINVAL;
448 } 486 }
487old_ddx_ok:
449 488
450 return 0; 489 return 0;
451} 490}
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1532 case CB_COLOR7_SLICE: 1571 case CB_COLOR7_SLICE:
1533 tmp = (reg - CB_COLOR0_SLICE) / 0x3c; 1572 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1534 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1573 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1574 track->cb_color_slice_idx[tmp] = idx;
1535 track->cb_dirty = true; 1575 track->cb_dirty = true;
1536 break; 1576 break;
1537 case CB_COLOR8_SLICE: 1577 case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1540 case CB_COLOR11_SLICE: 1580 case CB_COLOR11_SLICE:
1541 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; 1581 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1542 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); 1582 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1583 track->cb_color_slice_idx[tmp] = idx;
1543 track->cb_dirty = true; 1584 track->cb_dirty = true;
1544 break; 1585 break;
1545 case CB_COLOR0_ATTRIB: 1586 case CB_COLOR0_ATTRIB:
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index a51f880985f8..65c54160028b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -156,9 +156,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
156 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 156 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
157 uint32_t offset; 157 uint32_t offset;
158 158
159 if (ASIC_IS_DCE5(rdev))
160 return;
161
162 /* Silent, r600_hdmi_enable will raise WARN for us */ 159 /* Silent, r600_hdmi_enable will raise WARN for us */
163 if (!dig->afmt->enabled) 160 if (!dig->afmt->enabled)
164 return; 161 return;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 2773039b4902..b50b15c70498 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -503,6 +503,7 @@
503#define SCRATCH_UMSK 0x8540 503#define SCRATCH_UMSK 0x8540
504#define SCRATCH_ADDR 0x8544 504#define SCRATCH_ADDR 0x8544
505 505
506#define SMX_SAR_CTL0 0xA008
506#define SMX_DC_CTL0 0xA020 507#define SMX_DC_CTL0 0xA020
507#define USE_HASH_FUNCTION (1 << 0) 508#define USE_HASH_FUNCTION (1 << 0)
508#define NUMBER_OF_SETS(x) ((x) << 1) 509#define NUMBER_OF_SETS(x) ((x) << 1)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3df4efa11942..b7bf18e40215 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -460,15 +460,28 @@ static void cayman_gpu_init(struct radeon_device *rdev)
460 rdev->config.cayman.max_pipes_per_simd = 4; 460 rdev->config.cayman.max_pipes_per_simd = 4;
461 rdev->config.cayman.max_tile_pipes = 2; 461 rdev->config.cayman.max_tile_pipes = 2;
462 if ((rdev->pdev->device == 0x9900) || 462 if ((rdev->pdev->device == 0x9900) ||
463 (rdev->pdev->device == 0x9901)) { 463 (rdev->pdev->device == 0x9901) ||
464 (rdev->pdev->device == 0x9905) ||
465 (rdev->pdev->device == 0x9906) ||
466 (rdev->pdev->device == 0x9907) ||
467 (rdev->pdev->device == 0x9908) ||
468 (rdev->pdev->device == 0x9909) ||
469 (rdev->pdev->device == 0x9910) ||
470 (rdev->pdev->device == 0x9917)) {
464 rdev->config.cayman.max_simds_per_se = 6; 471 rdev->config.cayman.max_simds_per_se = 6;
465 rdev->config.cayman.max_backends_per_se = 2; 472 rdev->config.cayman.max_backends_per_se = 2;
466 } else if ((rdev->pdev->device == 0x9903) || 473 } else if ((rdev->pdev->device == 0x9903) ||
467 (rdev->pdev->device == 0x9904)) { 474 (rdev->pdev->device == 0x9904) ||
475 (rdev->pdev->device == 0x990A) ||
476 (rdev->pdev->device == 0x9913) ||
477 (rdev->pdev->device == 0x9918)) {
468 rdev->config.cayman.max_simds_per_se = 4; 478 rdev->config.cayman.max_simds_per_se = 4;
469 rdev->config.cayman.max_backends_per_se = 2; 479 rdev->config.cayman.max_backends_per_se = 2;
470 } else if ((rdev->pdev->device == 0x9990) || 480 } else if ((rdev->pdev->device == 0x9919) ||
471 (rdev->pdev->device == 0x9991)) { 481 (rdev->pdev->device == 0x9990) ||
482 (rdev->pdev->device == 0x9991) ||
483 (rdev->pdev->device == 0x9994) ||
484 (rdev->pdev->device == 0x99A0)) {
472 rdev->config.cayman.max_simds_per_se = 3; 485 rdev->config.cayman.max_simds_per_se = 3;
473 rdev->config.cayman.max_backends_per_se = 1; 486 rdev->config.cayman.max_backends_per_se = 1;
474 } else { 487 } else {
@@ -1290,6 +1303,10 @@ static int cayman_startup(struct radeon_device *rdev)
1290 if (r) 1303 if (r)
1291 return r; 1304 return r;
1292 1305
1306 r = r600_audio_init(rdev);
1307 if (r)
1308 return r;
1309
1293 return 0; 1310 return 0;
1294} 1311}
1295 1312
@@ -1316,6 +1333,7 @@ int cayman_resume(struct radeon_device *rdev)
1316 1333
1317int cayman_suspend(struct radeon_device *rdev) 1334int cayman_suspend(struct radeon_device *rdev)
1318{ 1335{
1336 r600_audio_fini(rdev);
1319 /* FIXME: we should wait for ring to be empty */ 1337 /* FIXME: we should wait for ring to be empty */
1320 radeon_ib_pool_suspend(rdev); 1338 radeon_ib_pool_suspend(rdev);
1321 radeon_vm_manager_suspend(rdev); 1339 radeon_vm_manager_suspend(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 45cfcea63507..bff627293812 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
1839 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 1839 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1840 NUM_CLIP_SEQ(3))); 1840 NUM_CLIP_SEQ(3)));
1841 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); 1841 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1842 WREG32(VC_ENHANCE, 0);
1842} 1843}
1843 1844
1844 1845
@@ -2426,6 +2427,12 @@ int r600_startup(struct radeon_device *rdev)
2426 if (r) 2427 if (r)
2427 return r; 2428 return r;
2428 2429
2430 r = r600_audio_init(rdev);
2431 if (r) {
2432 DRM_ERROR("radeon: audio init failed\n");
2433 return r;
2434 }
2435
2429 return 0; 2436 return 0;
2430} 2437}
2431 2438
@@ -2462,12 +2469,6 @@ int r600_resume(struct radeon_device *rdev)
2462 return r; 2469 return r;
2463 } 2470 }
2464 2471
2465 r = r600_audio_init(rdev);
2466 if (r) {
2467 DRM_ERROR("radeon: audio resume failed\n");
2468 return r;
2469 }
2470
2471 return r; 2472 return r;
2472} 2473}
2473 2474
@@ -2577,9 +2578,6 @@ int r600_init(struct radeon_device *rdev)
2577 rdev->accel_working = false; 2578 rdev->accel_working = false;
2578 } 2579 }
2579 2580
2580 r = r600_audio_init(rdev);
2581 if (r)
2582 return r; /* TODO error handling */
2583 return 0; 2581 return 0;
2584} 2582}
2585 2583
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 7c4fa77f018f..79b55916cf90 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,7 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
57 */ 57 */
58static int r600_audio_chipset_supported(struct radeon_device *rdev) 58static int r600_audio_chipset_supported(struct radeon_device *rdev)
59{ 59{
60 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE5(rdev)) 60 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
61 || rdev->family == CHIP_RS600 61 || rdev->family == CHIP_RS600
62 || rdev->family == CHIP_RS690 62 || rdev->family == CHIP_RS690
63 || rdev->family == CHIP_RS740; 63 || rdev->family == CHIP_RS740;
@@ -192,6 +192,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
192 struct radeon_device *rdev = dev->dev_private; 192 struct radeon_device *rdev = dev->dev_private;
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
195 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
195 int base_rate = 48000; 196 int base_rate = 48000;
196 197
197 switch (radeon_encoder->encoder_id) { 198 switch (radeon_encoder->encoder_id) {
@@ -217,8 +218,8 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
217 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10); 218 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
218 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071); 219 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
219 220
220 /* Some magic trigger or src sel? */ 221 /* Select DTO source */
221 WREG32_P(0x5ac, 0x01, ~0x77); 222 WREG32(0x5ac, radeon_crtc->crtc_id);
222 } else { 223 } else {
223 switch (dig->dig_encoder) { 224 switch (dig->dig_encoder) {
224 case 0: 225 case 0:
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0133f5f09bd6..ca87f7afaf23 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2079,6 +2079,48 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2079 return -EINVAL; 2079 return -EINVAL;
2080 } 2080 }
2081 break; 2081 break;
2082 case PACKET3_STRMOUT_BASE_UPDATE:
2083 if (p->family < CHIP_RV770) {
2084 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2085 return -EINVAL;
2086 }
2087 if (pkt->count != 1) {
2088 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2089 return -EINVAL;
2090 }
2091 if (idx_value > 3) {
2092 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2093 return -EINVAL;
2094 }
2095 {
2096 u64 offset;
2097
2098 r = r600_cs_packet_next_reloc(p, &reloc);
2099 if (r) {
2100 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2101 return -EINVAL;
2102 }
2103
2104 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2105 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2106 return -EINVAL;
2107 }
2108
2109 offset = radeon_get_ib_value(p, idx+1) << 8;
2110 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2111 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2112 offset, track->vgt_strmout_bo_offset[idx_value]);
2113 return -EINVAL;
2114 }
2115
2116 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2117 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2118 offset + 4, radeon_bo_size(reloc->robj));
2119 return -EINVAL;
2120 }
2121 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2122 }
2123 break;
2082 case PACKET3_SURFACE_BASE_UPDATE: 2124 case PACKET3_SURFACE_BASE_UPDATE:
2083 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) { 2125 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2084 DRM_ERROR("bad SURFACE_BASE_UPDATE\n"); 2126 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 226379e00ac1..82a0a4c919c0 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -322,9 +322,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
322 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 322 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
323 uint32_t offset; 323 uint32_t offset;
324 324
325 if (ASIC_IS_DCE5(rdev))
326 return;
327
328 /* Silent, r600_hdmi_enable will raise WARN for us */ 325 /* Silent, r600_hdmi_enable will raise WARN for us */
329 if (!dig->afmt->enabled) 326 if (!dig->afmt->enabled)
330 return; 327 return;
@@ -348,7 +345,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
348 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 345 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,
349 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 346 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */
350 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 347 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */
351 HDMI0_AUDIO_SEND_MAX_PACKETS | /* send NULL packets if no audio is available */
352 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 348 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */
353 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ 349 HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
354 } 350 }
@@ -484,7 +480,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
484 uint32_t offset; 480 uint32_t offset;
485 u32 hdmi; 481 u32 hdmi;
486 482
487 if (ASIC_IS_DCE5(rdev)) 483 if (ASIC_IS_DCE6(rdev))
488 return; 484 return;
489 485
490 /* Silent, r600_hdmi_enable will raise WARN for us */ 486 /* Silent, r600_hdmi_enable will raise WARN for us */
@@ -544,7 +540,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
544 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 540 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
545 uint32_t offset; 541 uint32_t offset;
546 542
547 if (ASIC_IS_DCE5(rdev)) 543 if (ASIC_IS_DCE6(rdev))
548 return; 544 return;
549 545
550 /* Called for ATOM_ENCODER_MODE_HDMI only */ 546 /* Called for ATOM_ENCODER_MODE_HDMI only */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a0dbf1fe6a40..025fd5b6c08c 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -485,6 +485,7 @@
485#define TC_L2_SIZE(x) ((x)<<5) 485#define TC_L2_SIZE(x) ((x)<<5)
486#define L2_DISABLE_LATE_HIT (1<<9) 486#define L2_DISABLE_LATE_HIT (1<<9)
487 487
488#define VC_ENHANCE 0x9714
488 489
489#define VGT_CACHE_INVALIDATION 0x88C4 490#define VGT_CACHE_INVALIDATION 0x88C4
490#define CACHE_INVALIDATION(x) ((x)<<0) 491#define CACHE_INVALIDATION(x) ((x)<<0)
@@ -1163,6 +1164,7 @@
1163#define PACKET3_SET_CTL_CONST 0x6F 1164#define PACKET3_SET_CTL_CONST 0x6F
1164#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1165#define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0
1165#define PACKET3_SET_CTL_CONST_END 0x0003e200 1166#define PACKET3_SET_CTL_CONST_END 0x0003e200
1167#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1166#define PACKET3_SURFACE_BASE_UPDATE 0x73 1168#define PACKET3_SURFACE_BASE_UPDATE 0x73
1167 1169
1168 1170
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 85dac33e3cce..fefcca55c1eb 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1374,9 +1374,9 @@ struct cayman_asic {
1374 1374
1375struct si_asic { 1375struct si_asic {
1376 unsigned max_shader_engines; 1376 unsigned max_shader_engines;
1377 unsigned max_pipes_per_simd;
1378 unsigned max_tile_pipes; 1377 unsigned max_tile_pipes;
1379 unsigned max_simds_per_se; 1378 unsigned max_cu_per_sh;
1379 unsigned max_sh_per_se;
1380 unsigned max_backends_per_se; 1380 unsigned max_backends_per_se;
1381 unsigned max_texture_channel_caches; 1381 unsigned max_texture_channel_caches;
1382 unsigned max_gprs; 1382 unsigned max_gprs;
@@ -1387,7 +1387,6 @@ struct si_asic {
1387 unsigned sc_hiz_tile_fifo_size; 1387 unsigned sc_hiz_tile_fifo_size;
1388 unsigned sc_earlyz_tile_fifo_size; 1388 unsigned sc_earlyz_tile_fifo_size;
1389 1389
1390 unsigned num_shader_engines;
1391 unsigned num_tile_pipes; 1390 unsigned num_tile_pipes;
1392 unsigned num_backends_per_se; 1391 unsigned num_backends_per_se;
1393 unsigned backend_disable_mask_per_asic; 1392 unsigned backend_disable_mask_per_asic;
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f0bb2b543b13..2c4d53fd20c5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -57,9 +57,11 @@
57 * 2.13.0 - virtual memory support, streamout 57 * 2.13.0 - virtual memory support, streamout
58 * 2.14.0 - add evergreen tiling informations 58 * 2.14.0 - add evergreen tiling informations
59 * 2.15.0 - add max_pipes query 59 * 2.15.0 - add max_pipes query
60 * 2.16.0 - fix evergreen 2D tiled surface calculation
61 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
60 */ 62 */
61#define KMS_DRIVER_MAJOR 2 63#define KMS_DRIVER_MAJOR 2
62#define KMS_DRIVER_MINOR 15 64#define KMS_DRIVER_MINOR 17
63#define KMS_DRIVER_PATCHLEVEL 0 65#define KMS_DRIVER_PATCHLEVEL 0
64int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 66int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
65int radeon_driver_unload_kms(struct drm_device *dev); 67int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 79db56e6c2ac..84b648a7ddd8 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -289,8 +289,9 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
289 rdev->vm_manager.enabled = false; 289 rdev->vm_manager.enabled = false;
290 290
291 /* mark first vm as always in use, it's the system one */ 291 /* mark first vm as always in use, it's the system one */
292 /* allocate enough for 2 full VM pts */
292 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager, 293 r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
293 rdev->vm_manager.max_pfn * 8, 294 rdev->vm_manager.max_pfn * 8 * 2,
294 RADEON_GEM_DOMAIN_VRAM); 295 RADEON_GEM_DOMAIN_VRAM);
295 if (r) { 296 if (r) {
296 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n", 297 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n",
@@ -476,12 +477,18 @@ int radeon_vm_bo_add(struct radeon_device *rdev,
476 477
477 mutex_lock(&vm->mutex); 478 mutex_lock(&vm->mutex);
478 if (last_pfn > vm->last_pfn) { 479 if (last_pfn > vm->last_pfn) {
479 /* grow va space 32M by 32M */ 480 /* release mutex and lock in right order */
480 unsigned align = ((32 << 20) >> 12) - 1; 481 mutex_unlock(&vm->mutex);
481 radeon_mutex_lock(&rdev->cs_mutex); 482 radeon_mutex_lock(&rdev->cs_mutex);
482 radeon_vm_unbind_locked(rdev, vm); 483 mutex_lock(&vm->mutex);
484 /* and check again */
485 if (last_pfn > vm->last_pfn) {
486 /* grow va space 32M by 32M */
487 unsigned align = ((32 << 20) >> 12) - 1;
488 radeon_vm_unbind_locked(rdev, vm);
489 vm->last_pfn = (last_pfn + align) & ~align;
490 }
483 radeon_mutex_unlock(&rdev->cs_mutex); 491 radeon_mutex_unlock(&rdev->cs_mutex);
484 vm->last_pfn = (last_pfn + align) & ~align;
485 } 492 }
486 head = &vm->va; 493 head = &vm->va;
487 last_offset = 0; 494 last_offset = 0;
@@ -595,8 +602,8 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
595 if (bo_va == NULL) 602 if (bo_va == NULL)
596 return 0; 603 return 0;
597 604
598 mutex_lock(&vm->mutex);
599 radeon_mutex_lock(&rdev->cs_mutex); 605 radeon_mutex_lock(&rdev->cs_mutex);
606 mutex_lock(&vm->mutex);
600 radeon_vm_bo_update_pte(rdev, vm, bo, NULL); 607 radeon_vm_bo_update_pte(rdev, vm, bo, NULL);
601 radeon_mutex_unlock(&rdev->cs_mutex); 608 radeon_mutex_unlock(&rdev->cs_mutex);
602 list_del(&bo_va->vm_list); 609 list_del(&bo_va->vm_list);
@@ -627,7 +634,15 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
627 mutex_init(&vm->mutex); 634 mutex_init(&vm->mutex);
628 INIT_LIST_HEAD(&vm->list); 635 INIT_LIST_HEAD(&vm->list);
629 INIT_LIST_HEAD(&vm->va); 636 INIT_LIST_HEAD(&vm->va);
630 vm->last_pfn = 0; 637 /* SI requires equal sized PTs for all VMs, so always set
638 * last_pfn to max_pfn. cayman allows variable sized
639 * pts so we can grow then as needed. Once we switch
640 * to two level pts we can unify this again.
641 */
642 if (rdev->family >= CHIP_TAHITI)
643 vm->last_pfn = rdev->vm_manager.max_pfn;
644 else
645 vm->last_pfn = 0;
631 /* map the ib pool buffer at 0 in virtual address space, set 646 /* map the ib pool buffer at 0 in virtual address space, set
632 * read only 647 * read only
633 */ 648 */
@@ -641,9 +656,8 @@ void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm)
641 struct radeon_bo_va *bo_va, *tmp; 656 struct radeon_bo_va *bo_va, *tmp;
642 int r; 657 int r;
643 658
644 mutex_lock(&vm->mutex);
645
646 radeon_mutex_lock(&rdev->cs_mutex); 659 radeon_mutex_lock(&rdev->cs_mutex);
660 mutex_lock(&vm->mutex);
647 radeon_vm_unbind_locked(rdev, vm); 661 radeon_vm_unbind_locked(rdev, vm);
648 radeon_mutex_unlock(&rdev->cs_mutex); 662 radeon_mutex_unlock(&rdev->cs_mutex);
649 663
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index f28bd4b7ef98..21ec9f5653ce 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -292,6 +292,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
292int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 292int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
293 struct drm_file *filp) 293 struct drm_file *filp)
294{ 294{
295 struct radeon_device *rdev = dev->dev_private;
295 struct drm_radeon_gem_busy *args = data; 296 struct drm_radeon_gem_busy *args = data;
296 struct drm_gem_object *gobj; 297 struct drm_gem_object *gobj;
297 struct radeon_bo *robj; 298 struct radeon_bo *robj;
@@ -317,13 +318,14 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
317 break; 318 break;
318 } 319 }
319 drm_gem_object_unreference_unlocked(gobj); 320 drm_gem_object_unreference_unlocked(gobj);
320 r = radeon_gem_handle_lockup(robj->rdev, r); 321 r = radeon_gem_handle_lockup(rdev, r);
321 return r; 322 return r;
322} 323}
323 324
324int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 325int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
325 struct drm_file *filp) 326 struct drm_file *filp)
326{ 327{
328 struct radeon_device *rdev = dev->dev_private;
327 struct drm_radeon_gem_wait_idle *args = data; 329 struct drm_radeon_gem_wait_idle *args = data;
328 struct drm_gem_object *gobj; 330 struct drm_gem_object *gobj;
329 struct radeon_bo *robj; 331 struct radeon_bo *robj;
@@ -336,10 +338,10 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
336 robj = gem_to_radeon_bo(gobj); 338 robj = gem_to_radeon_bo(gobj);
337 r = radeon_bo_wait(robj, NULL, false); 339 r = radeon_bo_wait(robj, NULL, false);
338 /* callback hw specific functions if any */ 340 /* callback hw specific functions if any */
339 if (robj->rdev->asic->ioctl_wait_idle) 341 if (rdev->asic->ioctl_wait_idle)
340 robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj); 342 robj->rdev->asic->ioctl_wait_idle(rdev, robj);
341 drm_gem_object_unreference_unlocked(gobj); 343 drm_gem_object_unreference_unlocked(gobj);
342 r = radeon_gem_handle_lockup(robj->rdev, r); 344 r = radeon_gem_handle_lockup(rdev, r);
343 return r; 345 return r;
344} 346}
345 347
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index f1016a5820d1..5c58d7d90cb2 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -273,7 +273,7 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
273 break; 273 break;
274 case RADEON_INFO_MAX_PIPES: 274 case RADEON_INFO_MAX_PIPES:
275 if (rdev->family >= CHIP_TAHITI) 275 if (rdev->family >= CHIP_TAHITI)
276 value = rdev->config.si.max_pipes_per_simd; 276 value = rdev->config.si.max_cu_per_sh;
277 else if (rdev->family >= CHIP_CAYMAN) 277 else if (rdev->family >= CHIP_CAYMAN)
278 value = rdev->config.cayman.max_pipes_per_simd; 278 value = rdev->config.cayman.max_pipes_per_simd;
279 else if (rdev->family >= CHIP_CEDAR) 279 else if (rdev->family >= CHIP_CEDAR)
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 08825548ee69..5b37e283ec38 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -801,9 +801,13 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
801 int i; 801 int i;
802 802
803 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 803 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
804 not_processed += radeon_fence_count_emitted(rdev, i); 804 struct radeon_ring *ring = &rdev->ring[i];
805 if (not_processed >= 3) 805
806 break; 806 if (ring->ready) {
807 not_processed += radeon_fence_count_emitted(rdev, i);
808 if (not_processed >= 3)
809 break;
810 }
807 } 811 }
808 812
809 if (not_processed >= 3) { /* should upclock */ 813 if (not_processed >= 3) { /* should upclock */
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 8ddab4c76710..6bef46ace831 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -169,11 +169,17 @@ struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
169 struct radeon_bo *bo = gem_to_radeon_bo(obj); 169 struct radeon_bo *bo = gem_to_radeon_bo(obj);
170 int ret = 0; 170 int ret = 0;
171 171
172 ret = radeon_bo_reserve(bo, false);
173 if (unlikely(ret != 0))
174 return ERR_PTR(ret);
175
172 /* pin buffer into GTT */ 176 /* pin buffer into GTT */
173 ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL); 177 ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
174 if (ret) 178 if (ret) {
179 radeon_bo_unreserve(bo);
175 return ERR_PTR(ret); 180 return ERR_PTR(ret);
176 181 }
182 radeon_bo_unreserve(bo);
177 return dma_buf_export(bo, &radeon_dmabuf_ops, obj->size, flags); 183 return dma_buf_export(bo, &radeon_dmabuf_ops, obj->size, flags);
178} 184}
179 185
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 25f9eef12c42..e95c5e61d4e2 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -908,12 +908,6 @@ static int rs600_startup(struct radeon_device *rdev)
908 return r; 908 return r;
909 } 909 }
910 910
911 r = r600_audio_init(rdev);
912 if (r) {
913 dev_err(rdev->dev, "failed initializing audio\n");
914 return r;
915 }
916
917 r = radeon_ib_pool_start(rdev); 911 r = radeon_ib_pool_start(rdev);
918 if (r) 912 if (r)
919 return r; 913 return r;
@@ -922,6 +916,12 @@ static int rs600_startup(struct radeon_device *rdev)
922 if (r) 916 if (r)
923 return r; 917 return r;
924 918
919 r = r600_audio_init(rdev);
920 if (r) {
921 dev_err(rdev->dev, "failed initializing audio\n");
922 return r;
923 }
924
925 return 0; 925 return 0;
926} 926}
927 927
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 3277ddecfe9f..159b6a43fda0 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -637,12 +637,6 @@ static int rs690_startup(struct radeon_device *rdev)
637 return r; 637 return r;
638 } 638 }
639 639
640 r = r600_audio_init(rdev);
641 if (r) {
642 dev_err(rdev->dev, "failed initializing audio\n");
643 return r;
644 }
645
646 r = radeon_ib_pool_start(rdev); 640 r = radeon_ib_pool_start(rdev);
647 if (r) 641 if (r)
648 return r; 642 return r;
@@ -651,6 +645,12 @@ static int rs690_startup(struct radeon_device *rdev)
651 if (r) 645 if (r)
652 return r; 646 return r;
653 647
648 r = r600_audio_init(rdev);
649 if (r) {
650 dev_err(rdev->dev, "failed initializing audio\n");
651 return r;
652 }
653
654 return 0; 654 return 0;
655} 655}
656 656
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 04ddc365a908..b4f51c569c36 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
616 ACK_FLUSH_CTL(3) | 616 ACK_FLUSH_CTL(3) |
617 SYNC_FLUSH_CTL)); 617 SYNC_FLUSH_CTL));
618 618
619 if (rdev->family != CHIP_RV770)
620 WREG32(SMX_SAR_CTL0, 0x00003f3f);
621
619 db_debug3 = RREG32(DB_DEBUG3); 622 db_debug3 = RREG32(DB_DEBUG3);
620 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); 623 db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
621 switch (rdev->family) { 624 switch (rdev->family) {
@@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
792 795
793 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | 796 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
794 NUM_CLIP_SEQ(3))); 797 NUM_CLIP_SEQ(3)));
795 798 WREG32(VC_ENHANCE, 0);
796} 799}
797 800
798void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 801void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
@@ -956,6 +959,12 @@ static int rv770_startup(struct radeon_device *rdev)
956 if (r) 959 if (r)
957 return r; 960 return r;
958 961
962 r = r600_audio_init(rdev);
963 if (r) {
964 DRM_ERROR("radeon: audio init failed\n");
965 return r;
966 }
967
959 return 0; 968 return 0;
960} 969}
961 970
@@ -978,12 +987,6 @@ int rv770_resume(struct radeon_device *rdev)
978 return r; 987 return r;
979 } 988 }
980 989
981 r = r600_audio_init(rdev);
982 if (r) {
983 dev_err(rdev->dev, "radeon: audio init failed\n");
984 return r;
985 }
986
987 return r; 990 return r;
988 991
989} 992}
@@ -1092,12 +1095,6 @@ int rv770_init(struct radeon_device *rdev)
1092 rdev->accel_working = false; 1095 rdev->accel_working = false;
1093 } 1096 }
1094 1097
1095 r = r600_audio_init(rdev);
1096 if (r) {
1097 dev_err(rdev->dev, "radeon: audio init failed\n");
1098 return r;
1099 }
1100
1101 return 0; 1098 return 0;
1102} 1099}
1103 1100
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fdc089896011..b0adfc595d75 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -211,6 +211,7 @@
211#define SCRATCH_UMSK 0x8540 211#define SCRATCH_UMSK 0x8540
212#define SCRATCH_ADDR 0x8544 212#define SCRATCH_ADDR 0x8544
213 213
214#define SMX_SAR_CTL0 0xA008
214#define SMX_DC_CTL0 0xA020 215#define SMX_DC_CTL0 0xA020
215#define USE_HASH_FUNCTION (1 << 0) 216#define USE_HASH_FUNCTION (1 << 0)
216#define CACHE_DEPTH(x) ((x) << 1) 217#define CACHE_DEPTH(x) ((x) << 1)
@@ -310,6 +311,8 @@
310#define TCP_CNTL 0x9610 311#define TCP_CNTL 0x9610
311#define TCP_CHAN_STEER 0x9614 312#define TCP_CHAN_STEER 0x9614
312 313
314#define VC_ENHANCE 0x9714
315
313#define VGT_CACHE_INVALIDATION 0x88C4 316#define VGT_CACHE_INVALIDATION 0x88C4
314#define CACHE_INVALIDATION(x) ((x)<<0) 317#define CACHE_INVALIDATION(x) ((x)<<0)
315#define VC_ONLY 0 318#define VC_ONLY 0
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 549732e56ca9..0b0279291a73 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -867,200 +867,6 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
867/* 867/*
868 * Core functions 868 * Core functions
869 */ 869 */
870static u32 si_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
871 u32 num_tile_pipes,
872 u32 num_backends_per_asic,
873 u32 *backend_disable_mask_per_asic,
874 u32 num_shader_engines)
875{
876 u32 backend_map = 0;
877 u32 enabled_backends_mask = 0;
878 u32 enabled_backends_count = 0;
879 u32 num_backends_per_se;
880 u32 cur_pipe;
881 u32 swizzle_pipe[SI_MAX_PIPES];
882 u32 cur_backend = 0;
883 u32 i;
884 bool force_no_swizzle;
885
886 /* force legal values */
887 if (num_tile_pipes < 1)
888 num_tile_pipes = 1;
889 if (num_tile_pipes > rdev->config.si.max_tile_pipes)
890 num_tile_pipes = rdev->config.si.max_tile_pipes;
891 if (num_shader_engines < 1)
892 num_shader_engines = 1;
893 if (num_shader_engines > rdev->config.si.max_shader_engines)
894 num_shader_engines = rdev->config.si.max_shader_engines;
895 if (num_backends_per_asic < num_shader_engines)
896 num_backends_per_asic = num_shader_engines;
897 if (num_backends_per_asic > (rdev->config.si.max_backends_per_se * num_shader_engines))
898 num_backends_per_asic = rdev->config.si.max_backends_per_se * num_shader_engines;
899
900 /* make sure we have the same number of backends per se */
901 num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
902 /* set up the number of backends per se */
903 num_backends_per_se = num_backends_per_asic / num_shader_engines;
904 if (num_backends_per_se > rdev->config.si.max_backends_per_se) {
905 num_backends_per_se = rdev->config.si.max_backends_per_se;
906 num_backends_per_asic = num_backends_per_se * num_shader_engines;
907 }
908
909 /* create enable mask and count for enabled backends */
910 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
911 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
912 enabled_backends_mask |= (1 << i);
913 ++enabled_backends_count;
914 }
915 if (enabled_backends_count == num_backends_per_asic)
916 break;
917 }
918
919 /* force the backends mask to match the current number of backends */
920 if (enabled_backends_count != num_backends_per_asic) {
921 u32 this_backend_enabled;
922 u32 shader_engine;
923 u32 backend_per_se;
924
925 enabled_backends_mask = 0;
926 enabled_backends_count = 0;
927 *backend_disable_mask_per_asic = SI_MAX_BACKENDS_MASK;
928 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
929 /* calc the current se */
930 shader_engine = i / rdev->config.si.max_backends_per_se;
931 /* calc the backend per se */
932 backend_per_se = i % rdev->config.si.max_backends_per_se;
933 /* default to not enabled */
934 this_backend_enabled = 0;
935 if ((shader_engine < num_shader_engines) &&
936 (backend_per_se < num_backends_per_se))
937 this_backend_enabled = 1;
938 if (this_backend_enabled) {
939 enabled_backends_mask |= (1 << i);
940 *backend_disable_mask_per_asic &= ~(1 << i);
941 ++enabled_backends_count;
942 }
943 }
944 }
945
946
947 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * SI_MAX_PIPES);
948 switch (rdev->family) {
949 case CHIP_TAHITI:
950 case CHIP_PITCAIRN:
951 case CHIP_VERDE:
952 force_no_swizzle = true;
953 break;
954 default:
955 force_no_swizzle = false;
956 break;
957 }
958 if (force_no_swizzle) {
959 bool last_backend_enabled = false;
960
961 force_no_swizzle = false;
962 for (i = 0; i < SI_MAX_BACKENDS; ++i) {
963 if (((enabled_backends_mask >> i) & 1) == 1) {
964 if (last_backend_enabled)
965 force_no_swizzle = true;
966 last_backend_enabled = true;
967 } else
968 last_backend_enabled = false;
969 }
970 }
971
972 switch (num_tile_pipes) {
973 case 1:
974 case 3:
975 case 5:
976 case 7:
977 DRM_ERROR("odd number of pipes!\n");
978 break;
979 case 2:
980 swizzle_pipe[0] = 0;
981 swizzle_pipe[1] = 1;
982 break;
983 case 4:
984 if (force_no_swizzle) {
985 swizzle_pipe[0] = 0;
986 swizzle_pipe[1] = 1;
987 swizzle_pipe[2] = 2;
988 swizzle_pipe[3] = 3;
989 } else {
990 swizzle_pipe[0] = 0;
991 swizzle_pipe[1] = 2;
992 swizzle_pipe[2] = 1;
993 swizzle_pipe[3] = 3;
994 }
995 break;
996 case 6:
997 if (force_no_swizzle) {
998 swizzle_pipe[0] = 0;
999 swizzle_pipe[1] = 1;
1000 swizzle_pipe[2] = 2;
1001 swizzle_pipe[3] = 3;
1002 swizzle_pipe[4] = 4;
1003 swizzle_pipe[5] = 5;
1004 } else {
1005 swizzle_pipe[0] = 0;
1006 swizzle_pipe[1] = 2;
1007 swizzle_pipe[2] = 4;
1008 swizzle_pipe[3] = 1;
1009 swizzle_pipe[4] = 3;
1010 swizzle_pipe[5] = 5;
1011 }
1012 break;
1013 case 8:
1014 if (force_no_swizzle) {
1015 swizzle_pipe[0] = 0;
1016 swizzle_pipe[1] = 1;
1017 swizzle_pipe[2] = 2;
1018 swizzle_pipe[3] = 3;
1019 swizzle_pipe[4] = 4;
1020 swizzle_pipe[5] = 5;
1021 swizzle_pipe[6] = 6;
1022 swizzle_pipe[7] = 7;
1023 } else {
1024 swizzle_pipe[0] = 0;
1025 swizzle_pipe[1] = 2;
1026 swizzle_pipe[2] = 4;
1027 swizzle_pipe[3] = 6;
1028 swizzle_pipe[4] = 1;
1029 swizzle_pipe[5] = 3;
1030 swizzle_pipe[6] = 5;
1031 swizzle_pipe[7] = 7;
1032 }
1033 break;
1034 }
1035
1036 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1037 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1038 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1039
1040 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1041
1042 cur_backend = (cur_backend + 1) % SI_MAX_BACKENDS;
1043 }
1044
1045 return backend_map;
1046}
1047
1048static u32 si_get_disable_mask_per_asic(struct radeon_device *rdev,
1049 u32 disable_mask_per_se,
1050 u32 max_disable_mask_per_se,
1051 u32 num_shader_engines)
1052{
1053 u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
1054 u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
1055
1056 if (num_shader_engines == 1)
1057 return disable_mask_per_asic;
1058 else if (num_shader_engines == 2)
1059 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
1060 else
1061 return 0xffffffff;
1062}
1063
1064static void si_tiling_mode_table_init(struct radeon_device *rdev) 870static void si_tiling_mode_table_init(struct radeon_device *rdev)
1065{ 871{
1066 const u32 num_tile_mode_states = 32; 872 const u32 num_tile_mode_states = 32;
@@ -1562,18 +1368,151 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1562 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); 1368 DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
1563} 1369}
1564 1370
1371static void si_select_se_sh(struct radeon_device *rdev,
1372 u32 se_num, u32 sh_num)
1373{
1374 u32 data = INSTANCE_BROADCAST_WRITES;
1375
1376 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1377 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1378 else if (se_num == 0xffffffff)
1379 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1380 else if (sh_num == 0xffffffff)
1381 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1382 else
1383 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1384 WREG32(GRBM_GFX_INDEX, data);
1385}
1386
1387static u32 si_create_bitmask(u32 bit_width)
1388{
1389 u32 i, mask = 0;
1390
1391 for (i = 0; i < bit_width; i++) {
1392 mask <<= 1;
1393 mask |= 1;
1394 }
1395 return mask;
1396}
1397
1398static u32 si_get_cu_enabled(struct radeon_device *rdev, u32 cu_per_sh)
1399{
1400 u32 data, mask;
1401
1402 data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1403 if (data & 1)
1404 data &= INACTIVE_CUS_MASK;
1405 else
1406 data = 0;
1407 data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1408
1409 data >>= INACTIVE_CUS_SHIFT;
1410
1411 mask = si_create_bitmask(cu_per_sh);
1412
1413 return ~data & mask;
1414}
1415
1416static void si_setup_spi(struct radeon_device *rdev,
1417 u32 se_num, u32 sh_per_se,
1418 u32 cu_per_sh)
1419{
1420 int i, j, k;
1421 u32 data, mask, active_cu;
1422
1423 for (i = 0; i < se_num; i++) {
1424 for (j = 0; j < sh_per_se; j++) {
1425 si_select_se_sh(rdev, i, j);
1426 data = RREG32(SPI_STATIC_THREAD_MGMT_3);
1427 active_cu = si_get_cu_enabled(rdev, cu_per_sh);
1428
1429 mask = 1;
1430 for (k = 0; k < 16; k++) {
1431 mask <<= k;
1432 if (active_cu & mask) {
1433 data &= ~mask;
1434 WREG32(SPI_STATIC_THREAD_MGMT_3, data);
1435 break;
1436 }
1437 }
1438 }
1439 }
1440 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1441}
1442
1443static u32 si_get_rb_disabled(struct radeon_device *rdev,
1444 u32 max_rb_num, u32 se_num,
1445 u32 sh_per_se)
1446{
1447 u32 data, mask;
1448
1449 data = RREG32(CC_RB_BACKEND_DISABLE);
1450 if (data & 1)
1451 data &= BACKEND_DISABLE_MASK;
1452 else
1453 data = 0;
1454 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1455
1456 data >>= BACKEND_DISABLE_SHIFT;
1457
1458 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se);
1459
1460 return data & mask;
1461}
1462
1463static void si_setup_rb(struct radeon_device *rdev,
1464 u32 se_num, u32 sh_per_se,
1465 u32 max_rb_num)
1466{
1467 int i, j;
1468 u32 data, mask;
1469 u32 disabled_rbs = 0;
1470 u32 enabled_rbs = 0;
1471
1472 for (i = 0; i < se_num; i++) {
1473 for (j = 0; j < sh_per_se; j++) {
1474 si_select_se_sh(rdev, i, j);
1475 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1476 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
1477 }
1478 }
1479 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1480
1481 mask = 1;
1482 for (i = 0; i < max_rb_num; i++) {
1483 if (!(disabled_rbs & mask))
1484 enabled_rbs |= mask;
1485 mask <<= 1;
1486 }
1487
1488 for (i = 0; i < se_num; i++) {
1489 si_select_se_sh(rdev, i, 0xffffffff);
1490 data = 0;
1491 for (j = 0; j < sh_per_se; j++) {
1492 switch (enabled_rbs & 3) {
1493 case 1:
1494 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1495 break;
1496 case 2:
1497 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1498 break;
1499 case 3:
1500 default:
1501 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1502 break;
1503 }
1504 enabled_rbs >>= 2;
1505 }
1506 WREG32(PA_SC_RASTER_CONFIG, data);
1507 }
1508 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1509}
1510
1565static void si_gpu_init(struct radeon_device *rdev) 1511static void si_gpu_init(struct radeon_device *rdev)
1566{ 1512{
1567 u32 cc_rb_backend_disable = 0;
1568 u32 cc_gc_shader_array_config;
1569 u32 gb_addr_config = 0; 1513 u32 gb_addr_config = 0;
1570 u32 mc_shared_chmap, mc_arb_ramcfg; 1514 u32 mc_shared_chmap, mc_arb_ramcfg;
1571 u32 gb_backend_map;
1572 u32 cgts_tcc_disable;
1573 u32 sx_debug_1; 1515 u32 sx_debug_1;
1574 u32 gc_user_shader_array_config;
1575 u32 gc_user_rb_backend_disable;
1576 u32 cgts_user_tcc_disable;
1577 u32 hdp_host_path_cntl; 1516 u32 hdp_host_path_cntl;
1578 u32 tmp; 1517 u32 tmp;
1579 int i, j; 1518 int i, j;
@@ -1581,9 +1520,9 @@ static void si_gpu_init(struct radeon_device *rdev)
1581 switch (rdev->family) { 1520 switch (rdev->family) {
1582 case CHIP_TAHITI: 1521 case CHIP_TAHITI:
1583 rdev->config.si.max_shader_engines = 2; 1522 rdev->config.si.max_shader_engines = 2;
1584 rdev->config.si.max_pipes_per_simd = 4;
1585 rdev->config.si.max_tile_pipes = 12; 1523 rdev->config.si.max_tile_pipes = 12;
1586 rdev->config.si.max_simds_per_se = 8; 1524 rdev->config.si.max_cu_per_sh = 8;
1525 rdev->config.si.max_sh_per_se = 2;
1587 rdev->config.si.max_backends_per_se = 4; 1526 rdev->config.si.max_backends_per_se = 4;
1588 rdev->config.si.max_texture_channel_caches = 12; 1527 rdev->config.si.max_texture_channel_caches = 12;
1589 rdev->config.si.max_gprs = 256; 1528 rdev->config.si.max_gprs = 256;
@@ -1594,12 +1533,13 @@ static void si_gpu_init(struct radeon_device *rdev)
1594 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1533 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1595 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1534 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1596 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1535 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1536 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 break; 1537 break;
1598 case CHIP_PITCAIRN: 1538 case CHIP_PITCAIRN:
1599 rdev->config.si.max_shader_engines = 2; 1539 rdev->config.si.max_shader_engines = 2;
1600 rdev->config.si.max_pipes_per_simd = 4;
1601 rdev->config.si.max_tile_pipes = 8; 1540 rdev->config.si.max_tile_pipes = 8;
1602 rdev->config.si.max_simds_per_se = 5; 1541 rdev->config.si.max_cu_per_sh = 5;
1542 rdev->config.si.max_sh_per_se = 2;
1603 rdev->config.si.max_backends_per_se = 4; 1543 rdev->config.si.max_backends_per_se = 4;
1604 rdev->config.si.max_texture_channel_caches = 8; 1544 rdev->config.si.max_texture_channel_caches = 8;
1605 rdev->config.si.max_gprs = 256; 1545 rdev->config.si.max_gprs = 256;
@@ -1610,13 +1550,14 @@ static void si_gpu_init(struct radeon_device *rdev)
1610 rdev->config.si.sc_prim_fifo_size_backend = 0x100; 1550 rdev->config.si.sc_prim_fifo_size_backend = 0x100;
1611 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1551 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1612 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1552 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1553 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1613 break; 1554 break;
1614 case CHIP_VERDE: 1555 case CHIP_VERDE:
1615 default: 1556 default:
1616 rdev->config.si.max_shader_engines = 1; 1557 rdev->config.si.max_shader_engines = 1;
1617 rdev->config.si.max_pipes_per_simd = 4;
1618 rdev->config.si.max_tile_pipes = 4; 1558 rdev->config.si.max_tile_pipes = 4;
1619 rdev->config.si.max_simds_per_se = 2; 1559 rdev->config.si.max_cu_per_sh = 2;
1560 rdev->config.si.max_sh_per_se = 2;
1620 rdev->config.si.max_backends_per_se = 4; 1561 rdev->config.si.max_backends_per_se = 4;
1621 rdev->config.si.max_texture_channel_caches = 4; 1562 rdev->config.si.max_texture_channel_caches = 4;
1622 rdev->config.si.max_gprs = 256; 1563 rdev->config.si.max_gprs = 256;
@@ -1627,6 +1568,7 @@ static void si_gpu_init(struct radeon_device *rdev)
1627 rdev->config.si.sc_prim_fifo_size_backend = 0x40; 1568 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1628 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; 1569 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1629 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1570 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1571 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1630 break; 1572 break;
1631 } 1573 }
1632 1574
@@ -1648,31 +1590,7 @@ static void si_gpu_init(struct radeon_device *rdev)
1648 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); 1590 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1649 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); 1591 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1650 1592
1651 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
1652 cc_gc_shader_array_config = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
1653 cgts_tcc_disable = 0xffff0000;
1654 for (i = 0; i < rdev->config.si.max_texture_channel_caches; i++)
1655 cgts_tcc_disable &= ~(1 << (16 + i));
1656 gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
1657 gc_user_shader_array_config = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
1658 cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
1659
1660 rdev->config.si.num_shader_engines = rdev->config.si.max_shader_engines;
1661 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; 1593 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes;
1662 tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1663 rdev->config.si.num_backends_per_se = r600_count_pipe_bits(tmp);
1664 tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
1665 rdev->config.si.backend_disable_mask_per_asic =
1666 si_get_disable_mask_per_asic(rdev, tmp, SI_MAX_BACKENDS_PER_SE_MASK,
1667 rdev->config.si.num_shader_engines);
1668 rdev->config.si.backend_map =
1669 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1670 rdev->config.si.num_backends_per_se *
1671 rdev->config.si.num_shader_engines,
1672 &rdev->config.si.backend_disable_mask_per_asic,
1673 rdev->config.si.num_shader_engines);
1674 tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
1675 rdev->config.si.num_texture_channel_caches = r600_count_pipe_bits(tmp);
1676 rdev->config.si.mem_max_burst_length_bytes = 256; 1594 rdev->config.si.mem_max_burst_length_bytes = 256;
1677 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT; 1595 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1678 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; 1596 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
@@ -1683,55 +1601,8 @@ static void si_gpu_init(struct radeon_device *rdev)
1683 rdev->config.si.num_gpus = 1; 1601 rdev->config.si.num_gpus = 1;
1684 rdev->config.si.multi_gpu_tile_size = 64; 1602 rdev->config.si.multi_gpu_tile_size = 64;
1685 1603
1686 gb_addr_config = 0; 1604 /* fix up row size */
1687 switch (rdev->config.si.num_tile_pipes) { 1605 gb_addr_config &= ~ROW_SIZE_MASK;
1688 case 1:
1689 gb_addr_config |= NUM_PIPES(0);
1690 break;
1691 case 2:
1692 gb_addr_config |= NUM_PIPES(1);
1693 break;
1694 case 4:
1695 gb_addr_config |= NUM_PIPES(2);
1696 break;
1697 case 8:
1698 default:
1699 gb_addr_config |= NUM_PIPES(3);
1700 break;
1701 }
1702
1703 tmp = (rdev->config.si.mem_max_burst_length_bytes / 256) - 1;
1704 gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
1705 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.si.num_shader_engines - 1);
1706 tmp = (rdev->config.si.shader_engine_tile_size / 16) - 1;
1707 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
1708 switch (rdev->config.si.num_gpus) {
1709 case 1:
1710 default:
1711 gb_addr_config |= NUM_GPUS(0);
1712 break;
1713 case 2:
1714 gb_addr_config |= NUM_GPUS(1);
1715 break;
1716 case 4:
1717 gb_addr_config |= NUM_GPUS(2);
1718 break;
1719 }
1720 switch (rdev->config.si.multi_gpu_tile_size) {
1721 case 16:
1722 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
1723 break;
1724 case 32:
1725 default:
1726 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
1727 break;
1728 case 64:
1729 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1730 break;
1731 case 128:
1732 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
1733 break;
1734 }
1735 switch (rdev->config.si.mem_row_size_in_kb) { 1606 switch (rdev->config.si.mem_row_size_in_kb) {
1736 case 1: 1607 case 1:
1737 default: 1608 default:
@@ -1745,26 +1616,6 @@ static void si_gpu_init(struct radeon_device *rdev)
1745 break; 1616 break;
1746 } 1617 }
1747 1618
1748 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1749 rdev->config.si.num_tile_pipes = (1 << tmp);
1750 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1751 rdev->config.si.mem_max_burst_length_bytes = (tmp + 1) * 256;
1752 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1753 rdev->config.si.num_shader_engines = tmp + 1;
1754 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1755 rdev->config.si.num_gpus = tmp + 1;
1756 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1757 rdev->config.si.multi_gpu_tile_size = 1 << tmp;
1758 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1759 rdev->config.si.mem_row_size_in_kb = 1 << tmp;
1760
1761 gb_backend_map =
1762 si_get_tile_pipe_to_backend_map(rdev, rdev->config.si.num_tile_pipes,
1763 rdev->config.si.num_backends_per_se *
1764 rdev->config.si.num_shader_engines,
1765 &rdev->config.si.backend_disable_mask_per_asic,
1766 rdev->config.si.num_shader_engines);
1767
1768 /* setup tiling info dword. gb_addr_config is not adequate since it does 1619 /* setup tiling info dword. gb_addr_config is not adequate since it does
1769 * not have bank info, so create a custom tiling dword. 1620 * not have bank info, so create a custom tiling dword.
1770 * bits 3:0 num_pipes 1621 * bits 3:0 num_pipes
@@ -1789,33 +1640,29 @@ static void si_gpu_init(struct radeon_device *rdev)
1789 rdev->config.si.tile_config |= (3 << 0); 1640 rdev->config.si.tile_config |= (3 << 0);
1790 break; 1641 break;
1791 } 1642 }
1792 rdev->config.si.tile_config |= 1643 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1793 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4; 1644 rdev->config.si.tile_config |= 1 << 4;
1645 else
1646 rdev->config.si.tile_config |= 0 << 4;
1794 rdev->config.si.tile_config |= 1647 rdev->config.si.tile_config |=
1795 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; 1648 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1796 rdev->config.si.tile_config |= 1649 rdev->config.si.tile_config |=
1797 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12; 1650 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1798 1651
1799 rdev->config.si.backend_map = gb_backend_map;
1800 WREG32(GB_ADDR_CONFIG, gb_addr_config); 1652 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1801 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1653 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1802 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1654 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1803 1655
1804 /* primary versions */ 1656 si_tiling_mode_table_init(rdev);
1805 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1806 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1807 WREG32(CC_GC_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1808
1809 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1810 1657
1811 /* user versions */ 1658 si_setup_rb(rdev, rdev->config.si.max_shader_engines,
1812 WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1659 rdev->config.si.max_sh_per_se,
1813 WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1660 rdev->config.si.max_backends_per_se);
1814 WREG32(GC_USER_SHADER_ARRAY_CONFIG, cc_gc_shader_array_config);
1815 1661
1816 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable); 1662 si_setup_spi(rdev, rdev->config.si.max_shader_engines,
1663 rdev->config.si.max_sh_per_se,
1664 rdev->config.si.max_cu_per_sh);
1817 1665
1818 si_tiling_mode_table_init(rdev);
1819 1666
1820 /* set HW defaults for 3D engine */ 1667 /* set HW defaults for 3D engine */
1821 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 1668 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
@@ -2518,12 +2365,12 @@ int si_pcie_gart_enable(struct radeon_device *rdev)
2518 WREG32(0x15DC, 0); 2365 WREG32(0x15DC, 0);
2519 2366
2520 /* empty context1-15 */ 2367 /* empty context1-15 */
2521 /* FIXME start with 1G, once using 2 level pt switch to full 2368 /* FIXME start with 4G, once using 2 level pt switch to full
2522 * vm size space 2369 * vm size space
2523 */ 2370 */
2524 /* set vm size, must be a multiple of 4 */ 2371 /* set vm size, must be a multiple of 4 */
2525 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); 2372 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
2526 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE); 2373 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
2527 for (i = 1; i < 16; i++) { 2374 for (i = 1; i < 16; i++) {
2528 if (i < 8) 2375 if (i < 8)
2529 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), 2376 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h
index eda938a7cb6e..501f9d431d57 100644
--- a/drivers/gpu/drm/radeon/si_reg.h
+++ b/drivers/gpu/drm/radeon/si_reg.h
@@ -30,4 +30,76 @@
30#define SI_DC_GPIO_HPD_EN 0x65b8 30#define SI_DC_GPIO_HPD_EN 0x65b8
31#define SI_DC_GPIO_HPD_Y 0x65bc 31#define SI_DC_GPIO_HPD_Y 0x65bc
32 32
33#define SI_GRPH_CONTROL 0x6804
34# define SI_GRPH_DEPTH(x) (((x) & 0x3) << 0)
35# define SI_GRPH_DEPTH_8BPP 0
36# define SI_GRPH_DEPTH_16BPP 1
37# define SI_GRPH_DEPTH_32BPP 2
38# define SI_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
39# define SI_ADDR_SURF_2_BANK 0
40# define SI_ADDR_SURF_4_BANK 1
41# define SI_ADDR_SURF_8_BANK 2
42# define SI_ADDR_SURF_16_BANK 3
43# define SI_GRPH_Z(x) (((x) & 0x3) << 4)
44# define SI_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
45# define SI_ADDR_SURF_BANK_WIDTH_1 0
46# define SI_ADDR_SURF_BANK_WIDTH_2 1
47# define SI_ADDR_SURF_BANK_WIDTH_4 2
48# define SI_ADDR_SURF_BANK_WIDTH_8 3
49# define SI_GRPH_FORMAT(x) (((x) & 0x7) << 8)
50/* 8 BPP */
51# define SI_GRPH_FORMAT_INDEXED 0
52/* 16 BPP */
53# define SI_GRPH_FORMAT_ARGB1555 0
54# define SI_GRPH_FORMAT_ARGB565 1
55# define SI_GRPH_FORMAT_ARGB4444 2
56# define SI_GRPH_FORMAT_AI88 3
57# define SI_GRPH_FORMAT_MONO16 4
58# define SI_GRPH_FORMAT_BGRA5551 5
59/* 32 BPP */
60# define SI_GRPH_FORMAT_ARGB8888 0
61# define SI_GRPH_FORMAT_ARGB2101010 1
62# define SI_GRPH_FORMAT_32BPP_DIG 2
63# define SI_GRPH_FORMAT_8B_ARGB2101010 3
64# define SI_GRPH_FORMAT_BGRA1010102 4
65# define SI_GRPH_FORMAT_8B_BGRA1010102 5
66# define SI_GRPH_FORMAT_RGB111110 6
67# define SI_GRPH_FORMAT_BGR101111 7
68# define SI_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
69# define SI_ADDR_SURF_BANK_HEIGHT_1 0
70# define SI_ADDR_SURF_BANK_HEIGHT_2 1
71# define SI_ADDR_SURF_BANK_HEIGHT_4 2
72# define SI_ADDR_SURF_BANK_HEIGHT_8 3
73# define SI_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
74# define SI_ADDR_SURF_TILE_SPLIT_64B 0
75# define SI_ADDR_SURF_TILE_SPLIT_128B 1
76# define SI_ADDR_SURF_TILE_SPLIT_256B 2
77# define SI_ADDR_SURF_TILE_SPLIT_512B 3
78# define SI_ADDR_SURF_TILE_SPLIT_1KB 4
79# define SI_ADDR_SURF_TILE_SPLIT_2KB 5
80# define SI_ADDR_SURF_TILE_SPLIT_4KB 6
81# define SI_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
82# define SI_ADDR_SURF_MACRO_TILE_ASPECT_1 0
83# define SI_ADDR_SURF_MACRO_TILE_ASPECT_2 1
84# define SI_ADDR_SURF_MACRO_TILE_ASPECT_4 2
85# define SI_ADDR_SURF_MACRO_TILE_ASPECT_8 3
86# define SI_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
87# define SI_GRPH_ARRAY_LINEAR_GENERAL 0
88# define SI_GRPH_ARRAY_LINEAR_ALIGNED 1
89# define SI_GRPH_ARRAY_1D_TILED_THIN1 2
90# define SI_GRPH_ARRAY_2D_TILED_THIN1 4
91# define SI_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
92# define SI_ADDR_SURF_P2 0
93# define SI_ADDR_SURF_P4_8x16 4
94# define SI_ADDR_SURF_P4_16x16 5
95# define SI_ADDR_SURF_P4_16x32 6
96# define SI_ADDR_SURF_P4_32x32 7
97# define SI_ADDR_SURF_P8_16x16_8x16 8
98# define SI_ADDR_SURF_P8_16x32_8x16 9
99# define SI_ADDR_SURF_P8_32x32_8x16 10
100# define SI_ADDR_SURF_P8_16x32_16x16 11
101# define SI_ADDR_SURF_P8_32x32_16x16 12
102# define SI_ADDR_SURF_P8_32x32_16x32 13
103# define SI_ADDR_SURF_P8_32x64_32x32 14
104
33#endif 105#endif
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 53ea2c42dbd6..db4067962868 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -24,6 +24,11 @@
24#ifndef SI_H 24#ifndef SI_H
25#define SI_H 25#define SI_H
26 26
27#define TAHITI_RB_BITMAP_WIDTH_PER_SH 2
28
29#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
30#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
31
27#define CG_MULT_THERMAL_STATUS 0x714 32#define CG_MULT_THERMAL_STATUS 0x714
28#define ASIC_MAX_TEMP(x) ((x) << 0) 33#define ASIC_MAX_TEMP(x) ((x) << 0)
29#define ASIC_MAX_TEMP_MASK 0x000001ff 34#define ASIC_MAX_TEMP_MASK 0x000001ff
@@ -408,6 +413,12 @@
408#define SOFT_RESET_IA (1 << 15) 413#define SOFT_RESET_IA (1 << 15)
409 414
410#define GRBM_GFX_INDEX 0x802C 415#define GRBM_GFX_INDEX 0x802C
416#define INSTANCE_INDEX(x) ((x) << 0)
417#define SH_INDEX(x) ((x) << 8)
418#define SE_INDEX(x) ((x) << 16)
419#define SH_BROADCAST_WRITES (1 << 29)
420#define INSTANCE_BROADCAST_WRITES (1 << 30)
421#define SE_BROADCAST_WRITES (1 << 31)
411 422
412#define GRBM_INT_CNTL 0x8060 423#define GRBM_INT_CNTL 0x8060
413# define RDERR_INT_ENABLE (1 << 0) 424# define RDERR_INT_ENABLE (1 << 0)
@@ -480,6 +491,8 @@
480#define VGT_TF_MEMORY_BASE 0x89B8 491#define VGT_TF_MEMORY_BASE 0x89B8
481 492
482#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 493#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
494#define INACTIVE_CUS_MASK 0xFFFF0000
495#define INACTIVE_CUS_SHIFT 16
483#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 496#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
484 497
485#define PA_CL_ENHANCE 0x8A14 498#define PA_CL_ENHANCE 0x8A14
@@ -688,6 +701,12 @@
688#define RLC_MC_CNTL 0xC344 701#define RLC_MC_CNTL 0xC344
689#define RLC_UCODE_CNTL 0xC348 702#define RLC_UCODE_CNTL 0xC348
690 703
704#define PA_SC_RASTER_CONFIG 0x28350
705# define RASTER_CONFIG_RB_MAP_0 0
706# define RASTER_CONFIG_RB_MAP_1 1
707# define RASTER_CONFIG_RB_MAP_2 2
708# define RASTER_CONFIG_RB_MAP_3 3
709
691#define VGT_EVENT_INITIATOR 0x28a90 710#define VGT_EVENT_INITIATOR 0x28a90
692# define SAMPLE_STREAMOUTSTATS1 (1 << 0) 711# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
693# define SAMPLE_STREAMOUTSTATS2 (2 << 0) 712# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c
index 30d98d14b5c5..dd14cd1a0033 100644
--- a/drivers/gpu/drm/sis/sis_drv.c
+++ b/drivers/gpu/drm/sis/sis_drv.c
@@ -47,9 +47,9 @@ static int sis_driver_load(struct drm_device *dev, unsigned long chipset)
47 if (dev_priv == NULL) 47 if (dev_priv == NULL)
48 return -ENOMEM; 48 return -ENOMEM;
49 49
50 idr_init(&dev_priv->object_idr);
50 dev->dev_private = (void *)dev_priv; 51 dev->dev_private = (void *)dev_priv;
51 dev_priv->chipset = chipset; 52 dev_priv->chipset = chipset;
52 idr_init(&dev->object_name_idr);
53 53
54 return 0; 54 return 0;
55} 55}
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index b67cfcaa661f..36f4b28c1b90 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -1204,6 +1204,7 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
1204 (*destroy)(bo); 1204 (*destroy)(bo);
1205 else 1205 else
1206 kfree(bo); 1206 kfree(bo);
1207 ttm_mem_global_free(mem_glob, acc_size);
1207 return -EINVAL; 1208 return -EINVAL;
1208 } 1209 }
1209 bo->destroy = destroy; 1210 bo->destroy = destroy;
@@ -1307,22 +1308,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev,
1307 struct ttm_buffer_object **p_bo) 1308 struct ttm_buffer_object **p_bo)
1308{ 1309{
1309 struct ttm_buffer_object *bo; 1310 struct ttm_buffer_object *bo;
1310 struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
1311 size_t acc_size; 1311 size_t acc_size;
1312 int ret; 1312 int ret;
1313 1313
1314 acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
1315 ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
1316 if (unlikely(ret != 0))
1317 return ret;
1318
1319 bo = kzalloc(sizeof(*bo), GFP_KERNEL); 1314 bo = kzalloc(sizeof(*bo), GFP_KERNEL);
1320 1315 if (unlikely(bo == NULL))
1321 if (unlikely(bo == NULL)) {
1322 ttm_mem_global_free(mem_glob, acc_size);
1323 return -ENOMEM; 1316 return -ENOMEM;
1324 }
1325 1317
1318 acc_size = ttm_bo_acc_size(bdev, size, sizeof(struct ttm_buffer_object));
1326 ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment, 1319 ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
1327 buffer_start, interruptible, 1320 buffer_start, interruptible,
1328 persistent_swap_storage, acc_size, NULL, NULL); 1321 persistent_swap_storage, acc_size, NULL, NULL);
diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c
index 4d02c46a9420..6e52069894b3 100644
--- a/drivers/gpu/drm/udl/udl_drv.c
+++ b/drivers/gpu/drm/udl/udl_drv.c
@@ -13,8 +13,21 @@
13 13
14static struct drm_driver driver; 14static struct drm_driver driver;
15 15
16/*
17 * There are many DisplayLink-based graphics products, all with unique PIDs.
18 * So we match on DisplayLink's VID + Vendor-Defined Interface Class (0xff)
19 * We also require a match on SubClass (0x00) and Protocol (0x00),
20 * which is compatible with all known USB 2.0 era graphics chips and firmware,
21 * but allows DisplayLink to increment those for any future incompatible chips
22 */
16static struct usb_device_id id_table[] = { 23static struct usb_device_id id_table[] = {
17 {.idVendor = 0x17e9, .match_flags = USB_DEVICE_ID_MATCH_VENDOR,}, 24 {.idVendor = 0x17e9, .bInterfaceClass = 0xff,
25 .bInterfaceSubClass = 0x00,
26 .bInterfaceProtocol = 0x00,
27 .match_flags = USB_DEVICE_ID_MATCH_VENDOR |
28 USB_DEVICE_ID_MATCH_INT_CLASS |
29 USB_DEVICE_ID_MATCH_INT_SUBCLASS |
30 USB_DEVICE_ID_MATCH_INT_PROTOCOL,},
18 {}, 31 {},
19}; 32};
20MODULE_DEVICE_TABLE(usb, id_table); 33MODULE_DEVICE_TABLE(usb, id_table);
diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c
index a8d5f09428c7..4c2d836a0893 100644
--- a/drivers/gpu/drm/udl/udl_main.c
+++ b/drivers/gpu/drm/udl/udl_main.c
@@ -61,7 +61,7 @@ static int udl_parse_vendor_descriptor(struct drm_device *dev,
61 u8 length; 61 u8 length;
62 u16 key; 62 u16 key;
63 63
64 key = *((u16 *) desc); 64 key = le16_to_cpu(*((u16 *) desc));
65 desc += sizeof(u16); 65 desc += sizeof(u16);
66 length = *desc; 66 length = *desc;
67 desc++; 67 desc++;
diff --git a/drivers/gpu/drm/via/via_map.c b/drivers/gpu/drm/via/via_map.c
index 1f182254e81e..c126182ac07e 100644
--- a/drivers/gpu/drm/via/via_map.c
+++ b/drivers/gpu/drm/via/via_map.c
@@ -100,12 +100,11 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset)
100 if (dev_priv == NULL) 100 if (dev_priv == NULL)
101 return -ENOMEM; 101 return -ENOMEM;
102 102
103 idr_init(&dev_priv->object_idr);
103 dev->dev_private = (void *)dev_priv; 104 dev->dev_private = (void *)dev_priv;
104 105
105 dev_priv->chipset = chipset; 106 dev_priv->chipset = chipset;
106 107
107 idr_init(&dev->object_name_idr);
108
109 pci_set_master(dev->pdev); 108 pci_set_master(dev->pdev);
110 109
111 ret = drm_vblank_init(dev, 1); 110 ret = drm_vblank_init(dev, 1);
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 38f9534ac513..5b3c7d135dc9 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -190,6 +190,19 @@ find_active_client(struct list_head *head)
190 return NULL; 190 return NULL;
191} 191}
192 192
193int vga_switcheroo_get_client_state(struct pci_dev *pdev)
194{
195 struct vga_switcheroo_client *client;
196
197 client = find_client_from_pci(&vgasr_priv.clients, pdev);
198 if (!client)
199 return VGA_SWITCHEROO_NOT_FOUND;
200 if (!vgasr_priv.active)
201 return VGA_SWITCHEROO_INIT;
202 return client->pwr_state;
203}
204EXPORT_SYMBOL(vga_switcheroo_get_client_state);
205
193void vga_switcheroo_unregister_client(struct pci_dev *pdev) 206void vga_switcheroo_unregister_client(struct pci_dev *pdev)
194{ 207{
195 struct vga_switcheroo_client *client; 208 struct vga_switcheroo_client *client;
@@ -291,8 +304,6 @@ static int vga_switchto_stage1(struct vga_switcheroo_client *new_client)
291 vga_switchon(new_client); 304 vga_switchon(new_client);
292 305
293 vga_set_default_device(new_client->pdev); 306 vga_set_default_device(new_client->pdev);
294 set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
295
296 return 0; 307 return 0;
297} 308}
298 309
@@ -308,6 +319,8 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
308 319
309 active->active = false; 320 active->active = false;
310 321
322 set_audio_state(active->id, VGA_SWITCHEROO_OFF);
323
311 if (new_client->fb_info) { 324 if (new_client->fb_info) {
312 struct fb_event event; 325 struct fb_event event;
313 event.info = new_client->fb_info; 326 event.info = new_client->fb_info;
@@ -321,11 +334,11 @@ static int vga_switchto_stage2(struct vga_switcheroo_client *new_client)
321 if (new_client->ops->reprobe) 334 if (new_client->ops->reprobe)
322 new_client->ops->reprobe(new_client->pdev); 335 new_client->ops->reprobe(new_client->pdev);
323 336
324 set_audio_state(active->id, VGA_SWITCHEROO_OFF);
325
326 if (active->pwr_state == VGA_SWITCHEROO_ON) 337 if (active->pwr_state == VGA_SWITCHEROO_ON)
327 vga_switchoff(active); 338 vga_switchoff(active);
328 339
340 set_audio_state(new_client->id, VGA_SWITCHEROO_ON);
341
329 new_client->active = true; 342 new_client->active = true;
330 return 0; 343 return 0;
331} 344}
@@ -371,8 +384,9 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
371 /* pwr off the device not in use */ 384 /* pwr off the device not in use */
372 if (strncmp(usercmd, "OFF", 3) == 0) { 385 if (strncmp(usercmd, "OFF", 3) == 0) {
373 list_for_each_entry(client, &vgasr_priv.clients, list) { 386 list_for_each_entry(client, &vgasr_priv.clients, list) {
374 if (client->active) 387 if (client->active || client_is_audio(client))
375 continue; 388 continue;
389 set_audio_state(client->id, VGA_SWITCHEROO_OFF);
376 if (client->pwr_state == VGA_SWITCHEROO_ON) 390 if (client->pwr_state == VGA_SWITCHEROO_ON)
377 vga_switchoff(client); 391 vga_switchoff(client);
378 } 392 }
@@ -381,10 +395,11 @@ vga_switcheroo_debugfs_write(struct file *filp, const char __user *ubuf,
381 /* pwr on the device not in use */ 395 /* pwr on the device not in use */
382 if (strncmp(usercmd, "ON", 2) == 0) { 396 if (strncmp(usercmd, "ON", 2) == 0) {
383 list_for_each_entry(client, &vgasr_priv.clients, list) { 397 list_for_each_entry(client, &vgasr_priv.clients, list) {
384 if (client->active) 398 if (client->active || client_is_audio(client))
385 continue; 399 continue;
386 if (client->pwr_state == VGA_SWITCHEROO_OFF) 400 if (client->pwr_state == VGA_SWITCHEROO_OFF)
387 vga_switchon(client); 401 vga_switchon(client);
402 set_audio_state(client->id, VGA_SWITCHEROO_ON);
388 } 403 }
389 goto out; 404 goto out;
390 } 405 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-24 13:48:42 -0500