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authorBen Skeggs <bskeggs@redhat.com>2014-08-09 14:10:27 -0400
committerBen Skeggs <bskeggs@redhat.com>2014-08-09 15:28:11 -0400
commit648d4dfde721885737b33a06f2b73ee125acf271 (patch)
tree5ad1a46f4de17e82d59b87c247f3b678f3ac7e41 /drivers/gpu
parent4952b4d339033c2019bbd00f28f422b6fc340408 (diff)
drm/nouveau/disp: audit and version display classes
The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/copy/nva3.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c2
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/copy/nve0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/device/base.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/dport.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/gm107.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv04.c3
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c100
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.h1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv84.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv94.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nva0.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nva3.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c13
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nve0.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c14
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c29
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c7
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c22
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv04.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv10.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv20.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv25.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv30.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv34.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv35.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv40.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nv04.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nv10.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nv50.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/software/nvc0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/include/core/class.h165
-rw-r--r--drivers/gpu/drm/nouveau/core/include/engine/perfmon.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_display.c26
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.c1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drm.h2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c157
-rw-r--r--drivers/gpu/drm/nouveau/nvif/class.h86
52 files changed, 323 insertions, 423 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
index f31527733e00..abb410ef09ea 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
@@ -30,7 +30,6 @@
30#include <subdev/vm.h> 30#include <subdev/vm.h>
31 31
32#include <core/client.h> 32#include <core/client.h>
33#include <core/class.h>
34#include <core/enum.h> 33#include <core/enum.h>
35 34
36 35
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
index ac3291f781f6..9261694d0d35 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c
@@ -26,9 +26,7 @@
26#include <engine/fifo.h> 26#include <engine/fifo.h>
27#include <engine/copy.h> 27#include <engine/copy.h>
28 28
29#include <core/class.h>
30#include <core/enum.h> 29#include <core/enum.h>
31#include <core/class.h>
32#include <core/enum.h> 30#include <core/enum.h>
33 31
34#include "fuc/nvc0.fuc.h" 32#include "fuc/nvc0.fuc.h"
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
index 748a61eb3c6f..c7194b354605 100644
--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c
@@ -24,7 +24,6 @@
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/enum.h> 26#include <core/enum.h>
27#include <core/class.h>
28#include <core/engctx.h> 27#include <core/engctx.h>
29 28
30#include <engine/copy.h> 29#include <engine/copy.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
index 2551dafbec73..ea5c42f31791 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
@@ -25,7 +25,6 @@
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/enum.h> 27#include <core/enum.h>
28#include <core/class.h>
29#include <core/engctx.h> 28#include <core/engctx.h>
30#include <core/gpuobj.h> 29#include <core/gpuobj.h>
31 30
diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
index c7082377ec76..5571c09534cb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
+++ b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
@@ -25,7 +25,6 @@
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/enum.h> 27#include <core/enum.h>
28#include <core/class.h>
29#include <core/engctx.h> 28#include <core/engctx.h>
30 29
31#include <subdev/timer.h> 30#include <subdev/timer.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c
index c7e9794a3abc..e4e089b65a01 100644
--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/core/engine/device/base.c
@@ -28,7 +28,6 @@
28#include <core/option.h> 28#include <core/option.h>
29#include <nvif/unpack.h> 29#include <nvif/unpack.h>
30#include <nvif/class.h> 30#include <nvif/class.h>
31#include <core/class.h>
32 31
33#include <subdev/fb.h> 32#include <subdev/fb.h>
34#include <subdev/instmem.h> 33#include <subdev/instmem.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index e0932b7c654c..b36addff06a9 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/class.h>
27#include <nvif/unpack.h> 26#include <nvif/unpack.h>
28#include <nvif/class.h> 27#include <nvif/class.h>
29 28
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
index 157bda97f59e..39890221b91c 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c
@@ -30,7 +30,7 @@
30 30
31#include <engine/disp.h> 31#include <engine/disp.h>
32 32
33#include <core/class.h> 33#include <nvif/class.h>
34 34
35#include "dport.h" 35#include "dport.h"
36#include "outpdp.h" 36#include "outpdp.h"
@@ -335,7 +335,7 @@ nouveau_dp_train(struct work_struct *w)
335 int ret; 335 int ret;
336 336
337 /* bring capabilities within encoder limits */ 337 /* bring capabilities within encoder limits */
338 if (nv_mclass(disp) < NVD0_DISP_CLASS) 338 if (nv_mclass(disp) < GF110_DISP)
339 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; 339 outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED;
340 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { 340 if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) {
341 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; 341 outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
index 6a25f38d7fbf..d54da8b5f87e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -35,17 +35,17 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37gm107_disp_sclass[] = { 37gm107_disp_sclass[] = {
38 { GM107_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base }, 38 { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
39 { GM107_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base }, 39 { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
40 { GM107_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base }, 40 { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
41 { GM107_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base }, 41 { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
42 { GM107_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base }, 42 { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45
46static struct nouveau_oclass 46static struct nouveau_oclass
47gm107_disp_base_oclass[] = { 47gm107_disp_base_oclass[] = {
48 { GM107_DISP_CLASS, &nvd0_disp_base_ofuncs }, 48 { GM107_DISP, &nvd0_disp_base_ofuncs },
49 {} 49 {}
50}; 50};
51 51
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
index 6dba53df35fc..9f0ae05f7d37 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
@@ -26,7 +26,6 @@
26 26
27#include <core/client.h> 27#include <core/client.h>
28#include <core/event.h> 28#include <core/event.h>
29#include <core/class.h>
30#include <nvif/unpack.h> 29#include <nvif/unpack.h>
31#include <nvif/class.h> 30#include <nvif/class.h>
32 31
@@ -117,7 +116,7 @@ nv04_disp_ofuncs = {
117 116
118static struct nouveau_oclass 117static struct nouveau_oclass
119nv04_disp_sclass[] = { 118nv04_disp_sclass[] = {
120 { NV04_DISP_CLASS, &nv04_disp_ofuncs }, 119 { NV04_DISP, &nv04_disp_ofuncs },
121 {}, 120 {},
122}; 121};
123 122
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 7e60c11d7d36..8dafd4106568 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -27,7 +27,6 @@
27#include <core/parent.h> 27#include <core/parent.h>
28#include <core/handle.h> 28#include <core/handle.h>
29#include <core/enum.h> 29#include <core/enum.h>
30#include <core/class.h>
31#include <nvif/unpack.h> 30#include <nvif/unpack.h>
32#include <nvif/class.h> 31#include <nvif/class.h>
33 32
@@ -410,14 +409,21 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
410 struct nouveau_oclass *oclass, void *data, u32 size, 409 struct nouveau_oclass *oclass, void *data, u32 size,
411 struct nouveau_object **pobject) 410 struct nouveau_object **pobject)
412{ 411{
413 struct nv50_display_mast_class *args = data; 412 union {
413 struct nv50_disp_core_channel_dma_v0 v0;
414 } *args = data;
414 struct nv50_disp_dmac *mast; 415 struct nv50_disp_dmac *mast;
415 int ret; 416 int ret;
416 417
417 if (size < sizeof(*args)) 418 nv_ioctl(parent, "create disp core channel dma size %d\n", size);
418 return -EINVAL; 419 if (nvif_unpack(args->v0, 0, 0, false)) {
420 nv_ioctl(parent, "create disp core channel dma vers %d "
421 "pushbuf %08x\n",
422 args->v0.version, args->v0.pushbuf);
423 } else
424 return ret;
419 425
420 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, 426 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
421 0, sizeof(*mast), (void **)&mast); 427 0, sizeof(*mast), (void **)&mast);
422 *pobject = nv_object(mast); 428 *pobject = nv_object(mast);
423 if (ret) 429 if (ret)
@@ -557,16 +563,26 @@ nv50_disp_sync_ctor(struct nouveau_object *parent,
557 struct nouveau_oclass *oclass, void *data, u32 size, 563 struct nouveau_oclass *oclass, void *data, u32 size,
558 struct nouveau_object **pobject) 564 struct nouveau_object **pobject)
559{ 565{
560 struct nv50_display_sync_class *args = data; 566 union {
567 struct nv50_disp_base_channel_dma_v0 v0;
568 } *args = data;
561 struct nv50_disp_priv *priv = (void *)engine; 569 struct nv50_disp_priv *priv = (void *)engine;
562 struct nv50_disp_dmac *dmac; 570 struct nv50_disp_dmac *dmac;
563 int ret; 571 int ret;
564 572
565 if (size < sizeof(*args) || args->head >= priv->head.nr) 573 nv_ioctl(parent, "create disp base channel dma size %d\n", size);
566 return -EINVAL; 574 if (nvif_unpack(args->v0, 0, 0, false)) {
575 nv_ioctl(parent, "create disp base channel dma vers %d "
576 "pushbuf %08x head %d\n",
577 args->v0.version, args->v0.pushbuf, args->v0.head);
578 if (args->v0.head > priv->head.nr)
579 return -EINVAL;
580 } else
581 return ret;
567 582
568 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, 583 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
569 args->head, sizeof(*dmac), (void **)&dmac); 584 args->v0.head, sizeof(*dmac),
585 (void **)&dmac);
570 *pobject = nv_object(dmac); 586 *pobject = nv_object(dmac);
571 if (ret) 587 if (ret)
572 return ret; 588 return ret;
@@ -635,16 +651,26 @@ nv50_disp_ovly_ctor(struct nouveau_object *parent,
635 struct nouveau_oclass *oclass, void *data, u32 size, 651 struct nouveau_oclass *oclass, void *data, u32 size,
636 struct nouveau_object **pobject) 652 struct nouveau_object **pobject)
637{ 653{
638 struct nv50_display_ovly_class *args = data; 654 union {
655 struct nv50_disp_overlay_channel_dma_v0 v0;
656 } *args = data;
639 struct nv50_disp_priv *priv = (void *)engine; 657 struct nv50_disp_priv *priv = (void *)engine;
640 struct nv50_disp_dmac *dmac; 658 struct nv50_disp_dmac *dmac;
641 int ret; 659 int ret;
642 660
643 if (size < sizeof(*args) || args->head >= priv->head.nr) 661 nv_ioctl(parent, "create disp overlay channel dma size %d\n", size);
644 return -EINVAL; 662 if (nvif_unpack(args->v0, 0, 0, false)) {
663 nv_ioctl(parent, "create disp overlay channel dma vers %d "
664 "pushbuf %08x head %d\n",
665 args->v0.version, args->v0.pushbuf, args->v0.head);
666 if (args->v0.head > priv->head.nr)
667 return -EINVAL;
668 } else
669 return ret;
645 670
646 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->pushbuf, 671 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf,
647 args->head, sizeof(*dmac), (void **)&dmac); 672 args->v0.head, sizeof(*dmac),
673 (void **)&dmac);
648 *pobject = nv_object(dmac); 674 *pobject = nv_object(dmac);
649 if (ret) 675 if (ret)
650 return ret; 676 return ret;
@@ -743,15 +769,23 @@ nv50_disp_oimm_ctor(struct nouveau_object *parent,
743 struct nouveau_oclass *oclass, void *data, u32 size, 769 struct nouveau_oclass *oclass, void *data, u32 size,
744 struct nouveau_object **pobject) 770 struct nouveau_object **pobject)
745{ 771{
746 struct nv50_display_oimm_class *args = data; 772 union {
773 struct nv50_disp_overlay_v0 v0;
774 } *args = data;
747 struct nv50_disp_priv *priv = (void *)engine; 775 struct nv50_disp_priv *priv = (void *)engine;
748 struct nv50_disp_pioc *pioc; 776 struct nv50_disp_pioc *pioc;
749 int ret; 777 int ret;
750 778
751 if (size < sizeof(*args) || args->head >= priv->head.nr) 779 nv_ioctl(parent, "create disp overlay size %d\n", size);
752 return -EINVAL; 780 if (nvif_unpack(args->v0, 0, 0, false)) {
781 nv_ioctl(parent, "create disp overlay vers %d head %d\n",
782 args->v0.version, args->v0.head);
783 if (args->v0.head > priv->head.nr)
784 return -EINVAL;
785 } else
786 return ret;
753 787
754 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head, 788 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
755 sizeof(*pioc), (void **)&pioc); 789 sizeof(*pioc), (void **)&pioc);
756 *pobject = nv_object(pioc); 790 *pobject = nv_object(pioc);
757 if (ret) 791 if (ret)
@@ -781,15 +815,23 @@ nv50_disp_curs_ctor(struct nouveau_object *parent,
781 struct nouveau_oclass *oclass, void *data, u32 size, 815 struct nouveau_oclass *oclass, void *data, u32 size,
782 struct nouveau_object **pobject) 816 struct nouveau_object **pobject)
783{ 817{
784 struct nv50_display_curs_class *args = data; 818 union {
819 struct nv50_disp_cursor_v0 v0;
820 } *args = data;
785 struct nv50_disp_priv *priv = (void *)engine; 821 struct nv50_disp_priv *priv = (void *)engine;
786 struct nv50_disp_pioc *pioc; 822 struct nv50_disp_pioc *pioc;
787 int ret; 823 int ret;
788 824
789 if (size < sizeof(*args) || args->head >= priv->head.nr) 825 nv_ioctl(parent, "create disp cursor size %d\n", size);
790 return -EINVAL; 826 if (nvif_unpack(args->v0, 0, 0, false)) {
827 nv_ioctl(parent, "create disp cursor vers %d head %d\n",
828 args->v0.version, args->v0.head);
829 if (args->v0.head > priv->head.nr)
830 return -EINVAL;
831 } else
832 return ret;
791 833
792 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->head, 834 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head,
793 sizeof(*pioc), (void **)&pioc); 835 sizeof(*pioc), (void **)&pioc);
794 *pobject = nv_object(pioc); 836 *pobject = nv_object(pioc);
795 if (ret) 837 if (ret)
@@ -1089,17 +1131,17 @@ nv50_disp_base_ofuncs = {
1089 1131
1090static struct nouveau_oclass 1132static struct nouveau_oclass
1091nv50_disp_base_oclass[] = { 1133nv50_disp_base_oclass[] = {
1092 { NV50_DISP_CLASS, &nv50_disp_base_ofuncs }, 1134 { NV50_DISP, &nv50_disp_base_ofuncs },
1093 {} 1135 {}
1094}; 1136};
1095 1137
1096static struct nouveau_oclass 1138static struct nouveau_oclass
1097nv50_disp_sclass[] = { 1139nv50_disp_sclass[] = {
1098 { NV50_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base }, 1140 { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
1099 { NV50_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base }, 1141 { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
1100 { NV50_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base }, 1142 { NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
1101 { NV50_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base }, 1143 { NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
1102 { NV50_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base }, 1144 { NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
1103 {} 1145 {}
1104}; 1146};
1105 1147
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
index 81bf80fd8dcd..9be9b45e3c5e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
@@ -188,6 +188,7 @@ int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
188 struct nouveau_oclass *, void *, u32, 188 struct nouveau_oclass *, void *, u32,
189 struct nouveau_object **); 189 struct nouveau_object **);
190void nv50_disp_base_dtor(struct nouveau_object *); 190void nv50_disp_base_dtor(struct nouveau_object *);
191extern struct nouveau_omthds nv50_disp_base_omthds[];
191extern struct nouveau_oclass nv50_disp_cclass; 192extern struct nouveau_oclass nv50_disp_cclass;
192void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, 193void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
193 const struct nv50_disp_mthd_chan *); 194 const struct nv50_disp_mthd_chan *);
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index 8746644d9ded..788ced1b6182 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -204,17 +204,17 @@ nv84_disp_ovly_mthd_chan = {
204 204
205static struct nouveau_oclass 205static struct nouveau_oclass
206nv84_disp_sclass[] = { 206nv84_disp_sclass[] = {
207 { NV84_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base }, 207 { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
208 { NV84_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base }, 208 { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
209 { NV84_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base }, 209 { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
210 { NV84_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base }, 210 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
211 { NV84_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base }, 211 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
212 {} 212 {}
213}; 213};
214 214
215static struct nouveau_oclass 215static struct nouveau_oclass
216nv84_disp_base_oclass[] = { 216nv84_disp_base_oclass[] = {
217 { NV84_DISP_CLASS, &nv50_disp_base_ofuncs }, 217 { G82_DISP, &nv50_disp_base_ofuncs },
218 {} 218 {}
219}; 219};
220 220
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index 11cd16abcee2..fa79de906eae 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -63,17 +63,17 @@ nv94_disp_mast_mthd_chan = {
63 63
64static struct nouveau_oclass 64static struct nouveau_oclass
65nv94_disp_sclass[] = { 65nv94_disp_sclass[] = {
66 { NV94_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base }, 66 { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
67 { NV94_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base }, 67 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
68 { NV94_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base }, 68 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
69 { NV94_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base }, 69 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
70 { NV94_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base }, 70 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
71 {} 71 {}
72}; 72};
73 73
74static struct nouveau_oclass 74static struct nouveau_oclass
75nv94_disp_base_oclass[] = { 75nv94_disp_base_oclass[] = {
76 { NV94_DISP_CLASS, &nv50_disp_base_ofuncs }, 76 { GT206_DISP, &nv50_disp_base_ofuncs },
77 {} 77 {}
78}; 78};
79 79
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
index 381957586f03..7af15f5d48dc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -80,17 +80,17 @@ nva0_disp_ovly_mthd_chan = {
80 80
81static struct nouveau_oclass 81static struct nouveau_oclass
82nva0_disp_sclass[] = { 82nva0_disp_sclass[] = {
83 { NVA0_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base }, 83 { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
84 { NVA0_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base }, 84 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
85 { NVA0_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base }, 85 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
86 { NVA0_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base }, 86 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
87 { NVA0_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base }, 87 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
88 {} 88 {}
89}; 89};
90 90
91static struct nouveau_oclass 91static struct nouveau_oclass
92nva0_disp_base_oclass[] = { 92nva0_disp_base_oclass[] = {
93 { NVA0_DISP_CLASS, &nv50_disp_base_ofuncs }, 93 { GT200_DISP, &nv50_disp_base_ofuncs },
94 {} 94 {}
95}; 95};
96 96
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 25df6b93c93a..6bd39448f8da 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -35,17 +35,17 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37nva3_disp_sclass[] = { 37nva3_disp_sclass[] = {
38 { NVA3_DISP_MAST_CLASS, &nv50_disp_mast_ofuncs.base }, 38 { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
39 { NVA3_DISP_SYNC_CLASS, &nv50_disp_sync_ofuncs.base }, 39 { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
40 { NVA3_DISP_OVLY_CLASS, &nv50_disp_ovly_ofuncs.base }, 40 { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
41 { NVA3_DISP_OIMM_CLASS, &nv50_disp_oimm_ofuncs.base }, 41 { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
42 { NVA3_DISP_CURS_CLASS, &nv50_disp_curs_ofuncs.base }, 42 { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45
46static struct nouveau_oclass 46static struct nouveau_oclass
47nva3_disp_base_oclass[] = { 47nva3_disp_base_oclass[] = {
48 { NVA3_DISP_CLASS, &nv50_disp_base_ofuncs }, 48 { GT214_DISP, &nv50_disp_base_ofuncs },
49 {} 49 {}
50}; 50};
51 51
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index deddd05e7c76..f64647b8b8d0 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -26,7 +26,6 @@
26#include <core/client.h> 26#include <core/client.h>
27#include <core/parent.h> 27#include <core/parent.h>
28#include <core/handle.h> 28#include <core/handle.h>
29#include <core/class.h>
30#include <nvif/unpack.h> 29#include <nvif/unpack.h>
31#include <nvif/class.h> 30#include <nvif/class.h>
32 31
@@ -716,17 +715,17 @@ nvd0_disp_base_ofuncs = {
716 715
717static struct nouveau_oclass 716static struct nouveau_oclass
718nvd0_disp_base_oclass[] = { 717nvd0_disp_base_oclass[] = {
719 { NVD0_DISP_CLASS, &nvd0_disp_base_ofuncs }, 718 { GF110_DISP, &nvd0_disp_base_ofuncs },
720 {} 719 {}
721}; 720};
722 721
723static struct nouveau_oclass 722static struct nouveau_oclass
724nvd0_disp_sclass[] = { 723nvd0_disp_sclass[] = {
725 { NVD0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base }, 724 { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
726 { NVD0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base }, 725 { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
727 { NVD0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base }, 726 { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
728 { NVD0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base }, 727 { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
729 { NVD0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base }, 728 { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
730 {} 729 {}
731}; 730};
732 731
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
index 58b0ac101f16..47fef1e398c4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -200,17 +200,17 @@ nve0_disp_ovly_mthd_chan = {
200 200
201static struct nouveau_oclass 201static struct nouveau_oclass
202nve0_disp_sclass[] = { 202nve0_disp_sclass[] = {
203 { NVE0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base }, 203 { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
204 { NVE0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base }, 204 { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
205 { NVE0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base }, 205 { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
206 { NVE0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base }, 206 { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
207 { NVE0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base }, 207 { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
208 {} 208 {}
209}; 209};
210 210
211static struct nouveau_oclass 211static struct nouveau_oclass
212nve0_disp_base_oclass[] = { 212nve0_disp_base_oclass[] = {
213 { NVE0_DISP_CLASS, &nvd0_disp_base_ofuncs }, 213 { GK104_DISP, &nvd0_disp_base_ofuncs },
214 {} 214 {}
215}; 215};
216 216
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
index b6b01463eb6c..04bda4ac4ed3 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
@@ -25,7 +25,7 @@
25#include <engine/software.h> 25#include <engine/software.h>
26#include <engine/disp.h> 26#include <engine/disp.h>
27 27
28#include <core/class.h> 28#include <nvif/class.h>
29 29
30#include "nv50.h" 30#include "nv50.h"
31 31
@@ -35,17 +35,17 @@
35 35
36static struct nouveau_oclass 36static struct nouveau_oclass
37nvf0_disp_sclass[] = { 37nvf0_disp_sclass[] = {
38 { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs.base }, 38 { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
39 { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs.base }, 39 { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
40 { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs.base }, 40 { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
41 { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs.base }, 41 { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
42 { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs.base }, 42 { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
43 {} 43 {}
44}; 44};
45 45
46static struct nouveau_oclass 46static struct nouveau_oclass
47nvf0_disp_base_oclass[] = { 47nvf0_disp_base_oclass[] = {
48 { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs }, 48 { GK110_DISP, &nvd0_disp_base_ofuncs },
49 {} 49 {}
50}; 50};
51 51
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 7b32821f3622..ddf1760c4400 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/class.h>
27#include <nvif/unpack.h> 26#include <nvif/unpack.h>
28#include <nvif/class.h> 27#include <nvif/class.h>
29 28
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
index 05487cda84a8..39f85d627336 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27 26
28#include <subdev/bios.h> 27#include <subdev/bios.h>
29#include <subdev/bios/dcb.h> 28#include <subdev/bios/dcb.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
index 97f0e9cd3d40..7b7bbc3e459e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27 26
28#include <subdev/bios.h> 27#include <subdev/bios.h>
29#include <subdev/bios/dcb.h> 28#include <subdev/bios/dcb.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
index 3e14f46cfbd2..20c9dbfe3b2e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/gpuobj.h> 25#include <core/gpuobj.h>
26#include <core/class.h>
27#include <nvif/class.h> 26#include <nvif/class.h>
28 27
29#include <subdev/fb.h> 28#include <subdev/fb.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
index 7495f7d363bb..a740ddba2ee2 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c
@@ -24,7 +24,6 @@
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/gpuobj.h> 26#include <core/gpuobj.h>
27#include <core/class.h>
28#include <nvif/unpack.h> 27#include <nvif/unpack.h>
29#include <nvif/class.h> 28#include <nvif/class.h>
30 29
@@ -51,21 +50,19 @@ nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
51 case NV40_CHANNEL_DMA: 50 case NV40_CHANNEL_DMA:
52 case NV50_CHANNEL_GPFIFO: 51 case NV50_CHANNEL_GPFIFO:
53 case G82_CHANNEL_GPFIFO: 52 case G82_CHANNEL_GPFIFO:
54 case NV50_DISP_MAST_CLASS: 53 case NV50_DISP_CORE_CHANNEL_DMA:
55 case NV84_DISP_MAST_CLASS: 54 case G82_DISP_CORE_CHANNEL_DMA:
56 case NV94_DISP_MAST_CLASS: 55 case GT206_DISP_CORE_CHANNEL_DMA:
57 case NVA0_DISP_MAST_CLASS: 56 case GT200_DISP_CORE_CHANNEL_DMA:
58 case NVA3_DISP_MAST_CLASS: 57 case GT214_DISP_CORE_CHANNEL_DMA:
59 case NV50_DISP_SYNC_CLASS: 58 case NV50_DISP_BASE_CHANNEL_DMA:
60 case NV84_DISP_SYNC_CLASS: 59 case G82_DISP_BASE_CHANNEL_DMA:
61 case NV94_DISP_SYNC_CLASS: 60 case GT200_DISP_BASE_CHANNEL_DMA:
62 case NVA0_DISP_SYNC_CLASS: 61 case GT214_DISP_BASE_CHANNEL_DMA:
63 case NVA3_DISP_SYNC_CLASS: 62 case NV50_DISP_OVERLAY_CHANNEL_DMA:
64 case NV50_DISP_OVLY_CLASS: 63 case G82_DISP_OVERLAY_CHANNEL_DMA:
65 case NV84_DISP_OVLY_CLASS: 64 case GT200_DISP_OVERLAY_CHANNEL_DMA:
66 case NV94_DISP_OVLY_CLASS: 65 case GT214_DISP_OVERLAY_CHANNEL_DMA:
67 case NVA0_DISP_OVLY_CLASS:
68 case NVA3_DISP_OVLY_CLASS:
69 break; 66 break;
70 default: 67 default:
71 return -EINVAL; 68 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
index ef8031e082c2..88ec33b20048 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c
@@ -25,7 +25,6 @@
25#include <core/client.h> 25#include <core/client.h>
26#include <core/device.h> 26#include <core/device.h>
27#include <core/gpuobj.h> 27#include <core/gpuobj.h>
28#include <core/class.h>
29#include <nvif/unpack.h> 28#include <nvif/unpack.h>
30#include <nvif/class.h> 29#include <nvif/class.h>
31 30
@@ -49,9 +48,9 @@ nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
49 48
50 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { 49 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
51 switch (nv_mclass(parent->parent)) { 50 switch (nv_mclass(parent->parent)) {
52 case NVA3_DISP_MAST_CLASS: 51 case GT214_DISP_CORE_CHANNEL_DMA:
53 case NVA3_DISP_SYNC_CLASS: 52 case GT214_DISP_BASE_CHANNEL_DMA:
54 case NVA3_DISP_OVLY_CLASS: 53 case GT214_DISP_OVERLAY_CHANNEL_DMA:
55 break; 54 break;
56 default: 55 default:
57 return -EINVAL; 56 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
index d07ed0daa14d..3fc4f0b0eaca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c
@@ -25,7 +25,6 @@
25#include <core/client.h> 25#include <core/client.h>
26#include <core/device.h> 26#include <core/device.h>
27#include <core/gpuobj.h> 27#include <core/gpuobj.h>
28#include <core/class.h>
29#include <nvif/unpack.h> 28#include <nvif/unpack.h>
30#include <nvif/class.h> 29#include <nvif/class.h>
31 30
@@ -48,18 +47,15 @@ nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj,
48 47
49 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { 48 if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {
50 switch (nv_mclass(parent->parent)) { 49 switch (nv_mclass(parent->parent)) {
51 case NVD0_DISP_MAST_CLASS: 50 case GF110_DISP_CORE_CHANNEL_DMA:
52 case NVD0_DISP_SYNC_CLASS: 51 case GK104_DISP_CORE_CHANNEL_DMA:
53 case NVD0_DISP_OVLY_CLASS: 52 case GK110_DISP_CORE_CHANNEL_DMA:
54 case NVE0_DISP_MAST_CLASS: 53 case GM107_DISP_CORE_CHANNEL_DMA:
55 case NVE0_DISP_SYNC_CLASS: 54 case GF110_DISP_BASE_CHANNEL_DMA:
56 case NVE0_DISP_OVLY_CLASS: 55 case GK104_DISP_BASE_CHANNEL_DMA:
57 case NVF0_DISP_MAST_CLASS: 56 case GK110_DISP_BASE_CHANNEL_DMA:
58 case NVF0_DISP_SYNC_CLASS: 57 case GF110_DISP_OVERLAY_CONTROL_DMA:
59 case NVF0_DISP_OVLY_CLASS: 58 case GK104_DISP_OVERLAY_CONTROL_DMA:
60 case GM107_DISP_MAST_CLASS:
61 case GM107_DISP_SYNC_CLASS:
62 case GM107_DISP_OVLY_CLASS:
63 break; 59 break;
64 default: 60 default:
65 return -EINVAL; 61 return -EINVAL;
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
index ad13dcdd15f9..f70e2f67a4dd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
@@ -24,7 +24,6 @@
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/class.h>
28#include <core/handle.h> 27#include <core/handle.h>
29#include <core/namedb.h> 28#include <core/namedb.h>
30 29
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
index 4532f7e5618c..2b12b09683c8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
@@ -24,7 +24,6 @@
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/class.h>
28#include <core/handle.h> 27#include <core/handle.h>
29 28
30#include <subdev/fb.h> 29#include <subdev/fb.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
index d145e080899a..ceb9c746d94e 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
@@ -1,6 +1,5 @@
1#include <core/client.h> 1#include <core/client.h>
2#include <core/os.h> 2#include <core/os.h>
3#include <core/class.h>
4#include <core/engctx.h> 3#include <core/engctx.h>
5#include <core/handle.h> 4#include <core/handle.h>
6#include <core/enum.h> 5#include <core/enum.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
index 7a80d005a974..f8a6fdd7d5e8 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c
@@ -1,5 +1,4 @@
1#include <core/os.h> 1#include <core/os.h>
2#include <core/class.h>
3#include <core/engctx.h> 2#include <core/engctx.h>
4#include <core/enum.h> 3#include <core/enum.h>
5 4
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
index 3e1f32ee43d4..5de9caa2ef67 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c
@@ -1,5 +1,4 @@
1#include <core/os.h> 1#include <core/os.h>
2#include <core/class.h>
3#include <core/engctx.h> 2#include <core/engctx.h>
4#include <core/enum.h> 3#include <core/enum.h>
5 4
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
index e451db32e92a..2f9dbc709389 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c
@@ -1,5 +1,4 @@
1#include <core/os.h> 1#include <core/os.h>
2#include <core/class.h>
3#include <core/engctx.h> 2#include <core/engctx.h>
4#include <core/enum.h> 3#include <core/enum.h>
5 4
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
index 9385ac7b44a4..34dd26c70b64 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c
@@ -1,5 +1,4 @@
1#include <core/os.h> 1#include <core/os.h>
2#include <core/class.h>
3#include <core/engctx.h> 2#include <core/engctx.h>
4#include <core/enum.h> 3#include <core/enum.h>
5 4
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
index 9ce84b73f86a..2fb5756d9f66 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c
@@ -1,5 +1,4 @@
1#include <core/os.h> 1#include <core/os.h>
2#include <core/class.h>
3#include <core/engctx.h> 2#include <core/engctx.h>
4#include <core/enum.h> 3#include <core/enum.h>
5 4
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
index 6477fbf6a550..4f401174868d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
@@ -24,7 +24,6 @@
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/class.h>
28#include <core/handle.h> 27#include <core/handle.h>
29#include <core/engctx.h> 28#include <core/engctx.h>
30 29
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
index 20665c21d80e..38e0aa26f1cd 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/client.h> 26#include <core/client.h>
28#include <core/handle.h> 27#include <core/handle.h>
29#include <core/engctx.h> 28#include <core/engctx.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
index 7eb6d94c84e2..d88c700b2f69 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
@@ -24,7 +24,6 @@
24 24
25#include <core/client.h> 25#include <core/client.h>
26#include <core/os.h> 26#include <core/os.h>
27#include <core/class.h>
28#include <core/engctx.h> 27#include <core/engctx.h>
29#include <core/handle.h> 28#include <core/handle.h>
30 29
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
index d4e7ec0ba68c..bdb2f20ff7b1 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28 27
29#include <subdev/fb.h> 28#include <subdev/fb.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
index 3d8c2133e0e8..72c7f33fd29b 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/client.h> 26#include <core/client.h>
28#include <core/engctx.h> 27#include <core/engctx.h>
29#include <core/handle.h> 28#include <core/handle.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
index 37a2bd9e8078..cae33f86b11a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28 27
29#include <subdev/vm.h> 28#include <subdev/vm.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
index 96f5aa92677b..e9cc8b116a24 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28 27
29#include <subdev/vm.h> 28#include <subdev/vm.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
index c571758e4a27..64df15c7f051 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28 27
29#include <engine/software.h> 28#include <engine/software.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
index a62f11a78430..f54a2253deca 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28 27
29#include <engine/software.h> 28#include <engine/software.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
index 48678ed41ba4..4d2994d8cc32 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28#include <core/namedb.h> 27#include <core/namedb.h>
29#include <core/handle.h> 28#include <core/handle.h>
diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
index df299a91cf70..6af370d3a06d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
@@ -23,7 +23,6 @@
23 */ 23 */
24 24
25#include <core/os.h> 25#include <core/os.h>
26#include <core/class.h>
27#include <core/engctx.h> 26#include <core/engctx.h>
28#include <core/event.h> 27#include <core/event.h>
29 28
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
deleted file mode 100644
index 24b85a9ac657..000000000000
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ /dev/null
@@ -1,165 +0,0 @@
1#ifndef __NOUVEAU_CLASS_H__
2#define __NOUVEAU_CLASS_H__
3
4#include <nvif/class.h>
5
6/* 0046: NV04_DISP
7 */
8
9#define NV04_DISP_CLASS 0x00000046
10
11struct nv04_display_class {
12};
13
14/* 5070: NV50_DISP
15 * 8270: NV84_DISP
16 * 8370: NVA0_DISP
17 * 8870: NV94_DISP
18 * 8570: NVA3_DISP
19 * 9070: NVD0_DISP
20 * 9170: NVE0_DISP
21 * 9270: NVF0_DISP
22 * 9470: GM107_DISP
23 */
24
25#define NV50_DISP_CLASS 0x00005070
26#define NV84_DISP_CLASS 0x00008270
27#define NVA0_DISP_CLASS 0x00008370
28#define NV94_DISP_CLASS 0x00008870
29#define NVA3_DISP_CLASS 0x00008570
30#define NVD0_DISP_CLASS 0x00009070
31#define NVE0_DISP_CLASS 0x00009170
32#define NVF0_DISP_CLASS 0x00009270
33#define GM107_DISP_CLASS 0x00009470
34
35struct nv50_display_class {
36};
37
38/* 507a: NV50_DISP_CURS
39 * 827a: NV84_DISP_CURS
40 * 837a: NVA0_DISP_CURS
41 * 887a: NV94_DISP_CURS
42 * 857a: NVA3_DISP_CURS
43 * 907a: NVD0_DISP_CURS
44 * 917a: NVE0_DISP_CURS
45 * 927a: NVF0_DISP_CURS
46 * 947a: GM107_DISP_CURS
47 */
48
49#define NV50_DISP_CURS_CLASS 0x0000507a
50#define NV84_DISP_CURS_CLASS 0x0000827a
51#define NVA0_DISP_CURS_CLASS 0x0000837a
52#define NV94_DISP_CURS_CLASS 0x0000887a
53#define NVA3_DISP_CURS_CLASS 0x0000857a
54#define NVD0_DISP_CURS_CLASS 0x0000907a
55#define NVE0_DISP_CURS_CLASS 0x0000917a
56#define NVF0_DISP_CURS_CLASS 0x0000927a
57#define GM107_DISP_CURS_CLASS 0x0000947a
58
59struct nv50_display_curs_class {
60 u32 head;
61};
62
63/* 507b: NV50_DISP_OIMM
64 * 827b: NV84_DISP_OIMM
65 * 837b: NVA0_DISP_OIMM
66 * 887b: NV94_DISP_OIMM
67 * 857b: NVA3_DISP_OIMM
68 * 907b: NVD0_DISP_OIMM
69 * 917b: NVE0_DISP_OIMM
70 * 927b: NVE0_DISP_OIMM
71 * 947b: GM107_DISP_OIMM
72 */
73
74#define NV50_DISP_OIMM_CLASS 0x0000507b
75#define NV84_DISP_OIMM_CLASS 0x0000827b
76#define NVA0_DISP_OIMM_CLASS 0x0000837b
77#define NV94_DISP_OIMM_CLASS 0x0000887b
78#define NVA3_DISP_OIMM_CLASS 0x0000857b
79#define NVD0_DISP_OIMM_CLASS 0x0000907b
80#define NVE0_DISP_OIMM_CLASS 0x0000917b
81#define NVF0_DISP_OIMM_CLASS 0x0000927b
82#define GM107_DISP_OIMM_CLASS 0x0000947b
83
84struct nv50_display_oimm_class {
85 u32 head;
86};
87
88/* 507c: NV50_DISP_SYNC
89 * 827c: NV84_DISP_SYNC
90 * 837c: NVA0_DISP_SYNC
91 * 887c: NV94_DISP_SYNC
92 * 857c: NVA3_DISP_SYNC
93 * 907c: NVD0_DISP_SYNC
94 * 917c: NVE0_DISP_SYNC
95 * 927c: NVF0_DISP_SYNC
96 * 947c: GM107_DISP_SYNC
97 */
98
99#define NV50_DISP_SYNC_CLASS 0x0000507c
100#define NV84_DISP_SYNC_CLASS 0x0000827c
101#define NVA0_DISP_SYNC_CLASS 0x0000837c
102#define NV94_DISP_SYNC_CLASS 0x0000887c
103#define NVA3_DISP_SYNC_CLASS 0x0000857c
104#define NVD0_DISP_SYNC_CLASS 0x0000907c
105#define NVE0_DISP_SYNC_CLASS 0x0000917c
106#define NVF0_DISP_SYNC_CLASS 0x0000927c
107#define GM107_DISP_SYNC_CLASS 0x0000947c
108
109struct nv50_display_sync_class {
110 u32 pushbuf;
111 u32 head;
112};
113
114/* 507d: NV50_DISP_MAST
115 * 827d: NV84_DISP_MAST
116 * 837d: NVA0_DISP_MAST
117 * 887d: NV94_DISP_MAST
118 * 857d: NVA3_DISP_MAST
119 * 907d: NVD0_DISP_MAST
120 * 917d: NVE0_DISP_MAST
121 * 927d: NVF0_DISP_MAST
122 * 947d: GM107_DISP_MAST
123 */
124
125#define NV50_DISP_MAST_CLASS 0x0000507d
126#define NV84_DISP_MAST_CLASS 0x0000827d
127#define NVA0_DISP_MAST_CLASS 0x0000837d
128#define NV94_DISP_MAST_CLASS 0x0000887d
129#define NVA3_DISP_MAST_CLASS 0x0000857d
130#define NVD0_DISP_MAST_CLASS 0x0000907d
131#define NVE0_DISP_MAST_CLASS 0x0000917d
132#define NVF0_DISP_MAST_CLASS 0x0000927d
133#define GM107_DISP_MAST_CLASS 0x0000947d
134
135struct nv50_display_mast_class {
136 u32 pushbuf;
137};
138
139/* 507e: NV50_DISP_OVLY
140 * 827e: NV84_DISP_OVLY
141 * 837e: NVA0_DISP_OVLY
142 * 887e: NV94_DISP_OVLY
143 * 857e: NVA3_DISP_OVLY
144 * 907e: NVD0_DISP_OVLY
145 * 917e: NVE0_DISP_OVLY
146 * 927e: NVF0_DISP_OVLY
147 * 947e: GM107_DISP_OVLY
148 */
149
150#define NV50_DISP_OVLY_CLASS 0x0000507e
151#define NV84_DISP_OVLY_CLASS 0x0000827e
152#define NVA0_DISP_OVLY_CLASS 0x0000837e
153#define NV94_DISP_OVLY_CLASS 0x0000887e
154#define NVA3_DISP_OVLY_CLASS 0x0000857e
155#define NVD0_DISP_OVLY_CLASS 0x0000907e
156#define NVE0_DISP_OVLY_CLASS 0x0000917e
157#define NVF0_DISP_OVLY_CLASS 0x0000927e
158#define GM107_DISP_OVLY_CLASS 0x0000947e
159
160struct nv50_display_ovly_class {
161 u32 pushbuf;
162 u32 head;
163};
164
165#endif
diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
index 49b0024910fe..88cc812baaa3 100644
--- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
+++ b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h
@@ -4,7 +4,6 @@
4#include <core/device.h> 4#include <core/device.h>
5#include <core/engine.h> 5#include <core/engine.h>
6#include <core/engctx.h> 6#include <core/engctx.h>
7#include <core/class.h>
8 7
9struct nouveau_perfdom; 8struct nouveau_perfdom;
10struct nouveau_perfctr; 9struct nouveau_perfctr;
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index f00e56c79ac4..a5a1f298c001 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -404,10 +404,10 @@ nouveau_display_create_properties(struct drm_device *dev)
404 struct nouveau_display *disp = nouveau_display(dev); 404 struct nouveau_display *disp = nouveau_display(dev);
405 int gen; 405 int gen;
406 406
407 if (disp->disp.oclass < NV50_DISP_CLASS) 407 if (disp->disp.oclass < NV50_DISP)
408 gen = 0; 408 gen = 0;
409 else 409 else
410 if (disp->disp.oclass < NVD0_DISP_CLASS) 410 if (disp->disp.oclass < GF110_DISP)
411 gen = 1; 411 gen = 1;
412 else 412 else
413 gen = 2; 413 gen = 2;
@@ -479,16 +479,16 @@ nouveau_display_create(struct drm_device *dev)
479 479
480 if (drm->vbios.dcb.entries) { 480 if (drm->vbios.dcb.entries) {
481 static const u16 oclass[] = { 481 static const u16 oclass[] = {
482 GM107_DISP_CLASS, 482 GM107_DISP,
483 NVF0_DISP_CLASS, 483 GK110_DISP,
484 NVE0_DISP_CLASS, 484 GK104_DISP,
485 NVD0_DISP_CLASS, 485 GF110_DISP,
486 NVA3_DISP_CLASS, 486 GT214_DISP,
487 NV94_DISP_CLASS, 487 GT206_DISP,
488 NVA0_DISP_CLASS, 488 GT200_DISP,
489 NV84_DISP_CLASS, 489 G82_DISP,
490 NV50_DISP_CLASS, 490 NV50_DISP,
491 NV04_DISP_CLASS, 491 NV04_DISP,
492 }; 492 };
493 int i; 493 int i;
494 494
@@ -500,7 +500,7 @@ nouveau_display_create(struct drm_device *dev)
500 500
501 if (ret == 0) { 501 if (ret == 0) {
502 nouveau_display_create_properties(dev); 502 nouveau_display_create_properties(dev);
503 if (disp->disp.oclass < NV50_DISP_CLASS) 503 if (disp->disp.oclass < NV50_DISP)
504 ret = nv04_display_create(dev); 504 ret = nv04_display_create(dev);
505 else 505 else
506 ret = nv50_display_create(dev); 506 ret = nv50_display_create(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index f11b65195337..12b5ba3d4fdc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -33,7 +33,6 @@
33 33
34#include <core/device.h> 34#include <core/device.h>
35#include <core/gpuobj.h> 35#include <core/gpuobj.h>
36#include <core/class.h>
37#include <core/option.h> 36#include <core/option.h>
38 37
39#include "nouveau_drm.h" 38#include "nouveau_drm.h"
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h
index 5479013e13f4..3a6ef5018f52 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.h
@@ -28,8 +28,6 @@
28#include <nvif/client.h> 28#include <nvif/client.h>
29#include <nvif/device.h> 29#include <nvif/device.h>
30 30
31#include <core/class.h>
32
33#include <drmP.h> 31#include <drmP.h>
34 32
35#include <drm/ttm/ttm_bo_api.h> 33#include <drm/ttm/ttm_bo_api.h>
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index bd85026ee067..82d6b4f6a5c2 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -53,12 +53,6 @@
53#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) 53#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
54#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) 54#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
55 55
56#define EVO_CORE_HANDLE (0xd1500000)
57#define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
58#define EVO_CHAN_OCLASS(t,c) (((c)->oclass & 0xff00) | ((t) & 0x00ff))
59#define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \
60 (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
61
62/****************************************************************************** 56/******************************************************************************
63 * EVO channel 57 * EVO channel
64 *****************************************************************************/ 58 *****************************************************************************/
@@ -119,19 +113,15 @@ struct nv50_curs {
119static int 113static int
120nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs) 114nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
121{ 115{
122 struct nv50_display_curs_class args = { 116 struct nv50_disp_cursor_v0 args = {
123 .head = head, 117 .head = head,
124 }; 118 };
125 static const u32 oclass[] = { 119 static const u32 oclass[] = {
126 GM107_DISP_CURS_CLASS, 120 GK104_DISP_CURSOR,
127 NVF0_DISP_CURS_CLASS, 121 GF110_DISP_CURSOR,
128 NVE0_DISP_CURS_CLASS, 122 GT214_DISP_CURSOR,
129 NVD0_DISP_CURS_CLASS, 123 G82_DISP_CURSOR,
130 NVA3_DISP_CURS_CLASS, 124 NV50_DISP_CURSOR,
131 NV94_DISP_CURS_CLASS,
132 NVA0_DISP_CURS_CLASS,
133 NV84_DISP_CURS_CLASS,
134 NV50_DISP_CURS_CLASS,
135 0 125 0
136 }; 126 };
137 127
@@ -150,19 +140,15 @@ struct nv50_oimm {
150static int 140static int
151nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm) 141nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
152{ 142{
153 struct nv50_display_oimm_class args = { 143 struct nv50_disp_cursor_v0 args = {
154 .head = head, 144 .head = head,
155 }; 145 };
156 static const u32 oclass[] = { 146 static const u32 oclass[] = {
157 GM107_DISP_OIMM_CLASS, 147 GK104_DISP_OVERLAY,
158 NVF0_DISP_OIMM_CLASS, 148 GF110_DISP_OVERLAY,
159 NVE0_DISP_OIMM_CLASS, 149 GT214_DISP_OVERLAY,
160 NVD0_DISP_OIMM_CLASS, 150 G82_DISP_OVERLAY,
161 NVA3_DISP_OIMM_CLASS, 151 NV50_DISP_OVERLAY,
162 NV94_DISP_OIMM_CLASS,
163 NVA0_DISP_OIMM_CLASS,
164 NV84_DISP_OIMM_CLASS,
165 NV50_DISP_OIMM_CLASS,
166 0 152 0
167 }; 153 };
168 154
@@ -208,8 +194,8 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
208 struct nv50_dmac *dmac) 194 struct nv50_dmac *dmac)
209{ 195{
210 struct nouveau_fb *pfb = nvkm_fb(nvif_device(disp)); 196 struct nouveau_fb *pfb = nvkm_fb(nvif_device(disp));
197 struct nv50_disp_core_channel_dma_v0 *args = data;
211 struct nvif_object pushbuf; 198 struct nvif_object pushbuf;
212 u32 handle = *(u32 *)data;
213 int ret; 199 int ret;
214 200
215 mutex_init(&dmac->lock); 201 mutex_init(&dmac->lock);
@@ -219,8 +205,8 @@ nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
219 if (!dmac->ptr) 205 if (!dmac->ptr)
220 return -ENOMEM; 206 return -ENOMEM;
221 207
222 ret = nvif_object_init(nvif_object(nvif_device(disp)), NULL, handle, 208 ret = nvif_object_init(nvif_object(nvif_device(disp)), NULL,
223 NV_DMA_FROM_MEMORY, 209 args->pushbuf, NV_DMA_FROM_MEMORY,
224 &(struct nv_dma_v0) { 210 &(struct nv_dma_v0) {
225 .target = NV_DMA_V0_TARGET_PCI_US, 211 .target = NV_DMA_V0_TARGET_PCI_US,
226 .access = NV_DMA_V0_ACCESS_RD, 212 .access = NV_DMA_V0_ACCESS_RD,
@@ -273,19 +259,19 @@ struct nv50_mast {
273static int 259static int
274nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core) 260nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
275{ 261{
276 struct nv50_display_mast_class args = { 262 struct nv50_disp_core_channel_dma_v0 args = {
277 .pushbuf = EVO_PUSH_HANDLE(MAST, 0), 263 .pushbuf = 0xb0007d00,
278 }; 264 };
279 static const u32 oclass[] = { 265 static const u32 oclass[] = {
280 GM107_DISP_MAST_CLASS, 266 GM107_DISP_CORE_CHANNEL_DMA,
281 NVF0_DISP_MAST_CLASS, 267 GK110_DISP_CORE_CHANNEL_DMA,
282 NVE0_DISP_MAST_CLASS, 268 GK104_DISP_CORE_CHANNEL_DMA,
283 NVD0_DISP_MAST_CLASS, 269 GF110_DISP_CORE_CHANNEL_DMA,
284 NVA3_DISP_MAST_CLASS, 270 GT214_DISP_CORE_CHANNEL_DMA,
285 NV94_DISP_MAST_CLASS, 271 GT206_DISP_CORE_CHANNEL_DMA,
286 NVA0_DISP_MAST_CLASS, 272 GT200_DISP_CORE_CHANNEL_DMA,
287 NV84_DISP_MAST_CLASS, 273 G82_DISP_CORE_CHANNEL_DMA,
288 NV50_DISP_MAST_CLASS, 274 NV50_DISP_CORE_CHANNEL_DMA,
289 0 275 0
290 }; 276 };
291 277
@@ -307,20 +293,18 @@ static int
307nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf, 293nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
308 struct nv50_sync *base) 294 struct nv50_sync *base)
309{ 295{
310 struct nv50_display_sync_class args = { 296 struct nv50_disp_base_channel_dma_v0 args = {
311 .pushbuf = EVO_PUSH_HANDLE(SYNC, head), 297 .pushbuf = 0xb0007c00 | head,
312 .head = head, 298 .head = head,
313 }; 299 };
314 static const u32 oclass[] = { 300 static const u32 oclass[] = {
315 GM107_DISP_SYNC_CLASS, 301 GK110_DISP_BASE_CHANNEL_DMA,
316 NVF0_DISP_SYNC_CLASS, 302 GK104_DISP_BASE_CHANNEL_DMA,
317 NVE0_DISP_SYNC_CLASS, 303 GF110_DISP_BASE_CHANNEL_DMA,
318 NVD0_DISP_SYNC_CLASS, 304 GT214_DISP_BASE_CHANNEL_DMA,
319 NVA3_DISP_SYNC_CLASS, 305 GT200_DISP_BASE_CHANNEL_DMA,
320 NV94_DISP_SYNC_CLASS, 306 G82_DISP_BASE_CHANNEL_DMA,
321 NVA0_DISP_SYNC_CLASS, 307 NV50_DISP_BASE_CHANNEL_DMA,
322 NV84_DISP_SYNC_CLASS,
323 NV50_DISP_SYNC_CLASS,
324 0 308 0
325 }; 309 };
326 310
@@ -340,20 +324,17 @@ static int
340nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf, 324nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
341 struct nv50_ovly *ovly) 325 struct nv50_ovly *ovly)
342{ 326{
343 struct nv50_display_ovly_class args = { 327 struct nv50_disp_overlay_channel_dma_v0 args = {
344 .pushbuf = EVO_PUSH_HANDLE(OVLY, head), 328 .pushbuf = 0xb0007e00 | head,
345 .head = head, 329 .head = head,
346 }; 330 };
347 static const u32 oclass[] = { 331 static const u32 oclass[] = {
348 GM107_DISP_OVLY_CLASS, 332 GK104_DISP_OVERLAY_CONTROL_DMA,
349 NVF0_DISP_OVLY_CLASS, 333 GF110_DISP_OVERLAY_CONTROL_DMA,
350 NVE0_DISP_OVLY_CLASS, 334 GT214_DISP_OVERLAY_CHANNEL_DMA,
351 NVD0_DISP_OVLY_CLASS, 335 GT200_DISP_OVERLAY_CHANNEL_DMA,
352 NVA3_DISP_OVLY_CLASS, 336 G82_DISP_OVERLAY_CHANNEL_DMA,
353 NV94_DISP_OVLY_CLASS, 337 NV50_DISP_OVERLAY_CHANNEL_DMA,
354 NVA0_DISP_OVLY_CLASS,
355 NV84_DISP_OVLY_CLASS,
356 NV50_DISP_OVLY_CLASS,
357 0 338 0
358 }; 339 };
359 340
@@ -628,7 +609,7 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
628 evo_mthd(push, 0x0110, 2); 609 evo_mthd(push, 0x0110, 2);
629 evo_data(push, 0x00000000); 610 evo_data(push, 0x00000000);
630 evo_data(push, 0x00000000); 611 evo_data(push, 0x00000000);
631 if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) { 612 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
632 evo_mthd(push, 0x0800, 5); 613 evo_mthd(push, 0x0800, 5);
633 evo_data(push, nv_fb->nvbo->bo.offset >> 8); 614 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
634 evo_data(push, 0); 615 evo_data(push, 0);
@@ -680,11 +661,11 @@ nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
680 661
681 push = evo_wait(mast, 4); 662 push = evo_wait(mast, 4);
682 if (push) { 663 if (push) {
683 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 664 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
684 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); 665 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
685 evo_data(push, mode); 666 evo_data(push, mode);
686 } else 667 } else
687 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) { 668 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
688 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); 669 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
689 evo_data(push, mode); 670 evo_data(push, mode);
690 } else { 671 } else {
@@ -775,7 +756,7 @@ nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
775 756
776 push = evo_wait(mast, 8); 757 push = evo_wait(mast, 8);
777 if (push) { 758 if (push) {
778 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 759 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
779 /*XXX: SCALE_CTRL_ACTIVE??? */ 760 /*XXX: SCALE_CTRL_ACTIVE??? */
780 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); 761 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
781 evo_data(push, (oY << 16) | oX); 762 evo_data(push, (oY << 16) | oX);
@@ -820,7 +801,7 @@ nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
820 801
821 push = evo_wait(mast, 16); 802 push = evo_wait(mast, 16);
822 if (push) { 803 if (push) {
823 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 804 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
824 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); 805 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
825 evo_data(push, (hue << 20) | (vib << 8)); 806 evo_data(push, (hue << 20) | (vib << 8));
826 } else { 807 } else {
@@ -848,7 +829,7 @@ nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
848 829
849 push = evo_wait(mast, 16); 830 push = evo_wait(mast, 16);
850 if (push) { 831 if (push) {
851 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 832 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
852 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); 833 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
853 evo_data(push, nvfb->nvbo->bo.offset >> 8); 834 evo_data(push, nvfb->nvbo->bo.offset >> 8);
854 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); 835 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
@@ -857,7 +838,7 @@ nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
857 evo_data(push, nvfb->r_format); 838 evo_data(push, nvfb->r_format);
858 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); 839 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
859 evo_data(push, (y << 16) | x); 840 evo_data(push, (y << 16) | x);
860 if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) { 841 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
861 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); 842 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
862 evo_data(push, nvfb->r_handle); 843 evo_data(push, nvfb->r_handle);
863 } 844 }
@@ -890,12 +871,12 @@ nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
890 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); 871 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
891 u32 *push = evo_wait(mast, 16); 872 u32 *push = evo_wait(mast, 16);
892 if (push) { 873 if (push) {
893 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { 874 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
894 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); 875 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
895 evo_data(push, 0x85000000); 876 evo_data(push, 0x85000000);
896 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); 877 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
897 } else 878 } else
898 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 879 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
899 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); 880 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
900 evo_data(push, 0x85000000); 881 evo_data(push, 0x85000000);
901 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); 882 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
@@ -918,11 +899,11 @@ nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
918 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); 899 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
919 u32 *push = evo_wait(mast, 16); 900 u32 *push = evo_wait(mast, 16);
920 if (push) { 901 if (push) {
921 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { 902 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
922 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); 903 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
923 evo_data(push, 0x05000000); 904 evo_data(push, 0x05000000);
924 } else 905 } else
925 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 906 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
926 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); 907 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
927 evo_data(push, 0x05000000); 908 evo_data(push, 0x05000000);
928 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); 909 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
@@ -973,13 +954,13 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
973 954
974 push = evo_wait(mast, 6); 955 push = evo_wait(mast, 6);
975 if (push) { 956 if (push) {
976 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { 957 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
977 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); 958 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
978 evo_data(push, 0x00000000); 959 evo_data(push, 0x00000000);
979 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); 960 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
980 evo_data(push, 0x40000000); 961 evo_data(push, 0x40000000);
981 } else 962 } else
982 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 963 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
983 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); 964 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
984 evo_data(push, 0x00000000); 965 evo_data(push, 0x00000000);
985 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); 966 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
@@ -1010,14 +991,14 @@ nv50_crtc_commit(struct drm_crtc *crtc)
1010 991
1011 push = evo_wait(mast, 32); 992 push = evo_wait(mast, 32);
1012 if (push) { 993 if (push) {
1013 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { 994 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
1014 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); 995 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1015 evo_data(push, nv_crtc->fb.handle); 996 evo_data(push, nv_crtc->fb.handle);
1016 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); 997 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1017 evo_data(push, 0xc0000000); 998 evo_data(push, 0xc0000000);
1018 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); 999 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1019 } else 1000 } else
1020 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 1001 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1021 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); 1002 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1022 evo_data(push, nv_crtc->fb.handle); 1003 evo_data(push, nv_crtc->fb.handle);
1023 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); 1004 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
@@ -1112,7 +1093,7 @@ nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1112 1093
1113 push = evo_wait(mast, 64); 1094 push = evo_wait(mast, 64);
1114 if (push) { 1095 if (push) {
1115 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 1096 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1116 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); 1097 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1117 evo_data(push, 0x00800000 | mode->clock); 1098 evo_data(push, 0x00800000 | mode->clock);
1118 evo_data(push, (ilace == 2) ? 2 : 0); 1099 evo_data(push, (ilace == 2) ? 2 : 0);
@@ -1205,7 +1186,7 @@ nv50_crtc_lut_load(struct drm_crtc *crtc)
1205 u16 g = nv_crtc->lut.g[i] >> 2; 1186 u16 g = nv_crtc->lut.g[i] >> 2;
1206 u16 b = nv_crtc->lut.b[i] >> 2; 1187 u16 b = nv_crtc->lut.b[i] >> 2;
1207 1188
1208 if (disp->disp->oclass < NVD0_DISP_CLASS) { 1189 if (disp->disp->oclass < GF110_DISP) {
1209 writew(r + 0x0000, lut + (i * 0x08) + 0); 1190 writew(r + 0x0000, lut + (i * 0x08) + 0);
1210 writew(g + 0x0000, lut + (i * 0x08) + 2); 1191 writew(g + 0x0000, lut + (i * 0x08) + 2);
1211 writew(b + 0x0000, lut + (i * 0x08) + 4); 1192 writew(b + 0x0000, lut + (i * 0x08) + 4);
@@ -1523,7 +1504,7 @@ nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1523 1504
1524 push = evo_wait(mast, 8); 1505 push = evo_wait(mast, 8);
1525 if (push) { 1506 if (push) {
1526 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 1507 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1527 u32 syncs = 0x00000000; 1508 u32 syncs = 0x00000000;
1528 1509
1529 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1510 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -1572,7 +1553,7 @@ nv50_dac_disconnect(struct drm_encoder *encoder)
1572 1553
1573 push = evo_wait(mast, 4); 1554 push = evo_wait(mast, 4);
1574 if (push) { 1555 if (push) {
1575 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 1556 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1576 evo_mthd(push, 0x0400 + (or * 0x080), 1); 1557 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1577 evo_data(push, 0x00000000); 1558 evo_data(push, 0x00000000);
1578 } else { 1559 } else {
@@ -1849,7 +1830,7 @@ nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1849 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); 1830 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1850 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; 1831 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1851 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { 1832 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1852 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 1833 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1853 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); 1834 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1854 evo_data(push, (nv_encoder->ctrl = temp)); 1835 evo_data(push, (nv_encoder->ctrl = temp));
1855 } else { 1836 } else {
@@ -1979,7 +1960,7 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1979 1960
1980 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON); 1961 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1981 1962
1982 if (nv50_vers(mast) >= NVD0_DISP_CLASS) { 1963 if (nv50_vers(mast) >= GF110_DISP) {
1983 u32 *push = evo_wait(mast, 3); 1964 u32 *push = evo_wait(mast, 3);
1984 if (push) { 1965 if (push) {
1985 u32 magic = 0x31ec6000 | (nv_crtc->index << 25); 1966 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
@@ -2154,7 +2135,7 @@ nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2154 2135
2155 push = evo_wait(mast, 8); 2136 push = evo_wait(mast, 8);
2156 if (push) { 2137 if (push) {
2157 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 2138 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2158 u32 ctrl = (depth << 16) | (proto << 8) | owner; 2139 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2159 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 2140 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2160 ctrl |= 0x00001000; 2141 ctrl |= 0x00001000;
@@ -2183,7 +2164,7 @@ nv50_pior_disconnect(struct drm_encoder *encoder)
2183 2164
2184 push = evo_wait(mast, 4); 2165 push = evo_wait(mast, 4);
2185 if (push) { 2166 if (push) {
2186 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { 2167 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2187 evo_mthd(push, 0x0700 + (or * 0x040), 1); 2168 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2188 evo_data(push, 0x00000000); 2169 evo_data(push, 0x00000000);
2189 } 2170 }
@@ -2380,12 +2361,12 @@ nv50_fb_ctor(struct drm_framebuffer *fb)
2380 return -EINVAL; 2361 return -EINVAL;
2381 } 2362 }
2382 2363
2383 if (disp->disp->oclass < NV84_DISP_CLASS) { 2364 if (disp->disp->oclass < G82_DISP) {
2384 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : 2365 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2385 (fb->pitches[0] | 0x00100000); 2366 (fb->pitches[0] | 0x00100000);
2386 nv_fb->r_format |= kind << 16; 2367 nv_fb->r_format |= kind << 16;
2387 } else 2368 } else
2388 if (disp->disp->oclass < NVD0_DISP_CLASS) { 2369 if (disp->disp->oclass < GF110_DISP) {
2389 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : 2370 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2390 (fb->pitches[0] | 0x00100000); 2371 (fb->pitches[0] | 0x00100000);
2391 } else { 2372 } else {
@@ -2497,7 +2478,7 @@ nv50_display_create(struct drm_device *dev)
2497 goto out; 2478 goto out;
2498 2479
2499 /* create crtc objects to represent the hw heads */ 2480 /* create crtc objects to represent the hw heads */
2500 if (disp->disp->oclass >= NVD0_DISP_CLASS) 2481 if (disp->disp->oclass >= GF110_DISP)
2501 crtcs = nvif_rd32(device, 0x022448); 2482 crtcs = nvif_rd32(device, 0x022448);
2502 else 2483 else
2503 crtcs = 2; 2484 crtcs = 2;
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index b0998e7a5396..15dc6a35589e 100644
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -12,6 +12,8 @@
12#define NV_DMA_TO_MEMORY 0x00000003 12#define NV_DMA_TO_MEMORY 0x00000003
13#define NV_DMA_IN_MEMORY 0x0000003d 13#define NV_DMA_IN_MEMORY 0x0000003d
14 14
15#define NV04_DISP 0x00000046
16
15#define NV03_CHANNEL_DMA 0x0000006b 17#define NV03_CHANNEL_DMA 0x0000006b
16#define NV10_CHANNEL_DMA 0x0000006e 18#define NV10_CHANNEL_DMA 0x0000006e
17#define NV17_CHANNEL_DMA 0x0000176e 19#define NV17_CHANNEL_DMA 0x0000176e
@@ -24,6 +26,53 @@
24#define FERMI_CHANNEL_GPFIFO 0x0000906f 26#define FERMI_CHANNEL_GPFIFO 0x0000906f
25#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f 27#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
26 28
29#define NV50_DISP 0x00005070
30#define G82_DISP 0x00008270
31#define GT200_DISP 0x00008370
32#define GT214_DISP 0x00008570
33#define GT206_DISP 0x00008870
34#define GF110_DISP 0x00009070
35#define GK104_DISP 0x00009170
36#define GK110_DISP 0x00009270
37#define GM107_DISP 0x00009470
38
39#define NV50_DISP_CURSOR 0x0000507a
40#define G82_DISP_CURSOR 0x0000827a
41#define GT214_DISP_CURSOR 0x0000857a
42#define GF110_DISP_CURSOR 0x0000907a
43#define GK104_DISP_CURSOR 0x0000917a
44
45#define NV50_DISP_OVERLAY 0x0000507b
46#define G82_DISP_OVERLAY 0x0000827b
47#define GT214_DISP_OVERLAY 0x0000857b
48#define GF110_DISP_OVERLAY 0x0000907b
49#define GK104_DISP_OVERLAY 0x0000917b
50
51#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
52#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
53#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
54#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
55#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
56#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
57#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
58
59#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
60#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
61#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
62#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
63#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
64#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
65#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
66#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
67#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
68
69#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
70#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
71#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
72#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
73#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
74#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
75
27 76
28/******************************************************************************* 77/*******************************************************************************
29 * client 78 * client
@@ -403,4 +452,41 @@ struct nv50_disp_pior_pwr_v0 {
403 __u8 pad03[5]; 452 __u8 pad03[5];
404}; 453};
405 454
455/* core */
456struct nv50_disp_core_channel_dma_v0 {
457 __u8 version;
458 __u8 pad01[3];
459 __u32 pushbuf;
460};
461
462/* cursor immediate */
463struct nv50_disp_cursor_v0 {
464 __u8 version;
465 __u8 head;
466 __u8 pad02[6];
467};
468
469/* base */
470struct nv50_disp_base_channel_dma_v0 {
471 __u8 version;
472 __u8 pad01[2];
473 __u8 head;
474 __u32 pushbuf;
475};
476
477/* overlay */
478struct nv50_disp_overlay_channel_dma_v0 {
479 __u8 version;
480 __u8 pad01[2];
481 __u8 head;
482 __u32 pushbuf;
483};
484
485/* overlay immediate */
486struct nv50_disp_overlay_v0 {
487 __u8 version;
488 __u8 head;
489 __u8 pad02[6];
490};
491
406#endif 492#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 02:23:52 -0400