diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-19 17:23:33 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-10-25 23:28:19 -0400 |
| commit | 5885b7a9f4d2a0405b7e42d44eab4ed2302a8239 (patch) | |
| tree | 8b95a46fb5fcaf03c71f55105bbc6a2a48e1ba8d /drivers/gpu | |
| parent | ceb776bc87280eb8d13f38e4d7afae757e95af44 (diff) | |
drm/radeon/kms: fix vram_width calculation on r6xx/r7xx
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 29 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/r600d.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 30 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/rv770d.h | 5 |
4 files changed, 52 insertions, 16 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 1b5aa1fd368b..e87475c87d52 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
| @@ -339,11 +339,10 @@ int r600_mc_init(struct radeon_device *rdev) | |||
| 339 | { | 339 | { |
| 340 | fixed20_12 a; | 340 | fixed20_12 a; |
| 341 | u32 tmp; | 341 | u32 tmp; |
| 342 | int chansize; | 342 | int chansize, numchan; |
| 343 | int r; | 343 | int r; |
| 344 | 344 | ||
| 345 | /* Get VRAM informations */ | 345 | /* Get VRAM informations */ |
| 346 | rdev->mc.vram_width = 128; | ||
| 347 | rdev->mc.vram_is_ddr = true; | 346 | rdev->mc.vram_is_ddr = true; |
| 348 | tmp = RREG32(RAMCFG); | 347 | tmp = RREG32(RAMCFG); |
| 349 | if (tmp & CHANSIZE_OVERRIDE) { | 348 | if (tmp & CHANSIZE_OVERRIDE) { |
| @@ -353,17 +352,23 @@ int r600_mc_init(struct radeon_device *rdev) | |||
| 353 | } else { | 352 | } else { |
| 354 | chansize = 32; | 353 | chansize = 32; |
| 355 | } | 354 | } |
| 356 | if (rdev->family == CHIP_R600) { | 355 | tmp = RREG32(CHMAP); |
| 357 | rdev->mc.vram_width = 8 * chansize; | 356 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
| 358 | } else if (rdev->family == CHIP_RV670) { | 357 | case 0: |
| 359 | rdev->mc.vram_width = 4 * chansize; | 358 | default: |
| 360 | } else if ((rdev->family == CHIP_RV610) || | 359 | numchan = 1; |
| 361 | (rdev->family == CHIP_RV620)) { | 360 | break; |
| 362 | rdev->mc.vram_width = chansize; | 361 | case 1: |
| 363 | } else if ((rdev->family == CHIP_RV630) || | 362 | numchan = 2; |
| 364 | (rdev->family == CHIP_RV635)) { | 363 | break; |
| 365 | rdev->mc.vram_width = 2 * chansize; | 364 | case 2: |
| 365 | numchan = 4; | ||
| 366 | break; | ||
| 367 | case 3: | ||
| 368 | numchan = 8; | ||
| 369 | break; | ||
| 366 | } | 370 | } |
| 371 | rdev->mc.vram_width = numchan * chansize; | ||
| 367 | /* Could aper size report 0 ? */ | 372 | /* Could aper size report 0 ? */ |
| 368 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 373 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| 369 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 374 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index 5084595eb919..cf238bf5700f 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h | |||
| @@ -270,6 +270,10 @@ | |||
| 270 | #define PCIE_PORT_INDEX 0x0038 | 270 | #define PCIE_PORT_INDEX 0x0038 |
| 271 | #define PCIE_PORT_DATA 0x003C | 271 | #define PCIE_PORT_DATA 0x003C |
| 272 | 272 | ||
| 273 | #define CHMAP 0x2004 | ||
| 274 | #define NOOFCHAN_SHIFT 12 | ||
| 275 | #define NOOFCHAN_MASK 0x00003000 | ||
| 276 | |||
| 273 | #define RAMCFG 0x2408 | 277 | #define RAMCFG 0x2408 |
| 274 | #define NOOFBANK_SHIFT 0 | 278 | #define NOOFBANK_SHIFT 0 |
| 275 | #define NOOFBANK_MASK 0x00000001 | 279 | #define NOOFBANK_MASK 0x00000001 |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 595ac638039d..40553913b928 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
| @@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev) | |||
| 774 | { | 774 | { |
| 775 | fixed20_12 a; | 775 | fixed20_12 a; |
| 776 | u32 tmp; | 776 | u32 tmp; |
| 777 | int chansize, numchan; | ||
| 777 | int r; | 778 | int r; |
| 778 | 779 | ||
| 779 | /* Get VRAM informations */ | 780 | /* Get VRAM informations */ |
| 780 | /* FIXME: Don't know how to determine vram width, need to check | ||
| 781 | * vram_width usage | ||
| 782 | */ | ||
| 783 | rdev->mc.vram_width = 128; | ||
| 784 | rdev->mc.vram_is_ddr = true; | 781 | rdev->mc.vram_is_ddr = true; |
| 782 | tmp = RREG32(MC_ARB_RAMCFG); | ||
| 783 | if (tmp & CHANSIZE_OVERRIDE) { | ||
| 784 | chansize = 16; | ||
| 785 | } else if (tmp & CHANSIZE_MASK) { | ||
| 786 | chansize = 64; | ||
| 787 | } else { | ||
| 788 | chansize = 32; | ||
| 789 | } | ||
| 790 | tmp = RREG32(MC_SHARED_CHMAP); | ||
| 791 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | ||
| 792 | case 0: | ||
| 793 | default: | ||
| 794 | numchan = 1; | ||
| 795 | break; | ||
| 796 | case 1: | ||
| 797 | numchan = 2; | ||
| 798 | break; | ||
| 799 | case 2: | ||
| 800 | numchan = 4; | ||
| 801 | break; | ||
| 802 | case 3: | ||
| 803 | numchan = 8; | ||
| 804 | break; | ||
| 805 | } | ||
| 806 | rdev->mc.vram_width = numchan * chansize; | ||
| 785 | /* Could aper size report 0 ? */ | 807 | /* Could aper size report 0 ? */ |
| 786 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); | 808 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
| 787 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); | 809 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h index 4b9c3d6396ff..a1367ab6f261 100644 --- a/drivers/gpu/drm/radeon/rv770d.h +++ b/drivers/gpu/drm/radeon/rv770d.h | |||
| @@ -129,6 +129,10 @@ | |||
| 129 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 | 129 | #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 |
| 130 | #define HDP_TILING_CONFIG 0x2F3C | 130 | #define HDP_TILING_CONFIG 0x2F3C |
| 131 | 131 | ||
| 132 | #define MC_SHARED_CHMAP 0x2004 | ||
| 133 | #define NOOFCHAN_SHIFT 12 | ||
| 134 | #define NOOFCHAN_MASK 0x00003000 | ||
| 135 | |||
| 132 | #define MC_ARB_RAMCFG 0x2760 | 136 | #define MC_ARB_RAMCFG 0x2760 |
| 133 | #define NOOFBANK_SHIFT 0 | 137 | #define NOOFBANK_SHIFT 0 |
| 134 | #define NOOFBANK_MASK 0x00000003 | 138 | #define NOOFBANK_MASK 0x00000003 |
| @@ -142,6 +146,7 @@ | |||
| 142 | #define CHANSIZE_MASK 0x00000100 | 146 | #define CHANSIZE_MASK 0x00000100 |
| 143 | #define BURSTLENGTH_SHIFT 9 | 147 | #define BURSTLENGTH_SHIFT 9 |
| 144 | #define BURSTLENGTH_MASK 0x00000200 | 148 | #define BURSTLENGTH_MASK 0x00000200 |
| 149 | #define CHANSIZE_OVERRIDE (1 << 11) | ||
| 145 | #define MC_VM_AGP_TOP 0x2028 | 150 | #define MC_VM_AGP_TOP 0x2028 |
| 146 | #define MC_VM_AGP_BOT 0x202C | 151 | #define MC_VM_AGP_BOT 0x202C |
| 147 | #define MC_VM_AGP_BASE 0x2030 | 152 | #define MC_VM_AGP_BASE 0x2030 |
