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authorDave Airlie <airlied@redhat.com>2010-10-18 20:36:47 -0400
committerDave Airlie <airlied@redhat.com>2010-10-19 00:12:22 -0400
commit5480f727dc4c049eb46b191bfaeb034067aa6835 (patch)
treed6b5166fd2e198e05de9027e0e61ebfb6abeb51f /drivers/gpu
parentc9220b0f7cbd1d2272426aa81a72ae2f6582bb71 (diff)
Revert "drm/radeon/kms: remove some pll algo flags"
This reverts commit f28488c282d8916b9b6190cc41714815bbaf97d5. On my rv610 test machine the monitor failed to light up after this. Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c26
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h14
4 files changed, 52 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 037e3260cb7c..176f424975ac 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -501,9 +501,21 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
501 (rdev->family == CHIP_RS740)) 501 (rdev->family == CHIP_RS740))
502 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 502 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
503 RADEON_PLL_PREFER_CLOSEST_LOWER); 503 RADEON_PLL_PREFER_CLOSEST_LOWER);
504 } else 504
505 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
506 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
507 else
508 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
509 } else {
505 pll->flags |= RADEON_PLL_LEGACY; 510 pll->flags |= RADEON_PLL_LEGACY;
506 511
512 if (mode->clock > 200000) /* range limits??? */
513 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
514 else
515 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
516
517 }
518
507 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 519 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
508 if (encoder->crtc == crtc) { 520 if (encoder->crtc == crtc) {
509 radeon_encoder = to_radeon_encoder(encoder); 521 radeon_encoder = to_radeon_encoder(encoder);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 6c6846cdaa30..9151ded9c1cd 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -611,8 +611,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
611 if ((best_vco == 0 && error < best_error) || 611 if ((best_vco == 0 && error < best_error) ||
612 (best_vco != 0 && 612 (best_vco != 0 &&
613 ((best_error > 100 && error < best_error - 100) || 613 ((best_error > 100 && error < best_error - 100) ||
614 (abs(error - best_error) < 100 && 614 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
615 vco_diff < best_vco_diff)))) {
616 best_post_div = post_div; 615 best_post_div = post_div;
617 best_ref_div = ref_div; 616 best_ref_div = ref_div;
618 best_feedback_div = feedback_div; 617 best_feedback_div = feedback_div;
@@ -620,6 +619,29 @@ void radeon_compute_pll(struct radeon_pll *pll,
620 best_freq = current_freq; 619 best_freq = current_freq;
621 best_error = error; 620 best_error = error;
622 best_vco_diff = vco_diff; 621 best_vco_diff = vco_diff;
622 } else if (current_freq == freq) {
623 if (best_freq == -1) {
624 best_post_div = post_div;
625 best_ref_div = ref_div;
626 best_feedback_div = feedback_div;
627 best_frac_feedback_div = frac_feedback_div;
628 best_freq = current_freq;
629 best_error = error;
630 best_vco_diff = vco_diff;
631 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
632 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
633 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
634 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
635 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
636 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
637 best_post_div = post_div;
638 best_ref_div = ref_div;
639 best_feedback_div = feedback_div;
640 best_frac_feedback_div = frac_feedback_div;
641 best_freq = current_freq;
642 best_error = error;
643 best_vco_diff = vco_diff;
644 }
623 } 645 }
624 if (current_freq < freq) 646 if (current_freq < freq)
625 min_frac_feed_div = frac_feedback_div + 1; 647 min_frac_feed_div = frac_feedback_div + 1;
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index c0bf8b7cc56c..f8dae717acc8 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -745,6 +745,11 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
745 745
746 pll->flags = RADEON_PLL_LEGACY; 746 pll->flags = RADEON_PLL_LEGACY;
747 747
748 if (mode->clock > 200000) /* range limits??? */
749 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
750 else
751 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
752
748 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 753 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
749 if (encoder->crtc == crtc) { 754 if (encoder->crtc == crtc) {
750 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 755 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 3cda63e37b28..d58b003e9a04 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -139,10 +139,16 @@ struct radeon_tmds_pll {
139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 139#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
140#define RADEON_PLL_USE_REF_DIV (1 << 2) 140#define RADEON_PLL_USE_REF_DIV (1 << 2)
141#define RADEON_PLL_LEGACY (1 << 3) 141#define RADEON_PLL_LEGACY (1 << 3)
142#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 4) 142#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
143#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5) 143#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
144#define RADEON_PLL_USE_POST_DIV (1 << 6) 144#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
145#define RADEON_PLL_IS_LCD (1 << 7) 145#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
146#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
147#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
148#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
149#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
150#define RADEON_PLL_USE_POST_DIV (1 << 12)
151#define RADEON_PLL_IS_LCD (1 << 13)
146 152
147struct radeon_pll { 153struct radeon_pll {
148 /* reference frequency */ 154 /* reference frequency */