diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-01-20 22:53:21 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-01-24 20:04:44 -0500 |
commit | 51f73d64b46cb765cd5bee3b8d9f5980c44c6446 (patch) | |
tree | 9a48557e7ce719a3fb3d651d2939ad9919d3bae4 /drivers/gpu | |
parent | 0f1cb203b46f8f836afdd2198060ff6169aa7272 (diff) |
drm/nvc0: implement irq handler for whatever's at 0x14xxxx
This is just barely enough to stop a never-ending IRQ storm that can
be triggered by our 3D driver. We have no idea what this engine is..
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_graph.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c index df393f01bf08..eb18a7e89f5b 100644 --- a/drivers/gpu/drm/nouveau/nvc0_graph.c +++ b/drivers/gpu/drm/nouveau/nvc0_graph.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "nvc0_graph.h" | 31 | #include "nvc0_graph.h" |
32 | 32 | ||
33 | static void nvc0_graph_isr(struct drm_device *); | 33 | static void nvc0_graph_isr(struct drm_device *); |
34 | static void nvc0_runk140_isr(struct drm_device *); | ||
34 | static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan); | 35 | static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan); |
35 | 36 | ||
36 | void | 37 | void |
@@ -281,6 +282,7 @@ nvc0_graph_destroy(struct drm_device *dev) | |||
281 | return; | 282 | return; |
282 | 283 | ||
283 | nouveau_irq_unregister(dev, 12); | 284 | nouveau_irq_unregister(dev, 12); |
285 | nouveau_irq_unregister(dev, 25); | ||
284 | 286 | ||
285 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); | 287 | nouveau_gpuobj_ref(NULL, &priv->unk4188b8); |
286 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); | 288 | nouveau_gpuobj_ref(NULL, &priv->unk4188b4); |
@@ -390,6 +392,7 @@ nvc0_graph_create(struct drm_device *dev) | |||
390 | } | 392 | } |
391 | 393 | ||
392 | nouveau_irq_register(dev, 12, nvc0_graph_isr); | 394 | nouveau_irq_register(dev, 12, nvc0_graph_isr); |
395 | nouveau_irq_register(dev, 25, nvc0_runk140_isr); | ||
393 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ | 396 | NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */ |
394 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ | 397 | NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */ |
395 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ | 398 | NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ |
@@ -777,3 +780,19 @@ nvc0_graph_isr(struct drm_device *dev) | |||
777 | 780 | ||
778 | nv_wr32(dev, 0x400500, 0x00010001); | 781 | nv_wr32(dev, 0x400500, 0x00010001); |
779 | } | 782 | } |
783 | |||
784 | static void | ||
785 | nvc0_runk140_isr(struct drm_device *dev) | ||
786 | { | ||
787 | u32 units = nv_rd32(dev, 0x00017c) & 0x1f; | ||
788 | |||
789 | while (units) { | ||
790 | u32 unit = ffs(units) - 1; | ||
791 | u32 reg = 0x140000 + unit * 0x2000; | ||
792 | u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0); | ||
793 | u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0); | ||
794 | |||
795 | NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1); | ||
796 | units &= ~(1 << unit); | ||
797 | } | ||
798 | } | ||