diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-11-09 23:10:04 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-12-21 02:17:09 -0500 |
commit | 4c74eb7ff276813ee73943a3756b295675fb2865 (patch) | |
tree | 29f0c29e5209d572906ed33031e8a42fab84899e /drivers/gpu | |
parent | 3ee0128140eed7d32b785a335099a2ec38258283 (diff) |
drm/nvc0: import initial vm backend
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bo.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_mem.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_vm.c | 31 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_vm.h | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_vm.c | 123 |
7 files changed, 169 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index b1d8941e04d8..e89d89593af1 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -28,7 +28,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ | |||
28 | nv10_gpio.o nv50_gpio.o \ | 28 | nv10_gpio.o nv50_gpio.o \ |
29 | nv50_calc.o \ | 29 | nv50_calc.o \ |
30 | nv04_pm.o nv50_pm.o nva3_pm.o \ | 30 | nv04_pm.o nv50_pm.o nva3_pm.o \ |
31 | nv50_vram.o nv50_vm.o | 31 | nv50_vram.o nv50_vm.o nvc0_vm.o |
32 | 32 | ||
33 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o | 33 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o |
34 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o | 34 | nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 42d1ad62b381..d17ffea3c617 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c | |||
@@ -909,8 +909,9 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |||
909 | break; | 909 | break; |
910 | } | 910 | } |
911 | 911 | ||
912 | ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size, 12, | 912 | ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size, |
913 | NV_MEM_ACCESS_RW, &vram->bar_vma); | 913 | vram->page_shift, NV_MEM_ACCESS_RW, |
914 | &vram->bar_vma); | ||
914 | if (ret) | 915 | if (ret) |
915 | return ret; | 916 | return ret; |
916 | 917 | ||
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 8f13906185b2..57da219fb18b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -69,6 +69,7 @@ struct nouveau_vram { | |||
69 | struct drm_device *dev; | 69 | struct drm_device *dev; |
70 | 70 | ||
71 | struct nouveau_vma bar_vma; | 71 | struct nouveau_vma bar_vma; |
72 | u8 page_shift; | ||
72 | 73 | ||
73 | struct list_head regions; | 74 | struct list_head regions; |
74 | u32 memtype; | 75 | u32 memtype; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 224181193a1f..07be1dd04530 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c | |||
@@ -731,6 +731,10 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man, | |||
731 | if (ret) | 731 | if (ret) |
732 | return ret; | 732 | return ret; |
733 | 733 | ||
734 | node->page_shift = 12; | ||
735 | if (nvbo->vma.node) | ||
736 | node->page_shift = nvbo->vma.node->type; | ||
737 | |||
734 | mem->mm_node = node; | 738 | mem->mm_node = node; |
735 | mem->start = node->offset >> PAGE_SHIFT; | 739 | mem->start = node->offset >> PAGE_SHIFT; |
736 | return 0; | 740 | return 0; |
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.c b/drivers/gpu/drm/nouveau/nouveau_vm.c index b023a64c27d8..97d82aedf86b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vm.c +++ b/drivers/gpu/drm/nouveau/nouveau_vm.c | |||
@@ -295,7 +295,34 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset, | |||
295 | vm->flush = nv50_vm_flush; | 295 | vm->flush = nv50_vm_flush; |
296 | vm->spg_shift = 12; | 296 | vm->spg_shift = 12; |
297 | vm->lpg_shift = 16; | 297 | vm->lpg_shift = 16; |
298 | |||
298 | pgt_bits = 29; | 299 | pgt_bits = 29; |
300 | block = (1 << pgt_bits); | ||
301 | if (length < block) | ||
302 | block = length; | ||
303 | |||
304 | } else | ||
305 | if (dev_priv->card_type == NV_C0) { | ||
306 | vm->map_pgt = nvc0_vm_map_pgt; | ||
307 | vm->map = nvc0_vm_map; | ||
308 | vm->map_sg = nvc0_vm_map_sg; | ||
309 | vm->unmap = nvc0_vm_unmap; | ||
310 | vm->flush = nvc0_vm_flush; | ||
311 | vm->spg_shift = 12; | ||
312 | vm->lpg_shift = 17; | ||
313 | pgt_bits = 27; | ||
314 | |||
315 | /* Should be 4096 everywhere, this is a hack that's | ||
316 | * currently necessary to avoid an elusive bug that | ||
317 | * causes corruption when mixing small/large pages | ||
318 | */ | ||
319 | if (length < (1ULL << 40)) | ||
320 | block = 4096; | ||
321 | else { | ||
322 | block = (1 << pgt_bits); | ||
323 | if (length < block) | ||
324 | block = length; | ||
325 | } | ||
299 | } else { | 326 | } else { |
300 | kfree(vm); | 327 | kfree(vm); |
301 | return -ENOSYS; | 328 | return -ENOSYS; |
@@ -314,10 +341,6 @@ nouveau_vm_new(struct drm_device *dev, u64 offset, u64 length, u64 mm_offset, | |||
314 | vm->refcount = 1; | 341 | vm->refcount = 1; |
315 | vm->pgt_bits = pgt_bits - 12; | 342 | vm->pgt_bits = pgt_bits - 12; |
316 | 343 | ||
317 | block = (1 << pgt_bits); | ||
318 | if (length < block) | ||
319 | block = length; | ||
320 | |||
321 | ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, | 344 | ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, |
322 | block >> 12); | 345 | block >> 12); |
323 | if (ret) { | 346 | if (ret) { |
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h index 105b6f65f19d..e1193515771b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vm.h +++ b/drivers/gpu/drm/nouveau/nouveau_vm.h | |||
@@ -100,4 +100,14 @@ void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt); | |||
100 | void nv50_vm_flush(struct nouveau_vm *); | 100 | void nv50_vm_flush(struct nouveau_vm *); |
101 | void nv50_vm_flush_engine(struct drm_device *, int engine); | 101 | void nv50_vm_flush_engine(struct drm_device *, int engine); |
102 | 102 | ||
103 | /* nvc0_vm.c */ | ||
104 | void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, | ||
105 | struct nouveau_gpuobj *pgt[2]); | ||
106 | void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *, | ||
107 | struct nouveau_vram *, u32 pte, u32 cnt, u64 phys); | ||
108 | void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *, | ||
109 | u32 pte, dma_addr_t *, u32 cnt); | ||
110 | void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt); | ||
111 | void nvc0_vm_flush(struct nouveau_vm *); | ||
112 | |||
103 | #endif | 113 | #endif |
diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c new file mode 100644 index 000000000000..4b9251bb0ff4 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvc0_vm.c | |||
@@ -0,0 +1,123 @@ | |||
1 | /* | ||
2 | * Copyright 2010 Red Hat Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | * Authors: Ben Skeggs | ||
23 | */ | ||
24 | |||
25 | #include "drmP.h" | ||
26 | |||
27 | #include "nouveau_drv.h" | ||
28 | #include "nouveau_vm.h" | ||
29 | |||
30 | void | ||
31 | nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, | ||
32 | struct nouveau_gpuobj *pgt[2]) | ||
33 | { | ||
34 | u32 pde[2] = { 0, 0 }; | ||
35 | |||
36 | if (pgt[0]) | ||
37 | pde[1] = 0x00000001 | (pgt[0]->vinst >> 8); | ||
38 | if (pgt[1]) | ||
39 | pde[0] = 0x00000001 | (pgt[1]->vinst >> 8); | ||
40 | |||
41 | nv_wo32(pgd, (index * 8) + 0, pde[0]); | ||
42 | nv_wo32(pgd, (index * 8) + 4, pde[1]); | ||
43 | } | ||
44 | |||
45 | static inline u64 | ||
46 | nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) | ||
47 | { | ||
48 | phys >>= 8; | ||
49 | |||
50 | phys |= 0x00000001; /* present */ | ||
51 | // if (vma->access & NV_MEM_ACCESS_SYS) | ||
52 | // phys |= 0x00000002; | ||
53 | |||
54 | phys |= ((u64)target << 32); | ||
55 | phys |= ((u64)memtype << 36); | ||
56 | |||
57 | return phys; | ||
58 | } | ||
59 | |||
60 | void | ||
61 | nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, | ||
62 | struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys) | ||
63 | { | ||
64 | u32 next = 1 << (vma->node->type - 8); | ||
65 | |||
66 | phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); | ||
67 | pte <<= 3; | ||
68 | while (cnt--) { | ||
69 | nv_wo32(pgt, pte + 0, lower_32_bits(phys)); | ||
70 | nv_wo32(pgt, pte + 4, upper_32_bits(phys)); | ||
71 | phys += next; | ||
72 | pte += 8; | ||
73 | } | ||
74 | } | ||
75 | |||
76 | void | ||
77 | nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, | ||
78 | u32 pte, dma_addr_t *list, u32 cnt) | ||
79 | { | ||
80 | pte <<= 3; | ||
81 | while (cnt--) { | ||
82 | u64 phys = nvc0_vm_addr(vma, *list++, 0, 5); | ||
83 | nv_wo32(pgt, pte + 0, lower_32_bits(phys)); | ||
84 | nv_wo32(pgt, pte + 4, upper_32_bits(phys)); | ||
85 | pte += 8; | ||
86 | } | ||
87 | } | ||
88 | |||
89 | void | ||
90 | nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) | ||
91 | { | ||
92 | pte <<= 3; | ||
93 | while (cnt--) { | ||
94 | nv_wo32(pgt, pte + 0, 0x00000000); | ||
95 | nv_wo32(pgt, pte + 4, 0x00000000); | ||
96 | pte += 8; | ||
97 | } | ||
98 | } | ||
99 | |||
100 | void | ||
101 | nvc0_vm_flush(struct nouveau_vm *vm) | ||
102 | { | ||
103 | struct drm_nouveau_private *dev_priv = vm->dev->dev_private; | ||
104 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; | ||
105 | struct drm_device *dev = vm->dev; | ||
106 | struct nouveau_vm_pgd *vpgd; | ||
107 | u32 r100c80, engine; | ||
108 | |||
109 | pinstmem->flush(vm->dev); | ||
110 | |||
111 | if (vm == dev_priv->chan_vm) | ||
112 | engine = 1; | ||
113 | else | ||
114 | engine = 5; | ||
115 | |||
116 | list_for_each_entry(vpgd, &vm->pgd_list, head) { | ||
117 | r100c80 = nv_rd32(dev, 0x100c80); | ||
118 | nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8); | ||
119 | nv_wr32(dev, 0x100cbc, 0x80000000 | engine); | ||
120 | if (!nv_wait(dev, 0x100c80, 0xffffffff, r100c80)) | ||
121 | NV_ERROR(dev, "vm flush timeout eng %d\n", engine); | ||
122 | } | ||
123 | } | ||