Merge remote branch 'origin/master' of /home/airlied/kernel//linux-2.6 into drm-core-next

47 files changed, 920 insertions, 551 deletions

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 7e31d4348340..dcbeb98f195a 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -34,6 +34,9 @@
 #include "drm_crtc_helper.h"
 #include "drm_fb_helper.h"
 
+static bool drm_kms_helper_poll = true;
+module_param_named(poll, drm_kms_helper_poll, bool, 0600);
+
 static void drm_mode_validate_flag(struct drm_connector *connector,
                                    int flags)
 {
@@ -99,8 +102,10 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
                         connector->status = connector_status_disconnected;
                 if (connector->funcs->force)
                         connector->funcs->force(connector);
-        } else
-                connector->status = connector->funcs->detect(connector);
+        } else {
+                connector->status = connector->funcs->detect(connector, true);
+                drm_kms_helper_poll_enable(dev);
+        }
 
         if (connector->status == connector_status_disconnected) {
                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] disconnected\n",
@@ -110,11 +115,10 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector,
         }
 
         count = (*connector_funcs->get_modes)(connector);
-        if (!count) {
+        if (count == 0 && connector->status == connector_status_connected)
                 count = drm_add_modes_noedid(connector, 1024, 768);
-                if (!count)
-                        return 0;
-        }
+        if (count == 0)
+                goto prune;
 
         drm_mode_connector_list_update(connector);
 
@@ -633,13 +637,13 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set)
                 mode_changed = true;
 
         if (mode_changed) {
-                old_fb = set->crtc->fb;
-                set->crtc->fb = set->fb;
                 set->crtc->enabled = (set->mode != NULL);
                 if (set->mode != NULL) {
                         DRM_DEBUG_KMS("attempting to set mode from"
                                         " userspace\n");
                         drm_mode_debug_printmodeline(set->mode);
+                        old_fb = set->crtc->fb;
+                        set->crtc->fb = set->fb;
                         if (!drm_crtc_helper_set_mode(set->crtc, set->mode,
                                                       set->x, set->y,
                                                       old_fb)) {
@@ -840,6 +844,9 @@ static void output_poll_execute(struct work_struct *work)
         enum drm_connector_status old_status, status;
         bool repoll = false, changed = false;
 
+        if (!drm_kms_helper_poll)
+                return;
+
         mutex_lock(&dev->mode_config.mutex);
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 
@@ -859,7 +866,7 @@ static void output_poll_execute(struct work_struct *work)
                     !(connector->polled & DRM_CONNECTOR_POLL_HPD))
                         continue;
 
-                status = connector->funcs->detect(connector);
+                status = connector->funcs->detect(connector, false);
                 if (old_status != status)
                         changed = true;
         }
@@ -890,6 +897,9 @@ void drm_kms_helper_poll_enable(struct drm_device *dev)
         bool poll = false;
         struct drm_connector *connector;
 
+        if (!dev->mode_config.poll_enabled || !drm_kms_helper_poll)
+                return;
+
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 if (connector->polled)
                         poll = true;
@@ -919,8 +929,10 @@ void drm_helper_hpd_irq_event(struct drm_device *dev)
 {
         if (!dev->mode_config.poll_enabled)
                 return;
+
         /* kill timer and schedule immediate execution, this doesn't block */
         cancel_delayed_work(&dev->mode_config.output_poll_work);
-        queue_delayed_work(system_nrt_wq, &dev->mode_config.output_poll_work, 0);
+        if (drm_kms_helper_poll)
+                queue_delayed_work(system_nrt_wq, &dev->mode_config.output_poll_work, 0);
 }
 EXPORT_SYMBOL(drm_helper_hpd_irq_event);
diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c
index e20f78b542a7..f5bd9e590c80 100644
--- a/drivers/gpu/drm/drm_pci.c
+++ b/drivers/gpu/drm/drm_pci.c
@@ -164,6 +164,8 @@ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
         dev->hose = pdev->sysdata;
 #endif
 
+        mutex_lock(&drm_global_mutex);
+
         if ((ret = drm_fill_in_dev(dev, ent, driver))) {
                 printk(KERN_ERR "DRM: Fill_in_dev failed.\n");
                 goto err_g2;
@@ -199,6 +201,7 @@ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
                  driver->name, driver->major, driver->minor, driver->patchlevel,
                  driver->date, pci_name(pdev), dev->primary->index);
 
+        mutex_unlock(&drm_global_mutex);
         return 0;
 
 err_g4:
@@ -210,6 +213,7 @@ err_g2:
         pci_disable_device(pdev);
 err_g1:
         kfree(dev);
+        mutex_unlock(&drm_global_mutex);
         return ret;
 }
 EXPORT_SYMBOL(drm_get_pci_dev);
diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c
index 460e9a3afa8d..92d1d0fb7b75 100644
--- a/drivers/gpu/drm/drm_platform.c
+++ b/drivers/gpu/drm/drm_platform.c
@@ -53,6 +53,8 @@ int drm_get_platform_dev(struct platform_device *platdev,
         dev->platformdev = platdev;
         dev->dev = &platdev->dev;
 
+        mutex_lock(&drm_global_mutex);
+
         ret = drm_fill_in_dev(dev, NULL, driver);
 
         if (ret) {
@@ -87,6 +89,8 @@ int drm_get_platform_dev(struct platform_device *platdev,
 
         list_add_tail(&dev->driver_item, &driver->device_list);
 
+        mutex_unlock(&drm_global_mutex);
+
         DRM_INFO("Initialized %s %d.%d.%d %s on minor %d\n",
                  driver->name, driver->major, driver->minor, driver->patchlevel,
                  driver->date, dev->primary->index);
@@ -100,6 +104,7 @@ err_g2:
                 drm_put_minor(&dev->control);
 err_g1:
         kfree(dev);
+        mutex_unlock(&drm_global_mutex);
         return ret;
 }
 EXPORT_SYMBOL(drm_get_platform_dev);
diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c
index 86118a742231..85da4c40694c 100644
--- a/drivers/gpu/drm/drm_sysfs.c
+++ b/drivers/gpu/drm/drm_sysfs.c
@@ -159,7 +159,7 @@ static ssize_t status_show(struct device *device,
         struct drm_connector *connector = to_drm_connector(device);
         enum drm_connector_status status;
 
-        status = connector->funcs->detect(connector);
+        status = connector->funcs->detect(connector, true);
         return snprintf(buf, PAGE_SIZE, "%s\n",
                         drm_get_connector_status_name(status));
 }
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 92d5605a34d1..5e43d7076789 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -31,6 +31,7 @@
 #include <linux/slab.h>
 #include "drmP.h"
 #include "drm.h"
+#include "intel_drv.h"
 #include "i915_drm.h"
 #include "i915_drv.h"
 
@@ -121,6 +122,54 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
         return 0;
 }
 
+static int i915_gem_pageflip_info(struct seq_file *m, void *data)
+{
+        struct drm_info_node *node = (struct drm_info_node *) m->private;
+        struct drm_device *dev = node->minor->dev;
+        unsigned long flags;
+        struct intel_crtc *crtc;
+
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
+                const char *pipe = crtc->pipe ? "B" : "A";
+                const char *plane = crtc->plane ? "B" : "A";
+                struct intel_unpin_work *work;
+
+                spin_lock_irqsave(&dev->event_lock, flags);
+                work = crtc->unpin_work;
+                if (work == NULL) {
+                        seq_printf(m, "No flip due on pipe %s (plane %s)\n",
+                                   pipe, plane);
+                } else {
+                        if (!work->pending) {
+                                seq_printf(m, "Flip queued on pipe %s (plane %s)\n",
+                                           pipe, plane);
+                        } else {
+                                seq_printf(m, "Flip pending (waiting for vsync) on pipe %s (plane %s)\n",
+                                           pipe, plane);
+                        }
+                        if (work->enable_stall_check)
+                                seq_printf(m, "Stall check enabled, ");
+                        else
+                                seq_printf(m, "Stall check waiting for page flip ioctl, ");
+                        seq_printf(m, "%d prepares\n", work->pending);
+
+                        if (work->old_fb_obj) {
+                                struct drm_i915_gem_object *obj_priv = to_intel_bo(work->old_fb_obj);
+                                if(obj_priv)
+                                        seq_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
+                        }
+                        if (work->pending_flip_obj) {
+                                struct drm_i915_gem_object *obj_priv = to_intel_bo(work->pending_flip_obj);
+                                if(obj_priv)
+                                        seq_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj_priv->gtt_offset );
+                        }
+                }
+                spin_unlock_irqrestore(&dev->event_lock, flags);
+        }
+
+        return 0;
+}
+
 static int i915_gem_request_info(struct seq_file *m, void *data)
 {
         struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -777,6 +826,7 @@ static struct drm_info_list i915_debugfs_list[] = {
         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
         {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
+        {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
         {"i915_gem_request", i915_gem_request_info, 0},
         {"i915_gem_seqno", i915_gem_seqno_info, 0},
         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index a7ec93e62f81..9d67b4853030 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -620,8 +620,10 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
                 ret = copy_from_user(cliprects, batch->cliprects,
                                      batch->num_cliprects *
                                      sizeof(struct drm_clip_rect));
-                if (ret != 0)
+                if (ret != 0) {
+                        ret = -EFAULT;
                         goto fail_free;
+                }
         }
 
         mutex_lock(&dev->struct_mutex);
@@ -662,8 +664,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
                 return -ENOMEM;
 
         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
-        if (ret != 0)
+        if (ret != 0) {
+                ret = -EFAULT;
                 goto fail_batch_free;
+        }
 
         if (cmdbuf->num_cliprects) {
                 cliprects = kcalloc(cmdbuf->num_cliprects,
@@ -676,8 +680,10 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
                                      cmdbuf->num_cliprects *
                                      sizeof(struct drm_clip_rect));
-                if (ret != 0)
+                if (ret != 0) {
+                        ret = -EFAULT;
                         goto fail_clip_free;
+                }
         }
 
         mutex_lock(&dev->struct_mutex);
@@ -885,7 +891,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
         u32 temp_lo, temp_hi = 0;
         u64 mchbar_addr;
-        int ret = 0;
+        int ret;
 
         if (IS_I965G(dev))
                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
@@ -895,22 +901,23 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 #ifdef CONFIG_PNP
         if (mchbar_addr &&
-            pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
-                ret = 0;
-                goto out;
-        }
+            pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
+                return 0;
 #endif
 
         /* Get some space for it */
-        ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
+        dev_priv->mch_res.name = "i915 MCHBAR";
+        dev_priv->mch_res.flags = IORESOURCE_MEM;
+        ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
+                                     &dev_priv->mch_res,
                                      MCHBAR_SIZE, MCHBAR_SIZE,
                                      PCIBIOS_MIN_MEM,
-                                     0,   pcibios_align_resource,
+                                     0, pcibios_align_resource,
                                      dev_priv->bridge_dev);
         if (ret) {
                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
                 dev_priv->mch_res.start = 0;
-                goto out;
+                return ret;
         }
 
         if (IS_I965G(dev))
@@ -919,8 +926,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
 
         pci_write_config_dword(dev_priv->bridge_dev, reg,
                                lower_32_bits(dev_priv->mch_res.start));
-out:
-        return ret;
+        return 0;
 }
 
 /* Setup MCHBAR if possible, return true if we should disable it again */
@@ -2082,6 +2088,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
                 goto free_priv;
         }
 
+        /* overlay on gen2 is broken and can't address above 1G */
+        if (IS_GEN2(dev))
+                dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
+
         dev_priv->regs = ioremap(base, size);
         if (!dev_priv->regs) {
                 DRM_ERROR("failed to map registers\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e6afa68775b0..9ed9d23caf14 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -61,91 +61,86 @@ extern int intel_agp_enabled;
         .driver_data = (unsigned long) info }
 
 static const struct intel_device_info intel_i830_info = {
-        .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
+        .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_845g_info = {
-        .is_i8xx = 1,
+        .gen = 2, .is_i8xx = 1,
 };
 
 static const struct intel_device_info intel_i85x_info = {
-        .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
+        .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
         .cursor_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i865g_info = {
-        .is_i8xx = 1,
+        .gen = 2, .is_i8xx = 1,
 };
 
 static const struct intel_device_info intel_i915g_info = {
-        .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
+        .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
 };
 static const struct intel_device_info intel_i915gm_info = {
-        .is_i9xx = 1,  .is_mobile = 1,
+        .gen = 3, .is_i9xx = 1,  .is_mobile = 1,
         .cursor_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945g_info = {
-        .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
+        .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
 };
 static const struct intel_device_info intel_i945gm_info = {
-        .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
+        .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
         .has_hotplug = 1, .cursor_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i965g_info = {
-        .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .has_hotplug = 1,
+        .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
+        .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
-        .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
-        .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1,
-        .has_hotplug = 1,
+        .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
+        .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_g33_info = {
-        .is_g33 = 1, .is_i9xx = 1, .need_gfx_hws = 1,
-        .has_hotplug = 1,
+        .gen = 3, .is_g33 = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_g45_info = {
-        .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
-        .has_pipe_cxsr = 1,
-        .has_hotplug = 1,
+        .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1,
+        .has_pipe_cxsr = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_gm45_info = {
-        .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
+        .gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1,
         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
-        .has_pipe_cxsr = 1,
-        .has_hotplug = 1,
+        .has_pipe_cxsr = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_pineview_info = {
-        .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
-        .need_gfx_hws = 1,
-        .has_hotplug = 1,
+        .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_ironlake_d_info = {
-        .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
-        .has_pipe_cxsr = 1,
-        .has_hotplug = 1,
+        .gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_ironlake_m_info = {
-        .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
-        .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
-        .has_hotplug = 1,
+        .gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_d_info = {
-        .is_i965g = 1, .is_i9xx = 1, .need_gfx_hws = 1,
-        .has_hotplug = 1, .is_gen6 = 1,
+        .gen = 6, .is_i965g = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_hotplug = 1,
 };
 
 static const struct intel_device_info intel_sandybridge_m_info = {
-        .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .need_gfx_hws = 1,
-        .has_hotplug = 1, .is_gen6 = 1,
+        .gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1,
+        .need_gfx_hws = 1, .has_hotplug = 1,
 };
 
 static const struct pci_device_id pciidlist[] = {               /* aka */
@@ -175,13 +170,18 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
+        INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
+        INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
+        INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
+        INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
+        INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
         {0, 0, 0}
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 047cd7ce7e1b..af4a263cf257 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -191,6 +191,7 @@ struct drm_i915_display_funcs {
 };
 
 struct intel_device_info {
+        u8 gen;
         u8 is_mobile : 1;
         u8 is_i8xx : 1;
         u8 is_i85x : 1;
@@ -206,7 +207,6 @@ struct intel_device_info {
         u8 is_broadwater : 1;
         u8 is_crestline : 1;
         u8 is_ironlake : 1;
-        u8 is_gen6 : 1;
         u8 has_fbc : 1;
         u8 has_rc6 : 1;
         u8 has_pipe_cxsr : 1;
@@ -1162,7 +1162,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
-#define IS_GEN2(dev)            (INTEL_INFO(dev)->is_i8xx)
 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
@@ -1181,27 +1180,13 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
 #define IS_IRONLAKE(dev)        (INTEL_INFO(dev)->is_ironlake)
 #define IS_I9XX(dev)            (INTEL_INFO(dev)->is_i9xx)
-#define IS_GEN6(dev)            (INTEL_INFO(dev)->is_gen6)
 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 
-#define IS_GEN3(dev)    (IS_I915G(dev) ||                       \
-                         IS_I915GM(dev) ||                      \
-                         IS_I945G(dev) ||                       \
-                         IS_I945GM(dev) ||                      \
-                         IS_G33(dev) || \
-                         IS_PINEVIEW(dev))
-#define IS_GEN4(dev)    ((dev)->pci_device == 0x2972 ||         \
-                         (dev)->pci_device == 0x2982 ||         \
-                         (dev)->pci_device == 0x2992 ||         \
-                         (dev)->pci_device == 0x29A2 ||         \
-                         (dev)->pci_device == 0x2A02 ||         \
-                         (dev)->pci_device == 0x2A12 ||         \
-                         (dev)->pci_device == 0x2E02 ||         \
-                         (dev)->pci_device == 0x2E12 ||         \
-                         (dev)->pci_device == 0x2E22 ||         \
-                         (dev)->pci_device == 0x2E32 ||         \
-                         (dev)->pci_device == 0x2A42 ||         \
-                         (dev)->pci_device == 0x2E42)
+#define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
+#define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
+#define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
+#define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
+#define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
 
 #define HAS_BSD(dev)            (IS_IRONLAKE(dev) || IS_G4X(dev))
 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index df5a7135c261..cf4ffbee1c00 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -34,6 +34,7 @@
 #include <linux/slab.h>
 #include <linux/swap.h>
 #include <linux/pci.h>
+#include <linux/intel-gtt.h>
 
 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
@@ -135,12 +136,15 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
                 return -ENOMEM;
 
         ret = drm_gem_handle_create(file_priv, obj, &handle);
-        drm_gem_object_unreference_unlocked(obj);
-        if (ret)
+        if (ret) {
+                drm_gem_object_unreference_unlocked(obj);
                 return ret;
+        }
 
-        args->handle = handle;
+        /* Sink the floating reference from kref_init(handlecount) */
+        drm_gem_object_handle_unreference_unlocked(obj);
 
+        args->handle = handle;
         return 0;
 }
 
@@ -2347,14 +2351,21 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
 
         reg->obj = obj;
 
-        if (IS_GEN6(dev))
+        switch (INTEL_INFO(dev)->gen) {
+        case 6:
                 sandybridge_write_fence_reg(reg);
-        else if (IS_I965G(dev))
+                break;
+        case 5:
+        case 4:
                 i965_write_fence_reg(reg);
-        else if (IS_I9XX(dev))
+                break;
+        case 3:
                 i915_write_fence_reg(reg);
-        else
+                break;
+        case 2:
                 i830_write_fence_reg(reg);
+                break;
+        }
 
         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
                         obj_priv->tiling_mode);
@@ -2377,22 +2388,26 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
         struct drm_i915_fence_reg *reg =
                 &dev_priv->fence_regs[obj_priv->fence_reg];
+        uint32_t fence_reg;
 
-        if (IS_GEN6(dev)) {
+        switch (INTEL_INFO(dev)->gen) {
+        case 6:
                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
                              (obj_priv->fence_reg * 8), 0);
-        } else if (IS_I965G(dev)) {
+                break;
+        case 5:
+        case 4:
                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
-        } else {
-                uint32_t fence_reg;
-
-                if (obj_priv->fence_reg < 8)
-                        fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
+                break;
+        case 3:
+                if (obj_priv->fence_reg > 8)
+                        fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
                 else
-                        fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
-                                                       8) * 4;
+        case 2:
+                        fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
 
                 I915_WRITE(fence_reg, 0);
+                break;
         }
 
         reg->obj = NULL;
@@ -3585,6 +3600,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                 if (ret != 0) {
                         DRM_ERROR("copy %d cliprects failed: %d\n",
                                   args->num_cliprects, ret);
+                        ret = -EFAULT;
                         goto pre_mutex_err;
                 }
         }
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 72cae3cccad8..e85246ef691c 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -79,6 +79,7 @@ mark_free(struct drm_i915_gem_object *obj_priv,
            struct list_head *unwind)
 {
         list_add(&obj_priv->evict_list, unwind);
+        drm_gem_object_reference(&obj_priv->base);
         return drm_mm_scan_add_block(obj_priv->gtt_space);
 }
 
@@ -165,6 +166,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
         list_for_each_entry(obj_priv, &unwind_list, evict_list) {
                 ret = drm_mm_scan_remove_block(obj_priv->gtt_space);
                 BUG_ON(ret);
+                drm_gem_object_unreference(&obj_priv->base);
         }
 
         /* We expect the caller to unpin, evict all and try again, or give up.
@@ -181,18 +183,21 @@ found:
                          * scanning, therefore store to be evicted objects on a
                          * temporary list. */
                         list_move(&obj_priv->evict_list, &eviction_list);
-                }
+                } else
+                        drm_gem_object_unreference(&obj_priv->base);
         }
 
         /* Unbinding will emit any required flushes */
         list_for_each_entry_safe(obj_priv, tmp_obj_priv,
                                  &eviction_list, evict_list) {
 #if WATCH_LRU
-                DRM_INFO("%s: evicting %p\n", __func__, obj);
+                DRM_INFO("%s: evicting %p\n", __func__, &obj_priv->base);
 #endif
                 ret = i915_gem_object_unbind(&obj_priv->base);
                 if (ret)
                         return ret;
+
+                drm_gem_object_unreference(&obj_priv->base);
         }
 
         /* The just created free hole should be on the top of the free stack
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 16861b800fee..744225ebb4b2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -887,6 +887,49 @@ static void i915_handle_error(struct drm_device *dev, bool wedged)
         queue_work(dev_priv->wq, &dev_priv->error_work);
 }
 
+static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
+{
+        drm_i915_private_t *dev_priv = dev->dev_private;
+        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
+        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+        struct drm_i915_gem_object *obj_priv;
+        struct intel_unpin_work *work;
+        unsigned long flags;
+        bool stall_detected;
+
+        /* Ignore early vblank irqs */
+        if (intel_crtc == NULL)
+                return;
+
+        spin_lock_irqsave(&dev->event_lock, flags);
+        work = intel_crtc->unpin_work;
+
+        if (work == NULL || work->pending || !work->enable_stall_check) {
+                /* Either the pending flip IRQ arrived, or we're too early. Don't check */
+                spin_unlock_irqrestore(&dev->event_lock, flags);
+                return;
+        }
+
+        /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
+        obj_priv = to_intel_bo(work->pending_flip_obj);
+        if(IS_I965G(dev)) {
+                int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
+                stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
+        } else {
+                int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
+                stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
+                                                        crtc->y * crtc->fb->pitch +
+                                                        crtc->x * crtc->fb->bits_per_pixel/8);
+        }
+
+        spin_unlock_irqrestore(&dev->event_lock, flags);
+
+        if (stall_detected) {
+                DRM_DEBUG_DRIVER("Pageflip stall detected\n");
+                intel_prepare_page_flip(dev, intel_crtc->plane);
+        }
+}
+
 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 {
         struct drm_device *dev = (struct drm_device *) arg;
@@ -1004,15 +1047,19 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
                 if (pipea_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 0);
-                        if (!dev_priv->flip_pending_is_done)
+                        if (!dev_priv->flip_pending_is_done) {
+                                i915_pageflip_stall_check(dev, 0);
                                 intel_finish_page_flip(dev, 0);
+                        }
                 }
 
                 if (pipeb_stats & vblank_status) {
                         vblank++;
                         drm_handle_vblank(dev, 1);
-                        if (!dev_priv->flip_pending_is_done)
+                        if (!dev_priv->flip_pending_is_done) {
+                                i915_pageflip_stall_check(dev, 1);
                                 intel_finish_page_flip(dev, 1);
+                        }
                 }
 
                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
@@ -1303,17 +1350,25 @@ void i915_hangcheck_elapsed(unsigned long data)
                 i915_seqno_passed(i915_get_gem_seqno(dev,
                                 &dev_priv->render_ring),
                         i915_get_tail_request(dev)->seqno)) {
+                bool missed_wakeup = false;
+
                 dev_priv->hangcheck_count = 0;
 
                 /* Issue a wake-up to catch stuck h/w. */
-                if (dev_priv->render_ring.waiting_gem_seqno |
-                    dev_priv->bsd_ring.waiting_gem_seqno) {
-                        DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
-                        if (dev_priv->render_ring.waiting_gem_seqno)
-                                DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
-                        if (dev_priv->bsd_ring.waiting_gem_seqno)
-                                DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
+                if (dev_priv->render_ring.waiting_gem_seqno &&
+                    waitqueue_active(&dev_priv->render_ring.irq_queue)) {
+                        DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
+                        missed_wakeup = true;
                 }
+
+                if (dev_priv->bsd_ring.waiting_gem_seqno &&
+                    waitqueue_active(&dev_priv->bsd_ring.irq_queue)) {
+                        DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
+                        missed_wakeup = true;
+                }
+
+                if (missed_wakeup)
+                        DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
                 return;
         }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 67e3ec1a6af9..4f5e15577e89 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -319,6 +319,7 @@
 
 #define MI_MODE         0x0209c
 # define VS_TIMER_DISPATCH                              (1 << 6)
+# define MI_FLUSH_ENABLE                                (1 << 11)
 
 #define SCPD0           0x0209c /* 915+ only */
 #define IER             0x020a0
@@ -2205,9 +2206,17 @@
 #define  WM1_LP_SR_EN           (1<<31)
 #define  WM1_LP_LATENCY_SHIFT   24
 #define  WM1_LP_LATENCY_MASK    (0x7f<<24)
+#define  WM1_LP_FBC_LP1_MASK    (0xf<<20)
+#define  WM1_LP_FBC_LP1_SHIFT   20
 #define  WM1_LP_SR_MASK         (0x1ff<<8)
 #define  WM1_LP_SR_SHIFT        8
 #define  WM1_LP_CURSOR_MASK     (0x3f)
+#define WM2_LP_ILK              0x4510c
+#define  WM2_LP_EN              (1<<31)
+#define WM3_LP_ILK              0x45110
+#define  WM3_LP_EN              (1<<31)
+#define WM1S_LP_ILK             0x45120
+#define  WM1S_LP_EN             (1<<31)
 
 /* Memory latency timer register */
 #define MLTR_ILK                0x11222
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 2c6b98f2440e..31f08581e93a 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -789,16 +789,25 @@ int i915_save_state(struct drm_device *dev)
                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 
         /* Fences */
-        if (IS_I965G(dev)) {
+        switch (INTEL_INFO(dev)->gen) {
+        case 6:
+                for (i = 0; i < 16; i++)
+                        dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
+                break;
+        case 5:
+        case 4:
                 for (i = 0; i < 16; i++)
                         dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
-        } else {
-                for (i = 0; i < 8; i++)
-                        dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
-
+                break;
+        case 3:
                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
                         for (i = 0; i < 8; i++)
                                 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
+        case 2:
+                for (i = 0; i < 8; i++)
+                        dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
+                break;
+
         }
 
         return 0;
@@ -815,15 +824,24 @@ int i915_restore_state(struct drm_device *dev)
         I915_WRITE(HWS_PGA, dev_priv->saveHWS);
 
         /* Fences */
-        if (IS_I965G(dev)) {
+        switch (INTEL_INFO(dev)->gen) {
+        case 6:
+                for (i = 0; i < 16; i++)
+                        I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
+                break;
+        case 5:
+        case 4:
                 for (i = 0; i < 16; i++)
                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
-        } else {
-                for (i = 0; i < 8; i++)
-                        I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
+                break;
+        case 3:
+        case 2:
                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
                         for (i = 0; i < 8; i++)
                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
+                for (i = 0; i < 8; i++)
+                        I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
+                break;
         }
 
         i915_restore_display(dev);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 4b7735196cd5..197d4f32585a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -188,7 +188,7 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
 
         if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
                      1000, 1))
-                DRM_ERROR("timed out waiting for FORCE_TRIGGER");
+                DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
 
         if (turn_off_dac) {
                 I915_WRITE(PCH_ADPA, temp);
@@ -245,7 +245,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
                 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
                               CRT_HOTPLUG_FORCE_DETECT) == 0,
                              1000, 1))
-                        DRM_ERROR("timed out waiting for FORCE_DETECT to go off");
+                        DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
         }
 
         stat = I915_READ(PORT_HOTPLUG_STAT);
@@ -400,7 +400,8 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
         return status;
 }
 
-static enum drm_connector_status intel_crt_detect(struct drm_connector *connector)
+static enum drm_connector_status
+intel_crt_detect(struct drm_connector *connector, bool force)
 {
         struct drm_device *dev = connector->dev;
         struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -419,6 +420,9 @@ static enum drm_connector_status intel_crt_detect(struct drm_connector *connecto
         if (intel_crt_detect_ddc(encoder))
                 return connector_status_connected;
 
+        if (!force)
+                return connector->status;
+
         /* for pre-945g platforms use load detect */
         if (encoder->crtc && encoder->crtc->enabled) {
                 status = intel_crt_load_detect(encoder->crtc, intel_encoder);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 11a3394f5fe1..b5bf51a4502d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -990,6 +990,22 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
         struct drm_i915_private *dev_priv = dev->dev_private;
         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 
+        /* Clear existing vblank status. Note this will clear any other
+         * sticky status fields as well.
+         *
+         * This races with i915_driver_irq_handler() with the result
+         * that either function could miss a vblank event.  Here it is not
+         * fatal, as we will either wait upon the next vblank interrupt or
+         * timeout.  Generally speaking intel_wait_for_vblank() is only
+         * called during modeset at which time the GPU should be idle and
+         * should *not* be performing page flips and thus not waiting on
+         * vblanks...
+         * Currently, the result of us stealing a vblank from the irq
+         * handler is that a single frame will be skipped during swapbuffers.
+         */
+        I915_WRITE(pipestat_reg,
+                   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
+
         /* Wait for vblank interrupt bit to set */
         if (wait_for((I915_READ(pipestat_reg) &
                       PIPE_VBLANK_INTERRUPT_STATUS),
@@ -1486,7 +1502,7 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                         dspcntr &= ~DISPPLANE_TILED;
         }
 
-        if (IS_IRONLAKE(dev))
+        if (HAS_PCH_SPLIT(dev))
                 /* must disable */
                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
 
@@ -1495,20 +1511,19 @@ intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
         Start = obj_priv->gtt_offset;
         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
 
-        DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
+                      Start, Offset, x, y, fb->pitch);
         I915_WRITE(dspstride, fb->pitch);
         if (IS_I965G(dev)) {
-                I915_WRITE(dspbase, Offset);
-                I915_READ(dspbase);
                 I915_WRITE(dspsurf, Start);
-                I915_READ(dspsurf);
                 I915_WRITE(dsptileoff, (y << 16) | x);
+                I915_WRITE(dspbase, Offset);
         } else {
                 I915_WRITE(dspbase, Start + Offset);
-                I915_READ(dspbase);
         }
+        POSTING_READ(dspbase);
 
-        if ((IS_I965G(dev) || plane == 0))
+        if (IS_I965G(dev) || plane == 0)
                 intel_update_fbc(crtc, &crtc->mode);
 
         intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -1522,7 +1537,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                     struct drm_framebuffer *old_fb)
 {
         struct drm_device *dev = crtc->dev;
-        struct drm_i915_private *dev_priv = dev->dev_private;
         struct drm_i915_master_private *master_priv;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_framebuffer *intel_fb;
@@ -1530,13 +1544,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
         struct drm_gem_object *obj;
         int pipe = intel_crtc->pipe;
         int plane = intel_crtc->plane;
-        unsigned long Start, Offset;
-        int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
-        int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
-        int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
-        int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
-        int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
-        u32 dspcntr;
         int ret;
 
         /* no fb bound */
@@ -1572,71 +1579,18 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                 return ret;
         }
 
-        dspcntr = I915_READ(dspcntr_reg);
-        /* Mask out pixel format bits in case we change it */
-        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
-        switch (crtc->fb->bits_per_pixel) {
-        case 8:
-                dspcntr |= DISPPLANE_8BPP;
-                break;
-        case 16:
-                if (crtc->fb->depth == 15)
-                        dspcntr |= DISPPLANE_15_16BPP;
-                else
-                        dspcntr |= DISPPLANE_16BPP;
-                break;
-        case 24:
-        case 32:
-                if (crtc->fb->depth == 30)
-                        dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
-                else
-                        dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
-                break;
-        default:
-                DRM_ERROR("Unknown color depth\n");
+        ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
+        if (ret) {
                 i915_gem_object_unpin(obj);
                 mutex_unlock(&dev->struct_mutex);
-                return -EINVAL;
-        }
-        if (IS_I965G(dev)) {
-                if (obj_priv->tiling_mode != I915_TILING_NONE)
-                        dspcntr |= DISPPLANE_TILED;
-                else
-                        dspcntr &= ~DISPPLANE_TILED;
-        }
-
-        if (HAS_PCH_SPLIT(dev))
-                /* must disable */
-                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
-
-        I915_WRITE(dspcntr_reg, dspcntr);
-
-        Start = obj_priv->gtt_offset;
-        Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
-
-        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
-                      Start, Offset, x, y, crtc->fb->pitch);
-        I915_WRITE(dspstride, crtc->fb->pitch);
-        if (IS_I965G(dev)) {
-                I915_WRITE(dspsurf, Start);
-                I915_WRITE(dsptileoff, (y << 16) | x);
-                I915_WRITE(dspbase, Offset);
-        } else {
-                I915_WRITE(dspbase, Start + Offset);
+                return ret;
         }
-        POSTING_READ(dspbase);
-
-        if ((IS_I965G(dev) || plane == 0))
-                intel_update_fbc(crtc, &crtc->mode);
-
-        intel_wait_for_vblank(dev, pipe);
 
         if (old_fb) {
                 intel_fb = to_intel_framebuffer(old_fb);
                 obj_priv = to_intel_bo(intel_fb->obj);
                 i915_gem_object_unpin(intel_fb->obj);
         }
-        intel_increase_pllclock(crtc, true);
 
         mutex_unlock(&dev->struct_mutex);
 
@@ -1911,9 +1865,6 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
-        int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
-        int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
-        int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
@@ -1982,15 +1933,19 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                 }
 
                 /* Enable panel fitting for LVDS */
-                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
-                    || HAS_eDP || intel_pch_has_edp(crtc)) {
-                        if (dev_priv->pch_pf_size) {
-                                temp = I915_READ(pf_ctl_reg);
-                                I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
-                                I915_WRITE(pf_win_pos, dev_priv->pch_pf_pos);
-                                I915_WRITE(pf_win_size, dev_priv->pch_pf_size);
-                        } else
-                                I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
+                if (dev_priv->pch_pf_size &&
+                    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+                    || HAS_eDP || intel_pch_has_edp(crtc))) {
+                        /* Force use of hard-coded filter coefficients
+                         * as some pre-programmed values are broken,
+                         * e.g. x201.
+                         */
+                        I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
+                                   PF_ENABLE | PF_FILTER_MED_3x3);
+                        I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
+                                   dev_priv->pch_pf_pos);
+                        I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
+                                   dev_priv->pch_pf_size);
                 }
 
                 /* Enable CPU pipe */
@@ -2115,7 +2070,7 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
                         I915_READ(transconf_reg);
 
-                        if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 10, 0))
+                        if (wait_for(I915_READ(transconf_reg) & TRANS_STATE_ENABLE, 100, 1))
                                 DRM_ERROR("failed to enable transcoder\n");
                 }
 
@@ -2155,14 +2110,8 @@ static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
                 udelay(100);
 
                 /* Disable PF */
-                temp = I915_READ(pf_ctl_reg);
-                if ((temp & PF_ENABLE) != 0) {
-                        I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
-                        I915_READ(pf_ctl_reg);
-                }
-                I915_WRITE(pf_win_size, 0);
-                POSTING_READ(pf_win_size);
-
+                I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
+                I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
 
                 /* disable CPU FDI tx and PCH FDI rx */
                 temp = I915_READ(fdi_tx_reg);
@@ -2421,6 +2370,9 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
         int pipe = intel_crtc->pipe;
         bool enabled;
 
+        if (intel_crtc->dpms_mode == mode)
+                return;
+
         intel_crtc->dpms_mode = mode;
         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
 
@@ -2511,11 +2463,19 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
                                   struct drm_display_mode *adjusted_mode)
 {
         struct drm_device *dev = crtc->dev;
+
         if (HAS_PCH_SPLIT(dev)) {
                 /* FDI link clock is fixed at 2.7G */
                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
                         return false;
         }
+
+        /* XXX some encoders set the crtcinfo, others don't.
+         * Obviously we need some form of conflict resolution here...
+         */
+        if (adjusted_mode->crtc_htotal == 0)
+                drm_mode_set_crtcinfo(adjusted_mode, 0);
+
         return true;
 }
 
@@ -2815,14 +2775,8 @@ static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
         /* Don't promote wm_size to unsigned... */
         if (wm_size > (long)wm->max_wm)
                 wm_size = wm->max_wm;
-        if (wm_size <= 0) {
+        if (wm_size <= 0)
                 wm_size = wm->default_wm;
-                DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
-                          " entries required = %ld, available = %lu.\n",
-                          entries_required + wm->guard_size,
-                          wm->fifo_size);
-        }
-
         return wm_size;
 }
 
@@ -3436,8 +3390,7 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
                 reg_value = I915_READ(WM1_LP_ILK);
                 reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
                                WM1_LP_CURSOR_MASK);
-                reg_value |= WM1_LP_SR_EN |
-                             (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
+                reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
                              (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
 
                 I915_WRITE(WM1_LP_ILK, reg_value);
@@ -3554,10 +3507,9 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
-        bool is_edp = false;
+        struct intel_encoder *has_edp_encoder = NULL;
         struct drm_mode_config *mode_config = &dev->mode_config;
         struct drm_encoder *encoder;
-        struct intel_encoder *intel_encoder = NULL;
         const intel_limit_t *limit;
         int ret;
         struct fdi_m_n m_n = {0};
@@ -3578,12 +3530,12 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
         drm_vblank_pre_modeset(dev, pipe);
 
         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+                struct intel_encoder *intel_encoder;
 
-                if (!encoder || encoder->crtc != crtc)
+                if (encoder->crtc != crtc)
                         continue;
 
                 intel_encoder = enc_to_intel_encoder(encoder);
-
                 switch (intel_encoder->type) {
                 case INTEL_OUTPUT_LVDS:
                         is_lvds = true;
@@ -3607,7 +3559,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                         is_dp = true;
                         break;
                 case INTEL_OUTPUT_EDP:
-                        is_edp = true;
+                        has_edp_encoder = intel_encoder;
                         break;
                 }
 
@@ -3685,10 +3637,10 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 int lane = 0, link_bw, bpp;
                 /* eDP doesn't require FDI link, so just set DP M/N
                    according to current link config */
-                if (is_edp) {
+                if (has_edp_encoder) {
                         target_clock = mode->clock;
-                        intel_edp_link_config(intel_encoder,
-                                        &lane, &link_bw);
+                        intel_edp_link_config(has_edp_encoder,
+                                              &lane, &link_bw);
                 } else {
                         /* DP over FDI requires target mode clock
                            instead of link clock */
@@ -3709,7 +3661,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                                 temp |= PIPE_8BPC;
                         else
                                 temp |= PIPE_6BPC;
-                } else if (is_edp || (is_dp && intel_pch_has_edp(crtc))) {
+                } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
                         switch (dev_priv->edp_bpp/3) {
                         case 8:
                                 temp |= PIPE_8BPC;
@@ -3782,7 +3734,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 
                 udelay(200);
 
-                if (is_edp) {
+                if (has_edp_encoder) {
                         if (dev_priv->lvds_use_ssc) {
                                 temp |= DREF_SSC1_ENABLE;
                                 I915_WRITE(PCH_DREF_CONTROL, temp);
@@ -3931,7 +3883,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 dpll_reg = pch_dpll_reg;
         }
 
-        if (!is_edp) {
+        if (!has_edp_encoder) {
                 I915_WRITE(fp_reg, fp);
                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
                 I915_READ(dpll_reg);
@@ -4026,7 +3978,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 }
         }
 
-        if (!is_edp) {
+        if (!has_edp_encoder) {
                 I915_WRITE(fp_reg, fp);
                 I915_WRITE(dpll_reg, dpll);
                 I915_READ(dpll_reg);
@@ -4105,7 +4057,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                 I915_WRITE(link_m1_reg, m_n.link_m);
                 I915_WRITE(link_n1_reg, m_n.link_n);
 
-                if (is_edp) {
+                if (has_edp_encoder) {
                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
                 } else {
                         /* enable FDI RX PLL too */
@@ -4911,15 +4863,6 @@ static void intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(intel_crtc);
 }
 
-struct intel_unpin_work {
-        struct work_struct work;
-        struct drm_device *dev;
-        struct drm_gem_object *old_fb_obj;
-        struct drm_gem_object *pending_flip_obj;
-        struct drm_pending_vblank_event *event;
-        int pending;
-};
-
 static void intel_unpin_work_fn(struct work_struct *__work)
 {
         struct intel_unpin_work *work =
@@ -5007,7 +4950,8 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane)
 
         spin_lock_irqsave(&dev->event_lock, flags);
         if (intel_crtc->unpin_work) {
-                intel_crtc->unpin_work->pending = 1;
+                if ((++intel_crtc->unpin_work->pending) > 1)
+                        DRM_ERROR("Prepared flip multiple times\n");
         } else {
                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
         }
@@ -5026,9 +4970,9 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
         unsigned long flags, offset;
-        int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
-        int ret, pipesrc;
-        u32 flip_mask;
+        int pipe = intel_crtc->pipe;
+        u32 pf, pipesrc;
+        int ret;
 
         work = kzalloc(sizeof *work, GFP_KERNEL);
         if (work == NULL)
@@ -5077,42 +5021,73 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         atomic_inc(&obj_priv->pending_flip);
         work->pending_flip_obj = obj;
 
-        if (intel_crtc->plane)
-                flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
-        else
-                flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
-
         if (IS_GEN3(dev) || IS_GEN2(dev)) {
+                u32 flip_mask;
+
+                if (intel_crtc->plane)
+                        flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
+                else
+                        flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
+
                 BEGIN_LP_RING(2);
                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
                 OUT_RING(0);
                 ADVANCE_LP_RING();
         }
 
+        work->enable_stall_check = true;
+
         /* Offset into the new buffer for cases of shared fbs between CRTCs */
-        offset = obj_priv->gtt_offset;
-        offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+        offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
 
         BEGIN_LP_RING(4);
-        if (IS_I965G(dev)) {
+        switch(INTEL_INFO(dev)->gen) {
+        case 2:
                 OUT_RING(MI_DISPLAY_FLIP |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(offset | obj_priv->tiling_mode);
-                pipesrc = I915_READ(pipesrc_reg); 
-                OUT_RING(pipesrc & 0x0fff0fff);
-        } else if (IS_GEN3(dev)) {
+                OUT_RING(obj_priv->gtt_offset + offset);
+                OUT_RING(MI_NOOP);
+                break;
+
+        case 3:
                 OUT_RING(MI_DISPLAY_FLIP_I915 |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(offset);
+                OUT_RING(obj_priv->gtt_offset + offset);
                 OUT_RING(MI_NOOP);
-        } else {
+                break;
+
+        case 4:
+        case 5:
+                /* i965+ uses the linear or tiled offsets from the
+                 * Display Registers (which do not change across a page-flip)
+                 * so we need only reprogram the base address.
+                 */
                 OUT_RING(MI_DISPLAY_FLIP |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(offset);
-                OUT_RING(MI_NOOP);
+                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+
+                /* XXX Enabling the panel-fitter across page-flip is so far
+                 * untested on non-native modes, so ignore it for now.
+                 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
+                 */
+                pf = 0;
+                pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
+                OUT_RING(pf | pipesrc);
+                break;
+
+        case 6:
+                OUT_RING(MI_DISPLAY_FLIP |
+                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
+                OUT_RING(fb->pitch | obj_priv->tiling_mode);
+                OUT_RING(obj_priv->gtt_offset);
+
+                pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
+                pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
+                OUT_RING(pf | pipesrc);
+                break;
         }
         ADVANCE_LP_RING();
 
@@ -5193,7 +5168,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
 
         intel_crtc->cursor_addr = 0;
-        intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
+        intel_crtc->dpms_mode = -1;
         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
 
         intel_crtc->busy = false;
@@ -5701,6 +5676,9 @@ void intel_init_clock_gating(struct drm_device *dev)
                         I915_WRITE(DISP_ARB_CTL,
                                         (I915_READ(DISP_ARB_CTL) |
                                                 DISP_FBC_WM_DIS));
+                I915_WRITE(WM3_LP_ILK, 0);
+                I915_WRITE(WM2_LP_ILK, 0);
+                I915_WRITE(WM1_LP_ILK, 0);
                 }
                 /*
                  * Based on the document from hardware guys the following bits
@@ -5722,8 +5700,7 @@ void intel_init_clock_gating(struct drm_device *dev)
                                    ILK_DPFC_DIS2 |
                                    ILK_CLK_FBC);
                 }
-                if (IS_GEN6(dev))
-                        return;
+                return;
         } else if (IS_G4X(dev)) {
                 uint32_t dspclk_gate;
                 I915_WRITE(RENCLK_GATE_D1, 0);
@@ -5784,11 +5761,9 @@ void intel_init_clock_gating(struct drm_device *dev)
                                 OUT_RING(MI_FLUSH);
                                 ADVANCE_LP_RING();
                         }
-                } else {
+                } else
                         DRM_DEBUG_KMS("Failed to allocate render context."
-                                      "Disable RC6\n");
-                        return;
-                }
+                                       "Disable RC6\n");
         }
 
         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 9caccd03dccb..1a51ee07de3e 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -239,7 +239,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         uint32_t ch_data = ch_ctl + 4;
         int i;
         int recv_bytes;
-        uint32_t ctl;
         uint32_t status;
         uint32_t aux_clock_divider;
         int try, precharge;
@@ -263,41 +262,43 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         else
                 precharge = 5;
 
+        if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
+                DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
+                          I915_READ(ch_ctl));
+                return -EBUSY;
+        }
+
         /* Must try at least 3 times according to DP spec */
         for (try = 0; try < 5; try++) {
                 /* Load the send data into the aux channel data registers */
-                for (i = 0; i < send_bytes; i += 4) {
-                        uint32_t    d = pack_aux(send + i, send_bytes - i);
-        
-                        I915_WRITE(ch_data + i, d);
-                }
-        
-                ctl = (DP_AUX_CH_CTL_SEND_BUSY |
-                       DP_AUX_CH_CTL_TIME_OUT_400us |
-                       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
-                       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
-                       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
-                       DP_AUX_CH_CTL_DONE |
-                       DP_AUX_CH_CTL_TIME_OUT_ERROR |
-                       DP_AUX_CH_CTL_RECEIVE_ERROR);
+                for (i = 0; i < send_bytes; i += 4)
+                        I915_WRITE(ch_data + i,
+                                   pack_aux(send + i, send_bytes - i));
         
                 /* Send the command and wait for it to complete */
-                I915_WRITE(ch_ctl, ctl);
-                (void) I915_READ(ch_ctl);
+                I915_WRITE(ch_ctl,
+                           DP_AUX_CH_CTL_SEND_BUSY |
+                           DP_AUX_CH_CTL_TIME_OUT_400us |
+                           (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
+                           (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
+                           (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
+                           DP_AUX_CH_CTL_DONE |
+                           DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                           DP_AUX_CH_CTL_RECEIVE_ERROR);
                 for (;;) {
-                        udelay(100);
                         status = I915_READ(ch_ctl);
                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
                                 break;
+                        udelay(100);
                 }
         
                 /* Clear done status and any errors */
-                I915_WRITE(ch_ctl, (status |
-                                DP_AUX_CH_CTL_DONE |
-                                DP_AUX_CH_CTL_TIME_OUT_ERROR |
-                                DP_AUX_CH_CTL_RECEIVE_ERROR));
-                (void) I915_READ(ch_ctl);
-                if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
+                I915_WRITE(ch_ctl,
+                           status |
+                           DP_AUX_CH_CTL_DONE |
+                           DP_AUX_CH_CTL_TIME_OUT_ERROR |
+                           DP_AUX_CH_CTL_RECEIVE_ERROR);
+                if (status & DP_AUX_CH_CTL_DONE)
                         break;
         }
 
@@ -324,15 +325,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
         /* Unload any bytes sent back from the other side */
         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
-
         if (recv_bytes > recv_size)
                 recv_bytes = recv_size;
         
-        for (i = 0; i < recv_bytes; i += 4) {
-                uint32_t    d = I915_READ(ch_data + i);
-
-                unpack_aux(d, recv + i, recv_bytes - i);
-        }
+        for (i = 0; i < recv_bytes; i += 4)
+                unpack_aux(I915_READ(ch_data + i),
+                           recv + i, recv_bytes - i);
 
         return recv_bytes;
 }
@@ -1388,7 +1386,7 @@ ironlake_dp_detect(struct drm_connector *connector)
  * \return false if DP port is disconnected.
  */
 static enum drm_connector_status
-intel_dp_detect(struct drm_connector *connector)
+intel_dp_detect(struct drm_connector *connector, bool force)
 {
         struct drm_encoder *encoder = intel_attached_encoder(connector);
         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0e92aa07b382..ad312ca6b3e5 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -176,6 +176,16 @@ struct intel_crtc {
 #define enc_to_intel_encoder(x) container_of(x, struct intel_encoder, enc)
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 
+struct intel_unpin_work {
+        struct work_struct work;
+        struct drm_device *dev;
+        struct drm_gem_object *old_fb_obj;
+        struct drm_gem_object *pending_flip_obj;
+        struct drm_pending_vblank_event *event;
+        int pending;
+        bool enable_stall_check;
+};
+
 struct i2c_adapter *intel_i2c_create(struct drm_device *dev, const u32 reg,
                                      const char *name);
 void intel_i2c_destroy(struct i2c_adapter *adapter);
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index a399f4b2c1c5..7c9ec1472d46 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -221,7 +221,8 @@ static void intel_dvo_mode_set(struct drm_encoder *encoder,
  *
  * Unimplemented.
  */
-static enum drm_connector_status intel_dvo_detect(struct drm_connector *connector)
+static enum drm_connector_status
+intel_dvo_detect(struct drm_connector *connector, bool force)
 {
         struct drm_encoder *encoder = intel_attached_encoder(connector);
         struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index ccd4c97e6524..926934a482ec 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -139,7 +139,7 @@ static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
 }
 
 static enum drm_connector_status
-intel_hdmi_detect(struct drm_connector *connector)
+intel_hdmi_detect(struct drm_connector *connector, bool force)
 {
         struct drm_encoder *encoder = intel_attached_encoder(connector);
         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index b819c1081147..6ec39a86ed06 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -445,7 +445,8 @@ static void intel_lvds_mode_set(struct drm_encoder *encoder,
  * connected and closed means disconnected.  We also send hotplug events as
  * needed, using lid status notification from the input layer.
  */
-static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
+static enum drm_connector_status
+intel_lvds_detect(struct drm_connector *connector, bool force)
 {
         struct drm_device *dev = connector->dev;
         enum drm_connector_status status = connector_status_connected;
@@ -540,7 +541,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
          * the LID nofication event.
          */
         if (connector)
-                connector->status = connector->funcs->detect(connector);
+                connector->status = connector->funcs->detect(connector,
+                                                             false);
+
         /* Don't force modeset on machines where it causes a GPU lockup */
         if (dmi_check_system(intel_no_modeset_on_lid))
                 return NOTIFY_OK;
@@ -875,8 +878,6 @@ void intel_lvds_init(struct drm_device *dev)
 
         intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
         intel_encoder->crtc_mask = (1 << 1);
-        if (IS_I965G(dev))
-                intel_encoder->crtc_mask |= (1 << 0);
         drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 4f00390d7c61..1d306a458be6 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -25,6 +25,8 @@
  *
  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  */
+
+#include <linux/seq_file.h>
 #include "drmP.h"
 #include "drm.h"
 #include "i915_drm.h"
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 51e9c9e718c4..cb3508f78bc3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -220,9 +220,13 @@ static int init_render_ring(struct drm_device *dev,
 {
         drm_i915_private_t *dev_priv = dev->dev_private;
         int ret = init_ring_common(dev, ring);
+        int mode;
+
         if (IS_I9XX(dev) && !IS_GEN3(dev)) {
-                I915_WRITE(MI_MODE,
-                                (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
+                mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
+                if (IS_GEN6(dev))
+                        mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
+                I915_WRITE(MI_MODE, mode);
         }
         return ret;
 }
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 093e914e8a41..e8e902d614ed 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1061,8 +1061,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
                 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
                         return false;
 
-                if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
-                        return false;
+                (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
+                                                             mode,
+                                                             adjusted_mode);
         } else if (intel_sdvo->is_lvds) {
                 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, 0);
 
@@ -1070,8 +1071,9 @@ static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
                                                             intel_sdvo->sdvo_lvds_fixed_mode))
                         return false;
 
-                if (!intel_sdvo_set_input_timings_for_mode(intel_sdvo, mode, adjusted_mode))
-                        return false;
+                (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
+                                                             mode,
+                                                             adjusted_mode);
         }
 
         /* Make the CRTC code factor in the SDVO pixel multiplier.  The
@@ -1108,10 +1110,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
         in_out.in0 = intel_sdvo->attached_output;
         in_out.in1 = 0;
 
-        if (!intel_sdvo_set_value(intel_sdvo,
-                                  SDVO_CMD_SET_IN_OUT_MAP,
-                                  &in_out, sizeof(in_out)))
-                return;
+        intel_sdvo_set_value(intel_sdvo,
+                             SDVO_CMD_SET_IN_OUT_MAP,
+                             &in_out, sizeof(in_out));
 
         if (intel_sdvo->is_hdmi) {
                 if (!intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
@@ -1122,11 +1123,9 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
 
         /* We have tried to get input timing in mode_fixup, and filled into
            adjusted_mode */
-        if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
-                intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
+        intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
+        if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
                 input_dtd.part2.sdvo_flags = intel_sdvo->sdvo_flags;
-        } else
-                intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
 
         /* If it's a TV, we already set the output timing in mode_fixup.
          * Otherwise, the output timing is equal to the input timing.
@@ -1137,8 +1136,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
                                                   intel_sdvo->attached_output))
                         return;
 
-                if (!intel_sdvo_set_output_timing(intel_sdvo, &input_dtd))
-                        return;
+                (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
         }
 
         /* Set the input timing to the screen. Assume always input 0. */
@@ -1165,8 +1163,7 @@ static void intel_sdvo_mode_set(struct drm_encoder *encoder,
                 intel_sdvo_set_input_timing(encoder, &input_dtd);
         }
 #else
-        if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
-                return;
+        (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
 #endif
 
         sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
@@ -1420,7 +1417,7 @@ intel_analog_is_connected(struct drm_device *dev)
         if (!analog_connector)
                 return false;
 
-        if (analog_connector->funcs->detect(analog_connector) ==
+        if (analog_connector->funcs->detect(analog_connector, false) ==
                         connector_status_disconnected)
                 return false;
 
@@ -1489,7 +1486,8 @@ intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
         return status;
 }
 
-static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
+static enum drm_connector_status
+intel_sdvo_detect(struct drm_connector *connector, bool force)
 {
         uint16_t response;
         struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -1932,6 +1930,41 @@ static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
         .destroy = intel_sdvo_enc_destroy,
 };
 
+static void
+intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
+{
+        uint16_t mask = 0;
+        unsigned int num_bits;
+
+        /* Make a mask of outputs less than or equal to our own priority in the
+         * list.
+         */
+        switch (sdvo->controlled_output) {
+        case SDVO_OUTPUT_LVDS1:
+                mask |= SDVO_OUTPUT_LVDS1;
+        case SDVO_OUTPUT_LVDS0:
+                mask |= SDVO_OUTPUT_LVDS0;
+        case SDVO_OUTPUT_TMDS1:
+                mask |= SDVO_OUTPUT_TMDS1;
+        case SDVO_OUTPUT_TMDS0:
+                mask |= SDVO_OUTPUT_TMDS0;
+        case SDVO_OUTPUT_RGB1:
+                mask |= SDVO_OUTPUT_RGB1;
+        case SDVO_OUTPUT_RGB0:
+                mask |= SDVO_OUTPUT_RGB0;
+                break;
+        }
+
+        /* Count bits to find what number we are in the priority list. */
+        mask &= sdvo->caps.output_flags;
+        num_bits = hweight16(mask);
+        /* If more than 3 outputs, default to DDC bus 3 for now. */
+        if (num_bits > 3)
+                num_bits = 3;
+
+        /* Corresponds to SDVO_CONTROL_BUS_DDCx */
+        sdvo->ddc_bus = 1 << num_bits;
+}
 
 /**
  * Choose the appropriate DDC bus for control bus switch command for this
@@ -1951,7 +1984,10 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
         else
                 mapping = &(dev_priv->sdvo_mappings[1]);
 
-        sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
+        if (mapping->initialized)
+                sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
+        else
+                intel_sdvo_guess_ddc_bus(sdvo);
 }
 
 static bool
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index d2029efee982..4a117e318a73 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1231,7 +1231,6 @@ intel_tv_detect_type (struct intel_tv *intel_tv)
         struct drm_encoder *encoder = &intel_tv->base.enc;
         struct drm_device *dev = encoder->dev;
         struct drm_i915_private *dev_priv = dev->dev_private;
-        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
         unsigned long irqflags;
         u32 tv_ctl, save_tv_ctl;
         u32 tv_dac, save_tv_dac;
@@ -1268,11 +1267,15 @@ intel_tv_detect_type (struct intel_tv *intel_tv)
                    DAC_C_0_7_V);
         I915_WRITE(TV_CTL, tv_ctl);
         I915_WRITE(TV_DAC, tv_dac);
-        intel_wait_for_vblank(dev, intel_crtc->pipe);
+        POSTING_READ(TV_DAC);
+        msleep(20);
+
         tv_dac = I915_READ(TV_DAC);
         I915_WRITE(TV_DAC, save_tv_dac);
         I915_WRITE(TV_CTL, save_tv_ctl);
-        intel_wait_for_vblank(dev, intel_crtc->pipe);
+        POSTING_READ(TV_CTL);
+        msleep(20);
+
         /*
          *  A B C
          *  0 1 1 Composite
@@ -1338,7 +1341,7 @@ static void intel_tv_find_better_format(struct drm_connector *connector)
  * we have a pipe programmed in order to probe the TV.
  */
 static enum drm_connector_status
-intel_tv_detect(struct drm_connector *connector)
+intel_tv_detect(struct drm_connector *connector, bool force)
 {
         struct drm_display_mode mode;
         struct drm_encoder *encoder = intel_attached_encoder(connector);
@@ -1350,7 +1353,7 @@ intel_tv_detect(struct drm_connector *connector)
 
         if (encoder->crtc && encoder->crtc->enabled) {
                 type = intel_tv_detect_type(intel_tv);
-        } else {
+        } else if (force) {
                 struct drm_crtc *crtc;
                 int dpms_mode;
 
@@ -1361,10 +1364,9 @@ intel_tv_detect(struct drm_connector *connector)
                         intel_release_load_detect_pipe(&intel_tv->base, connector,
                                                        dpms_mode);
                 } else
-                        type = -1;
-        }
-
-        intel_tv->type = type;
+                        return connector_status_unknown;
+        } else
+                return connector->status;
 
         if (type < 0)
                 return connector_status_disconnected;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index a1473fff06ac..87186a4bbf03 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -168,7 +168,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector,
 }
 
 static enum drm_connector_status
-nouveau_connector_detect(struct drm_connector *connector)
+nouveau_connector_detect(struct drm_connector *connector, bool force)
 {
         struct drm_device *dev = connector->dev;
         struct nouveau_connector *nv_connector = nouveau_connector(connector);
@@ -246,7 +246,7 @@ detect_analog:
 }
 
 static enum drm_connector_status
-nouveau_connector_detect_lvds(struct drm_connector *connector)
+nouveau_connector_detect_lvds(struct drm_connector *connector, bool force)
 {
         struct drm_device *dev = connector->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -267,7 +267,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector)
 
         /* Try retrieving EDID via DDC */
         if (!dev_priv->vbios.fp_no_ddc) {
-                status = nouveau_connector_detect(connector);
+                status = nouveau_connector_detect(connector, force);
                 if (status == connector_status_connected)
                         goto out;
         }
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 6b208ffafa8d..87ac21ec23d2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -64,16 +64,17 @@ nouveau_fence_update(struct nouveau_channel *chan)
         struct nouveau_fence *fence;
         uint32_t sequence;
 
+        spin_lock(&chan->fence.lock);
+
         if (USE_REFCNT)
                 sequence = nvchan_rd32(chan, 0x48);
         else
                 sequence = atomic_read(&chan->fence.last_sequence_irq);
 
         if (chan->fence.sequence_ack == sequence)
-                return;
+                goto out;
         chan->fence.sequence_ack = sequence;
 
-        spin_lock(&chan->fence.lock);
         list_for_each_safe(entry, tmp, &chan->fence.pending) {
                 fence = list_entry(entry, struct nouveau_fence, entry);
 
@@ -85,6 +86,7 @@ nouveau_fence_update(struct nouveau_channel *chan)
                 if (sequence == chan->fence.sequence_ack)
                         break;
         }
+out:
         spin_unlock(&chan->fence.lock);
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 581c67cd7b24..ead7b8fc53fc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -245,7 +245,7 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
                 list_del(&nvbo->entry);
                 nvbo->reserved_by = NULL;
                 ttm_bo_unreserve(&nvbo->bo);
-                drm_gem_object_unreference(nvbo->gem);
+                drm_gem_object_unreference_unlocked(nvbo->gem);
         }
 }
 
@@ -300,7 +300,7 @@ retry:
                         validate_fini(op, NULL);
                         if (ret == -EAGAIN)
                                 ret = ttm_bo_wait_unreserved(&nvbo->bo, false);
-                        drm_gem_object_unreference(gem);
+                        drm_gem_object_unreference_unlocked(gem);
                         if (ret) {
                                 NV_ERROR(dev, "fail reserve\n");
                                 return ret;
@@ -616,8 +616,6 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
                 return PTR_ERR(bo);
         }
 
-        mutex_lock(&dev->struct_mutex);
-
         /* Mark push buffers as being used on PFIFO, the validation code
          * will then make sure that if the pushbuf bo moves, that they
          * happen on the kernel channel, which will in turn cause a sync
@@ -731,7 +729,6 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
 out:
         validate_fini(&op, fence);
         nouveau_fence_unref((void**)&fence);
-        mutex_unlock(&dev->struct_mutex);
         kfree(bo);
         kfree(push);
 
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index c95bf9b681dd..91ef93cf1f35 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -139,6 +139,8 @@ nv50_instmem_init(struct drm_device *dev)
         chan->file_priv = (struct drm_file *)-2;
         dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
 
+        INIT_LIST_HEAD(&chan->ramht_refs);
+
         /* Channel's PRAMIN object + heap */
         ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
                                                         NULL, &chan->ramin);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 577239a24fd5..cd0290f946cf 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -332,6 +332,11 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
         args.usV_SyncWidth =
                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
 
+        args.ucOverscanRight = radeon_crtc->h_border;
+        args.ucOverscanLeft = radeon_crtc->h_border;
+        args.ucOverscanBottom = radeon_crtc->v_border;
+        args.ucOverscanTop = radeon_crtc->v_border;
+
         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
                 misc |= ATOM_VSYNC_POLARITY;
         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
@@ -534,6 +539,21 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
                                         pll->algo = PLL_ALGO_LEGACY;
                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
                                 }
+                                /* There is some evidence (often anecdotal) that RV515/RV620 LVDS
+                                 * (on some boards at least) prefers the legacy algo.  I'm not
+                                 * sure whether this should handled generically or on a
+                                 * case-by-case quirk basis.  Both algos should work fine in the
+                                 * majority of cases.
+                                 */
+                                if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) &&
+                                    ((rdev->family == CHIP_RV515) ||
+                                     (rdev->family == CHIP_RV620))) {
+                                        /* allow the user to overrride just in case */
+                                        if (radeon_new_pll == 1)
+                                                pll->algo = PLL_ALGO_NEW;
+                                        else
+                                                pll->algo = PLL_ALGO_LEGACY;
+                                }
                         } else {
                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
@@ -1056,11 +1076,11 @@ static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
 
         if (rdev->family >= CHIP_RV770) {
                 if (radeon_crtc->crtc_id) {
-                        WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
-                        WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+                        WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
+                        WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
                 } else {
-                        WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
-                        WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
+                        WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
+                        WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
                 }
         }
         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
@@ -1197,8 +1217,18 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
+        struct drm_encoder *encoder;
+        bool is_tvcv = false;
 
-        /* TODO color tiling */
+        list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+                /* find tv std */
+                if (encoder->crtc == crtc) {
+                        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+                        if (radeon_encoder->active_device &
+                            (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
+                                is_tvcv = true;
+                }
+        }
 
         atombios_disable_ss(crtc);
         /* always set DCPLL */
@@ -1207,9 +1237,14 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
         atombios_crtc_set_pll(crtc, adjusted_mode);
         atombios_enable_ss(crtc);
 
-        if (ASIC_IS_AVIVO(rdev))
+        if (ASIC_IS_DCE4(rdev))
                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
-        else {
+        else if (ASIC_IS_AVIVO(rdev)) {
+                if (is_tvcv)
+                        atombios_crtc_set_timing(crtc, adjusted_mode);
+                else
+                        atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
+        } else {
                 atombios_crtc_set_timing(crtc, adjusted_mode);
                 if (radeon_crtc->crtc_id == 0)
                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 957d5067ad9c..79082d4398ae 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -675,6 +675,43 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
         return 0;
 }
 
+static int evergreen_cp_start(struct radeon_device *rdev)
+{
+        int r;
+        uint32_t cp_me;
+
+        r = radeon_ring_lock(rdev, 7);
+        if (r) {
+                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+                return r;
+        }
+        radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
+        radeon_ring_write(rdev, 0x1);
+        radeon_ring_write(rdev, 0x0);
+        radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
+        radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
+        radeon_ring_write(rdev, 0);
+        radeon_ring_write(rdev, 0);
+        radeon_ring_unlock_commit(rdev);
+
+        cp_me = 0xff;
+        WREG32(CP_ME_CNTL, cp_me);
+
+        r = radeon_ring_lock(rdev, 4);
+        if (r) {
+                DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
+                return r;
+        }
+        /* init some VGT regs */
+        radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+        radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
+        radeon_ring_write(rdev, 0xe);
+        radeon_ring_write(rdev, 0x10);
+        radeon_ring_unlock_commit(rdev);
+
+        return 0;
+}
+
 int evergreen_cp_resume(struct radeon_device *rdev)
 {
         u32 tmp;
@@ -719,7 +756,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
         rdev->cp.rptr = RREG32(CP_RB_RPTR);
         rdev->cp.wptr = RREG32(CP_RB_WPTR);
 
-        r600_cp_start(rdev);
+        evergreen_cp_start(rdev);
         rdev->cp.ready = true;
         r = radeon_ring_test(rdev);
         if (r) {
@@ -1123,14 +1160,25 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                                                                         EVERGREEN_MAX_BACKENDS_MASK));
                         break;
                 }
-        } else
-                gb_backend_map =
-                        evergreen_get_tile_pipe_to_backend_map(rdev,
-                                                               rdev->config.evergreen.max_tile_pipes,
-                                                               rdev->config.evergreen.max_backends,
-                                                               ((EVERGREEN_MAX_BACKENDS_MASK <<
-                                                                 rdev->config.evergreen.max_backends) &
-                                                                EVERGREEN_MAX_BACKENDS_MASK));
+        } else {
+                switch (rdev->family) {
+                case CHIP_CYPRESS:
+                case CHIP_HEMLOCK:
+                        gb_backend_map = 0x66442200;
+                        break;
+                case CHIP_JUNIPER:
+                        gb_backend_map = 0x00006420;
+                        break;
+                default:
+                        gb_backend_map =
+                                evergreen_get_tile_pipe_to_backend_map(rdev,
+                                                                       rdev->config.evergreen.max_tile_pipes,
+                                                                       rdev->config.evergreen.max_backends,
+                                                                       ((EVERGREEN_MAX_BACKENDS_MASK <<
+                                                                         rdev->config.evergreen.max_backends) &
+                                                                        EVERGREEN_MAX_BACKENDS_MASK));
+                }
+        }
 
         rdev->config.evergreen.tile_config = gb_addr_config;
         WREG32(GB_BACKEND_MAP, gb_backend_map);
@@ -2054,11 +2102,6 @@ int evergreen_resume(struct radeon_device *rdev)
          */
         /* post card */
         atom_asic_init(rdev->mode_info.atom_context);
-        /* Initialize clocks */
-        r = radeon_clocks_init(rdev);
-        if (r) {
-                return r;
-        }
 
         r = evergreen_startup(rdev);
         if (r) {
@@ -2164,9 +2207,6 @@ int evergreen_init(struct radeon_device *rdev)
         radeon_surface_init(rdev);
         /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
-        r = radeon_clocks_init(rdev);
-        if (r)
-                return r;
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
         if (r)
@@ -2236,7 +2276,6 @@ void evergreen_fini(struct radeon_device *rdev)
         evergreen_pcie_gart_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
-        radeon_clocks_fini(rdev);
         radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e817a0bb5eb4..e151f16a8f86 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -2020,18 +2020,7 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l
                 return false;
         }
         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
-        if (elapsed >= 3000) {
-                /* very likely the improbable case where current
-                 * rptr is equal to last recorded, a while ago, rptr
-                 * this is more likely a false positive update tracking
-                 * information which should force us to be recall at
-                 * latter point
-                 */
-                lockup->last_cp_rptr = cp->rptr;
-                lockup->last_jiffies = jiffies;
-                return false;
-        }
-        if (elapsed >= 1000) {
+        if (elapsed >= 10000) {
                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
                 return true;
         }
@@ -3308,13 +3297,14 @@ int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
         unsigned long size;
         unsigned prim_walk;
         unsigned nverts;
+        unsigned num_cb = track->num_cb;
 
-        for (i = 0; i < track->num_cb; i++) {
+        if (!track->zb_cb_clear && !track->color_channel_mask &&
+            !track->blend_read_enable)
+                num_cb = 0;
+
+        for (i = 0; i < num_cb; i++) {
                 if (track->cb[i].robj == NULL) {
-                        if (!(track->zb_cb_clear || track->color_channel_mask ||
-                              track->blend_read_enable)) {
-                                continue;
-                        }
                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
                         return -EINVAL;
                 }
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index d0ebae9dde25..afc18d87fdca 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2119,10 +2119,7 @@ int r600_cp_start(struct radeon_device *rdev)
         }
         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
         radeon_ring_write(rdev, 0x1);
-        if (rdev->family >= CHIP_CEDAR) {
-                radeon_ring_write(rdev, 0x0);
-                radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
-        } else if (rdev->family >= CHIP_RV770) {
+        if (rdev->family >= CHIP_RV770) {
                 radeon_ring_write(rdev, 0x0);
                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
         } else {
@@ -2489,11 +2486,6 @@ int r600_resume(struct radeon_device *rdev)
          */
         /* post card */
         atom_asic_init(rdev->mode_info.atom_context);
-        /* Initialize clocks */
-        r = radeon_clocks_init(rdev);
-        if (r) {
-                return r;
-        }
 
         r = r600_startup(rdev);
         if (r) {
@@ -2586,9 +2578,6 @@ int r600_init(struct radeon_device *rdev)
         radeon_surface_init(rdev);
         /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
-        r = radeon_clocks_init(rdev);
-        if (r)
-                return r;
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
         if (r)
@@ -2663,7 +2652,6 @@ void r600_fini(struct radeon_device *rdev)
         radeon_agp_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
-        radeon_clocks_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
         kfree(rdev->bios);
@@ -3541,7 +3529,7 @@ void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
          */
         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) {
-                void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
+                void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
                 u32 tmp;
 
                 WREG32(HDP_DEBUG1, 0);
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index d13622ae74e9..9ceb2a1ce799 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -1,3 +1,28 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
+
 #include "drmP.h"
 #include "drm.h"
 #include "radeon_drm.h"
diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.h b/drivers/gpu/drm/radeon/r600_blit_shaders.h
index fdc3b378cbb0..f437d36dd98c 100644
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.h
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.h
@@ -1,3 +1,27 @@
+/*
+ * Copyright 2009 Advanced Micro Devices, Inc.
+ * Copyright 2009 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ */
 
 #ifndef R600_BLIT_SHADERS_H
 #define R600_BLIT_SHADERS_H
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index d8864949e387..250a3a918193 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -1170,9 +1170,8 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
         /* using get ib will give us the offset into the mipmap bo */
         word0 = radeon_get_ib_value(p, idx + 3) << 8;
         if ((mipmap_size + word0) > radeon_bo_size(mipmap)) {
-                dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
-                        w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));
-                return -EINVAL;
+                /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
+                  w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/
         }
         return 0;
 }
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 3dfcfa3ca425..a168d644bf9e 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1013,6 +1013,11 @@ int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
                                 struct drm_file *filp);
 
+/* VRAM scratch page for HDP bug */
+struct r700_vram_scratch {
+        struct radeon_bo                *robj;
+        volatile uint32_t               *ptr;
+};
 
 /*
  * Core structure, functions and helpers.
@@ -1079,6 +1084,7 @@ struct radeon_device {
         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
         struct r600_blit r600_blit;
+        struct r700_vram_scratch vram_scratch;
         int msi_enabled; /* msi enabled */
         struct r600_ih ih; /* r6/700 interrupt ring */
         struct workqueue_struct *wq;
@@ -1333,8 +1339,6 @@ extern bool radeon_card_posted(struct radeon_device *rdev);
 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
 extern void radeon_update_display_priority(struct radeon_device *rdev);
 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
-extern int radeon_clocks_init(struct radeon_device *rdev);
-extern void radeon_clocks_fini(struct radeon_device *rdev);
 extern void radeon_scratch_init(struct radeon_device *rdev);
 extern void radeon_surface_init(struct radeon_device *rdev);
 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index a21bf88e8c2d..25e1dd197791 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -858,21 +858,3 @@ int radeon_asic_init(struct radeon_device *rdev)
         return 0;
 }
 
-/*
- * Wrapper around modesetting bits. Move to radeon_clocks.c?
- */
-int radeon_clocks_init(struct radeon_device *rdev)
-{
-        int r;
-
-        r = radeon_static_clocks_init(rdev->ddev);
-        if (r) {
-                return r;
-        }
-        DRM_INFO("Clocks initialized !\n");
-        return 0;
-}
-
-void radeon_clocks_fini(struct radeon_device *rdev)
-{
-}
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 61141981880d..ebae14c4b768 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -85,6 +85,19 @@ static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_dev
                 for (i = 0; i < num_indices; i++) {
                         gpio = &i2c_info->asGPIO_Info[i];
 
+                        /* some evergreen boards have bad data for this entry */
+                        if (ASIC_IS_DCE4(rdev)) {
+                                if ((i == 7) &&
+                                    (gpio->usClkMaskRegisterIndex == 0x1936) &&
+                                    (gpio->sucI2cId.ucAccess == 0)) {
+                                        gpio->sucI2cId.ucAccess = 0x97;
+                                        gpio->ucDataMaskShift = 8;
+                                        gpio->ucDataEnShift = 8;
+                                        gpio->ucDataY_Shift = 8;
+                                        gpio->ucDataA_Shift = 8;
+                                }
+                        }
+
                         if (gpio->sucI2cId.ucAccess == id) {
                                 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
                                 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
@@ -147,6 +160,20 @@ void radeon_atombios_i2c_init(struct radeon_device *rdev)
                 for (i = 0; i < num_indices; i++) {
                         gpio = &i2c_info->asGPIO_Info[i];
                         i2c.valid = false;
+
+                        /* some evergreen boards have bad data for this entry */
+                        if (ASIC_IS_DCE4(rdev)) {
+                                if ((i == 7) &&
+                                    (gpio->usClkMaskRegisterIndex == 0x1936) &&
+                                    (gpio->sucI2cId.ucAccess == 0)) {
+                                        gpio->sucI2cId.ucAccess = 0x97;
+                                        gpio->ucDataMaskShift = 8;
+                                        gpio->ucDataEnShift = 8;
+                                        gpio->ucDataY_Shift = 8;
+                                        gpio->ucDataA_Shift = 8;
+                                }
+                        }
+
                         i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
                         i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
                         i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 14448a740ba6..5249af8931e6 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -327,6 +327,14 @@ void radeon_get_clock_info(struct drm_device *dev)
         mpll->max_feedback_div = 0xff;
         mpll->best_vco = 0;
 
+        if (!rdev->clock.default_sclk)
+                rdev->clock.default_sclk = radeon_get_engine_clock(rdev);
+        if ((!rdev->clock.default_mclk) && rdev->asic->get_memory_clock)
+                rdev->clock.default_mclk = radeon_get_memory_clock(rdev);
+
+        rdev->pm.current_sclk = rdev->clock.default_sclk;
+        rdev->pm.current_mclk = rdev->clock.default_mclk;
+
 }
 
 /* 10 khz */
@@ -897,53 +905,3 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
         }
 }
 
-static void radeon_apply_clock_quirks(struct radeon_device *rdev)
-{
-        uint32_t tmp;
-
-        /* XXX make sure engine is idle */
-
-        if (rdev->family < CHIP_RS600) {
-                tmp = RREG32_PLL(RADEON_SCLK_CNTL);
-                if (ASIC_IS_R300(rdev) || ASIC_IS_RV100(rdev))
-                        tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
-                if ((rdev->family == CHIP_RV250)
-                    || (rdev->family == CHIP_RV280))
-                        tmp |=
-                            RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_DISP2;
-                if ((rdev->family == CHIP_RV350)
-                    || (rdev->family == CHIP_RV380))
-                        tmp |= R300_SCLK_FORCE_VAP;
-                if (rdev->family == CHIP_R420)
-                        tmp |= R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX;
-                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
-        } else if (rdev->family < CHIP_R600) {
-                tmp = RREG32_PLL(AVIVO_CP_DYN_CNTL);
-                tmp |= AVIVO_CP_FORCEON;
-                WREG32_PLL(AVIVO_CP_DYN_CNTL, tmp);
-
-                tmp = RREG32_PLL(AVIVO_E2_DYN_CNTL);
-                tmp |= AVIVO_E2_FORCEON;
-                WREG32_PLL(AVIVO_E2_DYN_CNTL, tmp);
-
-                tmp = RREG32_PLL(AVIVO_IDCT_DYN_CNTL);
-                tmp |= AVIVO_IDCT_FORCEON;
-                WREG32_PLL(AVIVO_IDCT_DYN_CNTL, tmp);
-        }
-}
-
-int radeon_static_clocks_init(struct drm_device *dev)
-{
-        struct radeon_device *rdev = dev->dev_private;
-
-        /* XXX make sure engine is idle */
-
-        if (radeon_dynclks != -1) {
-                if (radeon_dynclks) {
-                        if (rdev->asic->set_clock_gating)
-                                radeon_set_clock_gating(rdev, 1);
-                }
-        }
-        radeon_apply_clock_quirks(rdev);
-        return 0;
-}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index bd74e428bd14..a04b7a6ad95f 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -1485,6 +1485,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                         /* PowerMac8,1 ? */
                         /* imac g5 isight */
                         rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
+                } else if ((rdev->pdev->device == 0x4a48) &&
+                           (rdev->pdev->subsystem_vendor == 0x1002) &&
+                           (rdev->pdev->subsystem_device == 0x4a48)) {
+                        /* Mac X800 */
+                        rdev->mode_info.connector_table = CT_MAC_X800;
                 } else
 #endif /* CONFIG_PPC_PMAC */
 #ifdef CONFIG_PPC64
@@ -1961,6 +1966,48 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
                                             CONNECTOR_OBJECT_ID_VGA,
                                             &hpd);
                 break;
+        case CT_MAC_X800:
+                DRM_INFO("Connector Table: %d (mac x800)\n",
+                         rdev->mode_info.connector_table);
+                /* DVI - primary dac, internal tmds */
+                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
+                hpd.hpd = RADEON_HPD_1; /* ??? */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                  ATOM_DEVICE_DFP1_SUPPORT,
+                                                                  0),
+                                          ATOM_DEVICE_DFP1_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                  ATOM_DEVICE_CRT1_SUPPORT,
+                                                                  1),
+                                          ATOM_DEVICE_CRT1_SUPPORT);
+                radeon_add_legacy_connector(dev, 0,
+                                            ATOM_DEVICE_DFP1_SUPPORT |
+                                            ATOM_DEVICE_CRT1_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,
+                                            &hpd);
+                /* DVI - tv dac, dvo */
+                ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
+                hpd.hpd = RADEON_HPD_2; /* ??? */
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                  ATOM_DEVICE_DFP2_SUPPORT,
+                                                                  0),
+                                          ATOM_DEVICE_DFP2_SUPPORT);
+                radeon_add_legacy_encoder(dev,
+                                          radeon_get_encoder_enum(dev,
+                                                                  ATOM_DEVICE_CRT2_SUPPORT,
+                                                                  2),
+                                          ATOM_DEVICE_CRT2_SUPPORT);
+                radeon_add_legacy_connector(dev, 1,
+                                            ATOM_DEVICE_DFP2_SUPPORT |
+                                            ATOM_DEVICE_CRT2_SUPPORT,
+                                            DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
+                                            CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,
+                                            &hpd);
+                break;
         default:
                 DRM_INFO("Connector table: %d (invalid)\n",
                          rdev->mode_info.connector_table);
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 1a5ee392e9c7..ecc1a8fafbfd 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -481,7 +481,8 @@ static int radeon_lvds_mode_valid(struct drm_connector *connector,
         return MODE_OK;
 }
 
-static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector)
+static enum drm_connector_status
+radeon_lvds_detect(struct drm_connector *connector, bool force)
 {
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct drm_encoder *encoder = radeon_best_single_encoder(connector);
@@ -594,7 +595,8 @@ static int radeon_vga_mode_valid(struct drm_connector *connector,
         return MODE_OK;
 }
 
-static enum drm_connector_status radeon_vga_detect(struct drm_connector *connector)
+static enum drm_connector_status
+radeon_vga_detect(struct drm_connector *connector, bool force)
 {
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct drm_encoder *encoder;
@@ -691,7 +693,8 @@ static int radeon_tv_mode_valid(struct drm_connector *connector,
         return MODE_OK;
 }
 
-static enum drm_connector_status radeon_tv_detect(struct drm_connector *connector)
+static enum drm_connector_status
+radeon_tv_detect(struct drm_connector *connector, bool force)
 {
         struct drm_encoder *encoder;
         struct drm_encoder_helper_funcs *encoder_funcs;
@@ -748,7 +751,8 @@ static int radeon_dvi_get_modes(struct drm_connector *connector)
  * we have to check if this analog encoder is shared with anyone else (TV)
  * if its shared we have to set the other connector to disconnected.
  */
-static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connector)
+static enum drm_connector_status
+radeon_dvi_detect(struct drm_connector *connector, bool force)
 {
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         struct drm_encoder *encoder = NULL;
@@ -972,7 +976,8 @@ static int radeon_dp_get_modes(struct drm_connector *connector)
         return ret;
 }
 
-static enum drm_connector_status radeon_dp_detect(struct drm_connector *connector)
+static enum drm_connector_status
+radeon_dp_detect(struct drm_connector *connector, bool force)
 {
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         enum drm_connector_status ret = connector_status_disconnected;
@@ -1051,10 +1056,16 @@ radeon_add_atom_connector(struct drm_device *dev,
         uint32_t subpixel_order = SubPixelNone;
         bool shared_ddc = false;
 
-        /* fixme - tv/cv/din */
         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
                 return;
 
+        /* if the user selected tv=0 don't try and add the connector */
+        if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
+             (connector_type == DRM_MODE_CONNECTOR_Composite) ||
+             (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
+            (radeon_tv == 0))
+                return;
+
         /* see if we already added it */
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 radeon_connector = to_radeon_connector(connector);
@@ -1209,19 +1220,17 @@ radeon_add_atom_connector(struct drm_device *dev,
         case DRM_MODE_CONNECTOR_SVIDEO:
         case DRM_MODE_CONNECTOR_Composite:
         case DRM_MODE_CONNECTOR_9PinDIN:
-                if (radeon_tv == 1) {
-                        drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
-                        drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
-                        radeon_connector->dac_load_detect = true;
-                        drm_connector_attach_property(&radeon_connector->base,
-                                                      rdev->mode_info.load_detect_property,
-                                                      1);
-                        drm_connector_attach_property(&radeon_connector->base,
-                                                      rdev->mode_info.tv_std_property,
-                                                      radeon_atombios_get_tv_info(rdev));
-                        /* no HPD on analog connectors */
-                        radeon_connector->hpd.hpd = RADEON_HPD_NONE;
-                }
+                drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+                radeon_connector->dac_load_detect = true;
+                drm_connector_attach_property(&radeon_connector->base,
+                                              rdev->mode_info.load_detect_property,
+                                              1);
+                drm_connector_attach_property(&radeon_connector->base,
+                                              rdev->mode_info.tv_std_property,
+                                              radeon_atombios_get_tv_info(rdev));
+                /* no HPD on analog connectors */
+                radeon_connector->hpd.hpd = RADEON_HPD_NONE;
                 break;
         case DRM_MODE_CONNECTOR_LVDS:
                 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
@@ -1272,10 +1281,16 @@ radeon_add_legacy_connector(struct drm_device *dev,
         struct radeon_connector *radeon_connector;
         uint32_t subpixel_order = SubPixelNone;
 
-        /* fixme - tv/cv/din */
         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
                 return;
 
+        /* if the user selected tv=0 don't try and add the connector */
+        if (((connector_type == DRM_MODE_CONNECTOR_SVIDEO) ||
+             (connector_type == DRM_MODE_CONNECTOR_Composite) ||
+             (connector_type == DRM_MODE_CONNECTOR_9PinDIN)) &&
+            (radeon_tv == 0))
+                return;
+
         /* see if we already added it */
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 radeon_connector = to_radeon_connector(connector);
@@ -1347,26 +1362,24 @@ radeon_add_legacy_connector(struct drm_device *dev,
         case DRM_MODE_CONNECTOR_SVIDEO:
         case DRM_MODE_CONNECTOR_Composite:
         case DRM_MODE_CONNECTOR_9PinDIN:
-                if (radeon_tv == 1) {
-                        drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
-                        drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
-                        radeon_connector->dac_load_detect = true;
-                        /* RS400,RC410,RS480 chipset seems to report a lot
-                         * of false positive on load detect, we haven't yet
-                         * found a way to make load detect reliable on those
-                         * chipset, thus just disable it for TV.
-                         */
-                        if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
-                                radeon_connector->dac_load_detect = false;
-                        drm_connector_attach_property(&radeon_connector->base,
-                                                      rdev->mode_info.load_detect_property,
-                                                      radeon_connector->dac_load_detect);
-                        drm_connector_attach_property(&radeon_connector->base,
-                                                      rdev->mode_info.tv_std_property,
-                                                      radeon_combios_get_tv_info(rdev));
-                        /* no HPD on analog connectors */
-                        radeon_connector->hpd.hpd = RADEON_HPD_NONE;
-                }
+                drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+                drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+                radeon_connector->dac_load_detect = true;
+                /* RS400,RC410,RS480 chipset seems to report a lot
+                 * of false positive on load detect, we haven't yet
+                 * found a way to make load detect reliable on those
+                 * chipset, thus just disable it for TV.
+                 */
+                if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
+                        radeon_connector->dac_load_detect = false;
+                drm_connector_attach_property(&radeon_connector->base,
+                                              rdev->mode_info.load_detect_property,
+                                              radeon_connector->dac_load_detect);
+                drm_connector_attach_property(&radeon_connector->base,
+                                              rdev->mode_info.tv_std_property,
+                                              radeon_combios_get_tv_info(rdev));
+                /* no HPD on analog connectors */
+                radeon_connector->hpd.hpd = RADEON_HPD_NONE;
                 break;
         case DRM_MODE_CONNECTOR_LVDS:
                 drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 69b3c2291e92..256d204a6d24 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -293,30 +293,20 @@ bool radeon_card_posted(struct radeon_device *rdev)
 void radeon_update_bandwidth_info(struct radeon_device *rdev)
 {
         fixed20_12 a;
-        u32 sclk, mclk;
+        u32 sclk = rdev->pm.current_sclk;
+        u32 mclk = rdev->pm.current_mclk;
 
-        if (rdev->flags & RADEON_IS_IGP) {
-                sclk = radeon_get_engine_clock(rdev);
-                mclk = rdev->clock.default_mclk;
-
-                a.full = dfixed_const(100);
-                rdev->pm.sclk.full = dfixed_const(sclk);
-                rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
-                rdev->pm.mclk.full = dfixed_const(mclk);
-                rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
+        /* sclk/mclk in Mhz */
+        a.full = dfixed_const(100);
+        rdev->pm.sclk.full = dfixed_const(sclk);
+        rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
+        rdev->pm.mclk.full = dfixed_const(mclk);
+        rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
 
+        if (rdev->flags & RADEON_IS_IGP) {
                 a.full = dfixed_const(16);
                 /* core_bandwidth = sclk(Mhz) * 16 */
                 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
-        } else {
-                sclk = radeon_get_engine_clock(rdev);
-                mclk = radeon_get_memory_clock(rdev);
-
-                a.full = dfixed_const(100);
-                rdev->pm.sclk.full = dfixed_const(sclk);
-                rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
-                rdev->pm.mclk.full = dfixed_const(mclk);
-                rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
         }
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 6dd434ad2429..127a395f70fb 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1140,17 +1140,18 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
                         else
                                 radeon_crtc->rmx_type = RMX_OFF;
-                        src_v = crtc->mode.vdisplay;
-                        dst_v = radeon_crtc->native_mode.vdisplay;
-                        src_h = crtc->mode.hdisplay;
-                        dst_h = radeon_crtc->native_mode.vdisplay;
                         /* copy native mode */
                         memcpy(&radeon_crtc->native_mode,
                                &radeon_encoder->native_mode,
                                 sizeof(struct drm_display_mode));
+                        src_v = crtc->mode.vdisplay;
+                        dst_v = radeon_crtc->native_mode.vdisplay;
+                        src_h = crtc->mode.hdisplay;
+                        dst_h = radeon_crtc->native_mode.hdisplay;
 
                         /* fix up for overscan on hdmi */
                         if (ASIC_IS_AVIVO(rdev) &&
+                            (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 0416804d8f30..6a13ee38a5b9 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -213,7 +213,7 @@ static void post_xfer(struct i2c_adapter *i2c_adap)
 
 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
 {
-        u32 sclk = radeon_get_engine_clock(rdev);
+        u32 sclk = rdev->pm.current_sclk;
         u32 prescale = 0;
         u32 nm;
         u8 n, m, loop;
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 8f93e2b4b0c8..17a6602b5885 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -204,7 +204,7 @@ struct radeon_i2c_chan {
 
 /* mostly for macs, but really any system without connector tables */
 enum radeon_connector_table {
-        CT_NONE,
+        CT_NONE = 0,
         CT_GENERIC,
         CT_IBOOK,
         CT_POWERBOOK_EXTERNAL,
@@ -215,6 +215,7 @@ enum radeon_connector_table {
         CT_IMAC_G5_ISIGHT,
         CT_EMAC,
         CT_RN50_POWER,
+        CT_MAC_X800,
 };
 
 enum radeon_dvo_chip {
@@ -600,7 +601,6 @@ extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct d
 void radeon_enc_destroy(struct drm_encoder *encoder);
 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
 void radeon_combios_asic_init(struct drm_device *dev);
-extern int radeon_static_clocks_init(struct drm_device *dev);
 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
                                         struct drm_display_mode *mode,
                                         struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index f1c796810117..bfa59db374d2 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -905,6 +905,54 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
 }
 
+static int rv770_vram_scratch_init(struct radeon_device *rdev)
+{
+        int r;
+        u64 gpu_addr;
+
+        if (rdev->vram_scratch.robj == NULL) {
+                r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
+                                        true, RADEON_GEM_DOMAIN_VRAM,
+                                        &rdev->vram_scratch.robj);
+                if (r) {
+                        return r;
+                }
+        }
+
+        r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
+        if (unlikely(r != 0))
+                return r;
+        r = radeon_bo_pin(rdev->vram_scratch.robj,
+                          RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
+        if (r) {
+                radeon_bo_unreserve(rdev->vram_scratch.robj);
+                return r;
+        }
+        r = radeon_bo_kmap(rdev->vram_scratch.robj,
+                                (void **)&rdev->vram_scratch.ptr);
+        if (r)
+                radeon_bo_unpin(rdev->vram_scratch.robj);
+        radeon_bo_unreserve(rdev->vram_scratch.robj);
+
+        return r;
+}
+
+static void rv770_vram_scratch_fini(struct radeon_device *rdev)
+{
+        int r;
+
+        if (rdev->vram_scratch.robj == NULL) {
+                return;
+        }
+        r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
+        if (likely(r == 0)) {
+                radeon_bo_kunmap(rdev->vram_scratch.robj);
+                radeon_bo_unpin(rdev->vram_scratch.robj);
+                radeon_bo_unreserve(rdev->vram_scratch.robj);
+        }
+        radeon_bo_unref(&rdev->vram_scratch.robj);
+}
+
 int rv770_mc_init(struct radeon_device *rdev)
 {
         u32 tmp;
@@ -970,6 +1018,9 @@ static int rv770_startup(struct radeon_device *rdev)
                 if (r)
                         return r;
         }
+        r = rv770_vram_scratch_init(rdev);
+        if (r)
+                return r;
         rv770_gpu_init(rdev);
         r = r600_blit_init(rdev);
         if (r) {
@@ -1023,11 +1074,6 @@ int rv770_resume(struct radeon_device *rdev)
          */
         /* post card */
         atom_asic_init(rdev->mode_info.atom_context);
-        /* Initialize clocks */
-        r = radeon_clocks_init(rdev);
-        if (r) {
-                return r;
-        }
 
         r = rv770_startup(rdev);
         if (r) {
@@ -1118,9 +1164,6 @@ int rv770_init(struct radeon_device *rdev)
         radeon_surface_init(rdev);
         /* Initialize clocks */
         radeon_get_clock_info(rdev->ddev);
-        r = radeon_clocks_init(rdev);
-        if (r)
-                return r;
         /* Fence driver */
         r = radeon_fence_driver_init(rdev);
         if (r)
@@ -1195,9 +1238,9 @@ void rv770_fini(struct radeon_device *rdev)
         r600_irq_fini(rdev);
         radeon_irq_kms_fini(rdev);
         rv770_pcie_gart_fini(rdev);
+        rv770_vram_scratch_fini(rdev);
         radeon_gem_fini(rdev);
         radeon_fence_driver_fini(rdev);
-        radeon_clocks_fini(rdev);
         radeon_agp_fini(rdev);
         radeon_bo_fini(rdev);
         radeon_atombios_fini(rdev);
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index 2ff5cf78235f..7083b1a24df3 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -335,7 +335,8 @@ static void vmw_ldu_connector_restore(struct drm_connector *connector)
 }
 
 static enum drm_connector_status
-        vmw_ldu_connector_detect(struct drm_connector *connector)
+        vmw_ldu_connector_detect(struct drm_connector *connector,
+                                 bool force)
 {
         if (vmw_connector_to_ldu(connector)->pref_active)
                 return connector_status_connected;
@@ -516,7 +517,7 @@ static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit)
 
         drm_connector_init(dev, connector, &vmw_legacy_connector_funcs,
                            DRM_MODE_CONNECTOR_LVDS);
-        connector->status = vmw_ldu_connector_detect(connector);
+        connector->status = vmw_ldu_connector_detect(connector, true);
 
         drm_encoder_init(dev, encoder, &vmw_legacy_encoder_funcs,
                          DRM_MODE_ENCODER_LVDS);
@@ -610,7 +611,7 @@ int vmw_kms_ldu_update_layout(struct vmw_private *dev_priv, unsigned num,
                         ldu->pref_height = 600;
                         ldu->pref_active = false;
                 }
-                con->status = vmw_ldu_connector_detect(con);
+                con->status = vmw_ldu_connector_detect(con, true);
         }
 
         mutex_unlock(&dev->mode_config.mutex);