diff options
author | Adam Buchbinder <adam.buchbinder@gmail.com> | 2012-09-19 21:48:00 -0400 |
---|---|---|
committer | Jiri Kosina <jkosina@suse.cz> | 2012-11-19 08:31:35 -0500 |
commit | 48fc7f7e787dd65ffe88521bce31f4062ba273eb (patch) | |
tree | 0ee37107cf965a6b2d6d85ed3686ef1d6a622bef /drivers/gpu | |
parent | 53f698cdeb0e1af2799a515b578a779943c43482 (diff) |
Fix misspellings of "whether" in comments.
"Whether" is misspelled in various comments across the tree; this
fixes them. No code changes.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 14313ad43b76..42509492717e 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1648,7 +1648,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev) | |||
1648 | ring->wptr = 0; | 1648 | ring->wptr = 0; |
1649 | WREG32(CP_RB_WPTR, ring->wptr); | 1649 | WREG32(CP_RB_WPTR, ring->wptr); |
1650 | 1650 | ||
1651 | /* set the wb address wether it's enabled or not */ | 1651 | /* set the wb address whether it's enabled or not */ |
1652 | WREG32(CP_RB_RPTR_ADDR, | 1652 | WREG32(CP_RB_RPTR_ADDR, |
1653 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); | 1653 | ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); |
1654 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | 1654 | WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index 81e6a568c29d..cda01f808f12 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -1059,7 +1059,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) | |||
1059 | 1059 | ||
1060 | WREG32(CP_DEBUG, (1 << 27)); | 1060 | WREG32(CP_DEBUG, (1 << 27)); |
1061 | 1061 | ||
1062 | /* set the wb address wether it's enabled or not */ | 1062 | /* set the wb address whether it's enabled or not */ |
1063 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); | 1063 | WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); |
1064 | WREG32(SCRATCH_UMSK, 0xff); | 1064 | WREG32(SCRATCH_UMSK, 0xff); |
1065 | 1065 | ||
@@ -1076,7 +1076,7 @@ static int cayman_cp_resume(struct radeon_device *rdev) | |||
1076 | #endif | 1076 | #endif |
1077 | WREG32(cp_rb_cntl[i], rb_cntl); | 1077 | WREG32(cp_rb_cntl[i], rb_cntl); |
1078 | 1078 | ||
1079 | /* set the wb address wether it's enabled or not */ | 1079 | /* set the wb address whether it's enabled or not */ |
1080 | addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; | 1080 | addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; |
1081 | WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); | 1081 | WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC); |
1082 | WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); | 1082 | WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF); |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index b0db712060fb..ea4691f79ccd 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -2007,7 +2007,7 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
2007 | ring->wptr = 0; | 2007 | ring->wptr = 0; |
2008 | WREG32(CP_RB0_WPTR, ring->wptr); | 2008 | WREG32(CP_RB0_WPTR, ring->wptr); |
2009 | 2009 | ||
2010 | /* set the wb address wether it's enabled or not */ | 2010 | /* set the wb address whether it's enabled or not */ |
2011 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 2011 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
2012 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); | 2012 | WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); |
2013 | 2013 | ||
@@ -2040,7 +2040,7 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
2040 | ring->wptr = 0; | 2040 | ring->wptr = 0; |
2041 | WREG32(CP_RB1_WPTR, ring->wptr); | 2041 | WREG32(CP_RB1_WPTR, ring->wptr); |
2042 | 2042 | ||
2043 | /* set the wb address wether it's enabled or not */ | 2043 | /* set the wb address whether it's enabled or not */ |
2044 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | 2044 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
2045 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); | 2045 | WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); |
2046 | 2046 | ||
@@ -2066,7 +2066,7 @@ static int si_cp_resume(struct radeon_device *rdev) | |||
2066 | ring->wptr = 0; | 2066 | ring->wptr = 0; |
2067 | WREG32(CP_RB2_WPTR, ring->wptr); | 2067 | WREG32(CP_RB2_WPTR, ring->wptr); |
2068 | 2068 | ||
2069 | /* set the wb address wether it's enabled or not */ | 2069 | /* set the wb address whether it's enabled or not */ |
2070 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | 2070 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
2071 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); | 2071 | WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); |
2072 | 2072 | ||