diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-08-14 01:33:20 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:13:05 -0400 |
commit | 368be5f1b84b3356eb03ad2ccaf073e2fbb7fc4e (patch) | |
tree | 532b2c0d49c3cf488436726f170a48dbbc1fff9d /drivers/gpu | |
parent | ab2858928b09911b7ab21051d7fc3f973d630bff (diff) |
drm/nv50/fifo: add support for dma channel class
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | 77 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/include/core/class.h | 1 |
3 files changed, 72 insertions, 7 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c index fbcd9d04fe6b..be5c0df644db 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | |||
@@ -109,6 +109,7 @@ nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
109 | return ret; | 109 | return ret; |
110 | 110 | ||
111 | switch (nv_mclass(parent)) { | 111 | switch (nv_mclass(parent)) { |
112 | case 0x506e: | ||
112 | case 0x506f: | 113 | case 0x506f: |
113 | case 0x826e: | 114 | case 0x826e: |
114 | case 0x826f: | 115 | case 0x826f: |
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c index 452f2241783a..44a0dce07e19 100644 --- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c | |||
@@ -178,10 +178,62 @@ nv50_fifo_object_detach(struct nouveau_object *parent, int cookie) | |||
178 | } | 178 | } |
179 | 179 | ||
180 | static int | 180 | static int |
181 | nv50_fifo_chan_ctor(struct nouveau_object *parent, | 181 | nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, |
182 | struct nouveau_object *engine, | 182 | struct nouveau_object *engine, |
183 | struct nouveau_oclass *oclass, void *data, u32 size, | 183 | struct nouveau_oclass *oclass, void *data, u32 size, |
184 | struct nouveau_object **pobject) | 184 | struct nouveau_object **pobject) |
185 | { | ||
186 | struct nouveau_bar *bar = nouveau_bar(parent); | ||
187 | struct nv50_fifo_base *base = (void *)parent; | ||
188 | struct nv50_fifo_chan *chan; | ||
189 | struct nv03_channel_dma_class *args = data; | ||
190 | int ret; | ||
191 | |||
192 | if (size < sizeof(*args)) | ||
193 | return -EINVAL; | ||
194 | |||
195 | ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, | ||
196 | 0x2000, args->pushbuf, | ||
197 | (1 << NVDEV_ENGINE_DMAOBJ) | | ||
198 | (1 << NVDEV_ENGINE_SW) | | ||
199 | (1 << NVDEV_ENGINE_GR) | | ||
200 | (1 << NVDEV_ENGINE_MPEG), &chan); | ||
201 | *pobject = nv_object(chan); | ||
202 | if (ret) | ||
203 | return ret; | ||
204 | |||
205 | nv_parent(chan)->context_attach = nv50_fifo_context_attach; | ||
206 | nv_parent(chan)->context_detach = nv50_fifo_context_detach; | ||
207 | nv_parent(chan)->object_attach = nv50_fifo_object_attach; | ||
208 | nv_parent(chan)->object_detach = nv50_fifo_object_detach; | ||
209 | |||
210 | ret = nouveau_ramht_new(parent, parent, 0x8000, 16, &chan->ramht); | ||
211 | if (ret) | ||
212 | return ret; | ||
213 | |||
214 | nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset)); | ||
215 | nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset)); | ||
216 | nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset)); | ||
217 | nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset)); | ||
218 | nv_wo32(base->ramfc, 0x3c, 0x003f6078); | ||
219 | nv_wo32(base->ramfc, 0x44, 0x01003fff); | ||
220 | nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); | ||
221 | nv_wo32(base->ramfc, 0x4c, 0xffffffff); | ||
222 | nv_wo32(base->ramfc, 0x60, 0x7fffffff); | ||
223 | nv_wo32(base->ramfc, 0x78, 0x00000000); | ||
224 | nv_wo32(base->ramfc, 0x7c, 0x30000001); | ||
225 | nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | | ||
226 | (4 << 24) /* SEARCH_FULL */ | | ||
227 | (chan->ramht->base.node->offset >> 4)); | ||
228 | bar->flush(bar); | ||
229 | return 0; | ||
230 | } | ||
231 | |||
232 | static int | ||
233 | nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, | ||
234 | struct nouveau_object *engine, | ||
235 | struct nouveau_oclass *oclass, void *data, u32 size, | ||
236 | struct nouveau_object **pobject) | ||
185 | { | 237 | { |
186 | struct nv50_channel_ind_class *args = data; | 238 | struct nv50_channel_ind_class *args = data; |
187 | struct nouveau_bar *bar = nouveau_bar(parent); | 239 | struct nouveau_bar *bar = nouveau_bar(parent); |
@@ -273,8 +325,18 @@ nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) | |||
273 | } | 325 | } |
274 | 326 | ||
275 | static struct nouveau_ofuncs | 327 | static struct nouveau_ofuncs |
276 | nv50_fifo_ofuncs = { | 328 | nv50_fifo_ofuncs_dma = { |
277 | .ctor = nv50_fifo_chan_ctor, | 329 | .ctor = nv50_fifo_chan_ctor_dma, |
330 | .dtor = nv50_fifo_chan_dtor, | ||
331 | .init = nv50_fifo_chan_init, | ||
332 | .fini = nv50_fifo_chan_fini, | ||
333 | .rd32 = _nouveau_fifo_channel_rd32, | ||
334 | .wr32 = _nouveau_fifo_channel_wr32, | ||
335 | }; | ||
336 | |||
337 | static struct nouveau_ofuncs | ||
338 | nv50_fifo_ofuncs_ind = { | ||
339 | .ctor = nv50_fifo_chan_ctor_ind, | ||
278 | .dtor = nv50_fifo_chan_dtor, | 340 | .dtor = nv50_fifo_chan_dtor, |
279 | .init = nv50_fifo_chan_init, | 341 | .init = nv50_fifo_chan_init, |
280 | .fini = nv50_fifo_chan_fini, | 342 | .fini = nv50_fifo_chan_fini, |
@@ -284,7 +346,8 @@ nv50_fifo_ofuncs = { | |||
284 | 346 | ||
285 | static struct nouveau_oclass | 347 | static struct nouveau_oclass |
286 | nv50_fifo_sclass[] = { | 348 | nv50_fifo_sclass[] = { |
287 | { 0x506f, &nv50_fifo_ofuncs }, | 349 | { 0x506e, &nv50_fifo_ofuncs_dma }, |
350 | { 0x506f, &nv50_fifo_ofuncs_ind }, | ||
288 | {} | 351 | {} |
289 | }; | 352 | }; |
290 | 353 | ||
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h index 36759159db05..b0e1948f4e71 100644 --- a/drivers/gpu/drm/nouveau/core/include/core/class.h +++ b/drivers/gpu/drm/nouveau/core/include/core/class.h | |||
@@ -55,6 +55,7 @@ struct nv_dma_class { | |||
55 | * 006e: NV10_CHANNEL_DMA | 55 | * 006e: NV10_CHANNEL_DMA |
56 | * 176e: NV17_CHANNEL_DMA | 56 | * 176e: NV17_CHANNEL_DMA |
57 | * 406e: NV40_CHANNEL_DMA | 57 | * 406e: NV40_CHANNEL_DMA |
58 | * 506e: NV50_CHANNEL_DMA | ||
58 | * 826e: NV84_CHANNEL_DMA | 59 | * 826e: NV84_CHANNEL_DMA |
59 | */ | 60 | */ |
60 | 61 | ||