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authorImre Deak <imre.deak@intel.com>2013-05-21 13:03:20 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-05-22 07:51:26 -0400
commit3598706b52cb45ba0a9e8aa99ce5ac59140f2b8b (patch)
tree2dfeb6b1e1f59b39cfbd5cc20477efc2101b3c7b /drivers/gpu
parente054cc3937a4a58e77870d4c922a7b21824b610a (diff)
drm/i915: avoid premature DP AUX timeouts
During DP AUX communication we might time out 1 jiffy too early, because the calculated expiry jiffy value is one less than needed. This is only one reason for false DP AUX timeouts. For a complete solution we also need the following fix, which is now queued for mainline: http://marc.info/?l=linux-kernel&m=136748515710837&w=2 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64133 Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c3
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3d704b706a8d..70789b1b5642 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -303,7 +303,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
304 if (has_aux_irq) 304 if (has_aux_irq)
305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10)); 306 msecs_to_jiffies_timeout(10));
307 else 307 else
308 done = wait_for_atomic(C, 10) == 0; 308 done = wait_for_atomic(C, 10) == 0;
309 if (!done) 309 if (!done)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 98cd85352d9a..639fe192997c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -263,7 +263,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
263 /* Important: The hw handles only the first bit, so set only one! */ 263 /* Important: The hw handles only the first bit, so set only one! */
264 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); 264 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
265 265
266 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10); 266 ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
267 msecs_to_jiffies_timeout(10));
267 268
268 I915_WRITE(GMBUS4 + reg_offset, 0); 269 I915_WRITE(GMBUS4 + reg_offset, 0);
269 270