drm/radeon: update line buffer allocation for dce6

We need to allocate line buffer to each display when
setting up the watermarks.  Failure to do so can lead
to a blank screen.  This fixes blank screen problems
on dce6 asics.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=64850

Based on an initial fix from:
Jay Cornwall <jay.cornwall@amd.com>

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

2 files changed, 23 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 0b4e979b2cbf..89393ed593fa 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1711,7 +1711,8 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
                                    struct drm_display_mode *mode,
                                    struct drm_display_mode *other_mode)
 {
-        u32 tmp;
+        u32 tmp, buffer_alloc, i;
+        u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
         /*
          * Line Buffer Setup
          * There are 3 line buffers, each one shared by 2 display controllers.
@@ -1726,16 +1727,30 @@ static u32 dce6_line_buffer_adjust(struct radeon_device *rdev,
          * non-linked crtcs for maximum line buffer allocation.
          */
         if (radeon_crtc->base.enabled && mode) {
-                if (other_mode)
+                if (other_mode) {
                         tmp = 0; /* 1/2 */
-                else
+                        buffer_alloc = 1;
+                } else {
                         tmp = 2; /* whole */
-        } else
+                        buffer_alloc = 2;
+                }
+        } else {
                 tmp = 0;
+                buffer_alloc = 0;
+        }
 
         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset,
                DC_LB_MEMORY_CONFIG(tmp));
 
+        WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
+               DMIF_BUFFERS_ALLOCATED(buffer_alloc));
+        for (i = 0; i < rdev->usec_timeout; i++) {
+                if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
+                    DMIF_BUFFERS_ALLOCATED_COMPLETED)
+                        break;
+                udelay(1);
+        }
+
         if (radeon_crtc->base.enabled && mode) {
                 switch (tmp) {
                 case 0:
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 91dae16fddc4..52d2ab6b67a0 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -282,6 +282,10 @@
 
 #define DMIF_ADDR_CALC                                  0xC00
 
+#define PIPE0_DMIF_BUFFER_CONTROL                         0x0ca0
+#       define DMIF_BUFFERS_ALLOCATED(x)                  ((x) << 0)
+#       define DMIF_BUFFERS_ALLOCATED_COMPLETED           (1 << 4)
+
 #define SRBM_STATUS                                     0xE50
 #define         GRBM_RQ_PENDING                         (1 << 5)
 #define         VMC_BUSY                                (1 << 8)