diff options
author | Damien Lespiau <damien.lespiau@intel.com> | 2012-10-19 12:55:41 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-19 14:30:51 -0400 |
commit | 231e54f6391ccc7a3377df5bbaff3800822def1d (patch) | |
tree | b9af38073ae8baca34f07ad836433ea57c989efa /drivers/gpu | |
parent | 36ec8f877481449bdfa072e6adf2060869e2b970 (diff) |
drm/i915: Consolidate ILK_DSPCLK_GATE and PCH_DSPCLK_GATE
Register 0x42020 was defined twice under the names PCH_DSPCLK_GATE_D and
ILK_DSPCLK_GATE. This patch consolidate the 2 sets of defines in one.
The transforms done are:
PCH_DSPCLK_GATE_D -> ILK_DSPCLK_GATE_D
ILK_DSPCLK_GATE -> ILK_DSPCLK_GATE_D
DPARBUNIT_CLOCK_GATE_DISABLE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
ILK_DPARB_CLK_GATE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
DPFDUNIT_CLOCK_GATE_DISABLE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
ILK_DPFD_CLK_GATE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
ILK_CLK_FBC -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
DPFCRUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
ILK_DPFC_DIS1 -> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
DPFCUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
ILK_DPFC_DIS2 -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
We have a VHRUNIT_CLOCK_GATE_DISABLE define for the pre-ILK DSPCLK_GATE_D.
Even if the same bit is used in ILK_DSPCLK_GATE_D, other bits in the
register change, so I went with re-defining it, well more precisely rename
IVB_VRHUNIT_CLK_GATE, which is not specific to IVB+. So:
IVB_VRHUNIT_CLK_GATE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE
VHRUNIT_CLOCK_GATE_DISABLE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE (ILK+ code)
This commit is only a renaming commit, further commits will clean up the
logic.
v2: Rename bit 5 and 7 to _ENABLE as setting them to 1 enables clock
gating on their respective units, contrary to all of the other bits
(Paulo Zanoni)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 22 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 52 |
2 files changed, 33 insertions, 41 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c31ee5bd1a56..08c51ab43c50 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -3248,12 +3248,6 @@ | |||
3248 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 | 3248 | #define DISPLAY_PORT_PLL_BIOS_1 0x46010 |
3249 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 | 3249 | #define DISPLAY_PORT_PLL_BIOS_2 0x46014 |
3250 | 3250 | ||
3251 | #define PCH_DSPCLK_GATE_D 0x42020 | ||
3252 | # define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) | ||
3253 | # define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | ||
3254 | # define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) | ||
3255 | # define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) | ||
3256 | |||
3257 | #define PCH_3DCGDIS0 0x46020 | 3251 | #define PCH_3DCGDIS0 0x46020 |
3258 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) | 3252 | # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) |
3259 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) | 3253 | # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) |
@@ -3425,15 +3419,13 @@ | |||
3425 | #define ILK_HDCP_DISABLE (1<<25) | 3419 | #define ILK_HDCP_DISABLE (1<<25) |
3426 | #define ILK_eDP_A_DISABLE (1<<24) | 3420 | #define ILK_eDP_A_DISABLE (1<<24) |
3427 | #define ILK_DESKTOP (1<<23) | 3421 | #define ILK_DESKTOP (1<<23) |
3428 | #define ILK_DSPCLK_GATE 0x42020 | 3422 | |
3429 | #define IVB_VRHUNIT_CLK_GATE (1<<28) | 3423 | #define ILK_DSPCLK_GATE_D 0x42020 |
3430 | #define ILK_DPARB_CLK_GATE (1<<5) | 3424 | #define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) |
3431 | #define ILK_DPFD_CLK_GATE (1<<7) | 3425 | #define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9) |
3432 | 3426 | #define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8) | |
3433 | /* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */ | 3427 | #define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7) |
3434 | #define ILK_CLK_FBC (1<<7) | 3428 | #define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5) |
3435 | #define ILK_DPFC_DIS1 (1<<8) | ||
3436 | #define ILK_DPFC_DIS2 (1<<9) | ||
3437 | 3429 | ||
3438 | #define IVB_CHICKEN3 0x4200c | 3430 | #define IVB_CHICKEN3 0x4200c |
3439 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) | 3431 | # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 568c98dc5b14..d2a226a7658c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -3295,14 +3295,14 @@ void intel_enable_gt_powersave(struct drm_device *dev) | |||
3295 | static void ironlake_init_clock_gating(struct drm_device *dev) | 3295 | static void ironlake_init_clock_gating(struct drm_device *dev) |
3296 | { | 3296 | { |
3297 | struct drm_i915_private *dev_priv = dev->dev_private; | 3297 | struct drm_i915_private *dev_priv = dev->dev_private; |
3298 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | 3298 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3299 | 3299 | ||
3300 | /* Required for FBC */ | 3300 | /* Required for FBC */ |
3301 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | 3301 | dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
3302 | DPFCRUNIT_CLOCK_GATE_DISABLE | | 3302 | ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3303 | DPFDUNIT_CLOCK_GATE_DISABLE; | 3303 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
3304 | /* Required for CxSR */ | 3304 | /* Required for CxSR */ |
3305 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | 3305 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
3306 | 3306 | ||
3307 | I915_WRITE(PCH_3DCGDIS0, | 3307 | I915_WRITE(PCH_3DCGDIS0, |
3308 | MARIUNIT_CLOCK_GATE_DISABLE | | 3308 | MARIUNIT_CLOCK_GATE_DISABLE | |
@@ -3310,7 +3310,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev) | |||
3310 | I915_WRITE(PCH_3DCGDIS1, | 3310 | I915_WRITE(PCH_3DCGDIS1, |
3311 | VFMUNIT_CLOCK_GATE_DISABLE); | 3311 | VFMUNIT_CLOCK_GATE_DISABLE); |
3312 | 3312 | ||
3313 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | 3313 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3314 | 3314 | ||
3315 | /* | 3315 | /* |
3316 | * According to the spec the following bits should be set in | 3316 | * According to the spec the following bits should be set in |
@@ -3322,9 +3322,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev) | |||
3322 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 3322 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3323 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | 3323 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
3324 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | 3324 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
3325 | I915_WRITE(ILK_DSPCLK_GATE, | 3325 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3326 | (I915_READ(ILK_DSPCLK_GATE) | | 3326 | (I915_READ(ILK_DSPCLK_GATE_D) | |
3327 | ILK_DPARB_CLK_GATE)); | 3327 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE)); |
3328 | I915_WRITE(DISP_ARB_CTL, | 3328 | I915_WRITE(DISP_ARB_CTL, |
3329 | (I915_READ(DISP_ARB_CTL) | | 3329 | (I915_READ(DISP_ARB_CTL) | |
3330 | DISP_FBC_WM_DIS)); | 3330 | DISP_FBC_WM_DIS)); |
@@ -3346,11 +3346,11 @@ static void ironlake_init_clock_gating(struct drm_device *dev) | |||
3346 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 3346 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3347 | I915_READ(ILK_DISPLAY_CHICKEN2) | | 3347 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3348 | ILK_DPARB_GATE); | 3348 | ILK_DPARB_GATE); |
3349 | I915_WRITE(ILK_DSPCLK_GATE, | 3349 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3350 | I915_READ(ILK_DSPCLK_GATE) | | 3350 | I915_READ(ILK_DSPCLK_GATE_D) | |
3351 | ILK_DPFC_DIS1 | | 3351 | ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3352 | ILK_DPFC_DIS2 | | 3352 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
3353 | ILK_CLK_FBC); | 3353 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
3354 | } | 3354 | } |
3355 | 3355 | ||
3356 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 3356 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
@@ -3365,9 +3365,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) | |||
3365 | { | 3365 | { |
3366 | struct drm_i915_private *dev_priv = dev->dev_private; | 3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
3367 | int pipe; | 3367 | int pipe; |
3368 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | 3368 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3369 | 3369 | ||
3370 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | 3370 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3371 | 3371 | ||
3372 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 3372 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3373 | I915_READ(ILK_DISPLAY_CHICKEN2) | | 3373 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
@@ -3422,10 +3422,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) | |||
3422 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | 3422 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3423 | I915_READ(ILK_DISPLAY_CHICKEN2) | | 3423 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
3424 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | 3424 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
3425 | I915_WRITE(ILK_DSPCLK_GATE, | 3425 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3426 | I915_READ(ILK_DSPCLK_GATE) | | 3426 | I915_READ(ILK_DSPCLK_GATE_D) | |
3427 | ILK_DPARB_CLK_GATE | | 3427 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
3428 | ILK_DPFD_CLK_GATE); | 3428 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
3429 | 3429 | ||
3430 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | | 3430 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3431 | GEN6_MBCTL_ENABLE_BOOT_FETCH); | 3431 | GEN6_MBCTL_ENABLE_BOOT_FETCH); |
@@ -3507,16 +3507,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) | |||
3507 | { | 3507 | { |
3508 | struct drm_i915_private *dev_priv = dev->dev_private; | 3508 | struct drm_i915_private *dev_priv = dev->dev_private; |
3509 | int pipe; | 3509 | int pipe; |
3510 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | 3510 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3511 | uint32_t snpcr; | 3511 | uint32_t snpcr; |
3512 | 3512 | ||
3513 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | 3513 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3514 | 3514 | ||
3515 | I915_WRITE(WM3_LP_ILK, 0); | 3515 | I915_WRITE(WM3_LP_ILK, 0); |
3516 | I915_WRITE(WM2_LP_ILK, 0); | 3516 | I915_WRITE(WM2_LP_ILK, 0); |
3517 | I915_WRITE(WM1_LP_ILK, 0); | 3517 | I915_WRITE(WM1_LP_ILK, 0); |
3518 | 3518 | ||
3519 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); | 3519 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3520 | 3520 | ||
3521 | /* WaDisableEarlyCull */ | 3521 | /* WaDisableEarlyCull */ |
3522 | I915_WRITE(_3D_CHICKEN3, | 3522 | I915_WRITE(_3D_CHICKEN3, |
@@ -3589,15 +3589,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev) | |||
3589 | { | 3589 | { |
3590 | struct drm_i915_private *dev_priv = dev->dev_private; | 3590 | struct drm_i915_private *dev_priv = dev->dev_private; |
3591 | int pipe; | 3591 | int pipe; |
3592 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | 3592 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
3593 | 3593 | ||
3594 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | 3594 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3595 | 3595 | ||
3596 | I915_WRITE(WM3_LP_ILK, 0); | 3596 | I915_WRITE(WM3_LP_ILK, 0); |
3597 | I915_WRITE(WM2_LP_ILK, 0); | 3597 | I915_WRITE(WM2_LP_ILK, 0); |
3598 | I915_WRITE(WM1_LP_ILK, 0); | 3598 | I915_WRITE(WM1_LP_ILK, 0); |
3599 | 3599 | ||
3600 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); | 3600 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
3601 | 3601 | ||
3602 | /* WaDisableEarlyCull */ | 3602 | /* WaDisableEarlyCull */ |
3603 | I915_WRITE(_3D_CHICKEN3, | 3603 | I915_WRITE(_3D_CHICKEN3, |