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authorAlex Deucher <alexdeucher@gmail.com>2011-01-27 17:01:52 -0500
committerDave Airlie <airlied@gmail.com>2011-01-27 19:59:31 -0500
commit1e644d6dce366a7bae22484f60133b61ba322911 (patch)
tree12eb2e66e98ba7cef9d0464a1783d9559638d7b9 /drivers/gpu
parentdca0d6129f3ec77bcf42ce85bcd64c87e5cf0c04 (diff)
drm/radeon/kms: re-emit full context state for evergreen blits
clear state doesn't seem to work properly in some cases Fixes hangs in heavy 3D on some evergreen cards reported on IRC. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=33381 possibly others. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@gmail.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c39
1 files changed, 33 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index b758dc7f2f2c..d4d4db49a8b8 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -232,7 +232,7 @@ draw_auto(struct radeon_device *rdev)
232 232
233} 233}
234 234
235/* emits 30 */ 235/* emits 34 */
236static void 236static void
237set_default_state(struct radeon_device *rdev) 237set_default_state(struct radeon_device *rdev)
238{ 238{
@@ -245,6 +245,8 @@ set_default_state(struct radeon_device *rdev)
245 int num_hs_threads, num_ls_threads; 245 int num_hs_threads, num_ls_threads;
246 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; 246 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
247 int num_hs_stack_entries, num_ls_stack_entries; 247 int num_hs_stack_entries, num_ls_stack_entries;
248 u64 gpu_addr;
249 int dwords;
248 250
249 switch (rdev->family) { 251 switch (rdev->family) {
250 case CHIP_CEDAR: 252 case CHIP_CEDAR:
@@ -497,6 +499,14 @@ set_default_state(struct radeon_device *rdev)
497 radeon_ring_write(rdev, 0x00000000); 499 radeon_ring_write(rdev, 0x00000000);
498 radeon_ring_write(rdev, 0x00000000); 500 radeon_ring_write(rdev, 0x00000000);
499 501
502 /* emit an IB pointing at default state */
503 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
504 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
505 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
506 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
507 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
508 radeon_ring_write(rdev, dwords);
509
500} 510}
501 511
502static inline uint32_t i2f(uint32_t input) 512static inline uint32_t i2f(uint32_t input)
@@ -527,8 +537,10 @@ static inline uint32_t i2f(uint32_t input)
527int evergreen_blit_init(struct radeon_device *rdev) 537int evergreen_blit_init(struct radeon_device *rdev)
528{ 538{
529 u32 obj_size; 539 u32 obj_size;
530 int r; 540 int r, dwords;
531 void *ptr; 541 void *ptr;
542 u32 packet2s[16];
543 int num_packet2s = 0;
532 544
533 /* pin copy shader into vram if already initialized */ 545 /* pin copy shader into vram if already initialized */
534 if (rdev->r600_blit.shader_obj) 546 if (rdev->r600_blit.shader_obj)
@@ -536,8 +548,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
536 548
537 mutex_init(&rdev->r600_blit.mutex); 549 mutex_init(&rdev->r600_blit.mutex);
538 rdev->r600_blit.state_offset = 0; 550 rdev->r600_blit.state_offset = 0;
539 rdev->r600_blit.state_len = 0; 551
540 obj_size = 0; 552 rdev->r600_blit.state_len = evergreen_default_size;
553
554 dwords = rdev->r600_blit.state_len;
555 while (dwords & 0xf) {
556 packet2s[num_packet2s++] = PACKET2(0);
557 dwords++;
558 }
559
560 obj_size = dwords * 4;
561 obj_size = ALIGN(obj_size, 256);
541 562
542 rdev->r600_blit.vs_offset = obj_size; 563 rdev->r600_blit.vs_offset = obj_size;
543 obj_size += evergreen_vs_size * 4; 564 obj_size += evergreen_vs_size * 4;
@@ -567,6 +588,12 @@ int evergreen_blit_init(struct radeon_device *rdev)
567 return r; 588 return r;
568 } 589 }
569 590
591 memcpy_toio(ptr + rdev->r600_blit.state_offset,
592 evergreen_default_state, rdev->r600_blit.state_len * 4);
593
594 if (num_packet2s)
595 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
596 packet2s, num_packet2s * 4);
570 memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4); 597 memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
571 memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4); 598 memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
572 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 599 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
@@ -652,7 +679,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
652 /* calculate number of loops correctly */ 679 /* calculate number of loops correctly */
653 ring_size = num_loops * dwords_per_loop; 680 ring_size = num_loops * dwords_per_loop;
654 /* set default + shaders */ 681 /* set default + shaders */
655 ring_size += 46; /* shaders + def state */ 682 ring_size += 50; /* shaders + def state */
656 ring_size += 10; /* fence emit for VB IB */ 683 ring_size += 10; /* fence emit for VB IB */
657 ring_size += 5; /* done copy */ 684 ring_size += 5; /* done copy */
658 ring_size += 10; /* fence emit for done copy */ 685 ring_size += 10; /* fence emit for done copy */
@@ -660,7 +687,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
660 if (r) 687 if (r)
661 return r; 688 return r;
662 689
663 set_default_state(rdev); /* 30 */ 690 set_default_state(rdev); /* 34 */
664 set_shaders(rdev); /* 16 */ 691 set_shaders(rdev); /* 16 */
665 return 0; 692 return 0;
666} 693}