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authorAlex Deucher <alexander.deucher@amd.com>2012-02-23 17:53:40 -0500
committerDave Airlie <airlied@redhat.com>2012-02-27 09:49:24 -0500
commit0f9e006c9a8b264c1a391a58142f6c0e777e63c2 (patch)
tree68fe22075ce561493261c5bbb2130ea9227d9418 /drivers/gpu
parent901ea57dc4a2792900497172fa41358f9b2f67c3 (diff)
drm/radeon/kms: reorganize page flip callbacks
tidy up the radeon_asic struct. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h14
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c136
2 files changed, 93 insertions, 57 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f1a369d07e87..f627ac935d7f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1205,9 +1205,11 @@ struct radeon_asic {
1205 void (*pm_init_profile)(struct radeon_device *rdev); 1205 void (*pm_init_profile)(struct radeon_device *rdev);
1206 void (*pm_get_dynpm_state)(struct radeon_device *rdev); 1206 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
1207 /* pageflipping */ 1207 /* pageflipping */
1208 void (*pre_page_flip)(struct radeon_device *rdev, int crtc); 1208 struct {
1209 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); 1209 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1210 void (*post_page_flip)(struct radeon_device *rdev, int crtc); 1210 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1211 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
1212 } pflip;
1211 /* wait for vblank */ 1213 /* wait for vblank */
1212 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); 1214 void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
1213 /* wait for mc_idle */ 1215 /* wait for mc_idle */
@@ -1697,9 +1699,9 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1697#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) 1699#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1698#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) 1700#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1699#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) 1701#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1700#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) 1702#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pflip.pre_page_flip((rdev), (crtc))
1701#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) 1703#define radeon_page_flip(rdev, crtc, base) rdev->asic->pflip.page_flip((rdev), (crtc), (base))
1702#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) 1704#define radeon_post_page_flip(rdev, crtc) rdev->asic->pflip.post_page_flip((rdev), (crtc))
1703#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->wait_for_vblank((rdev), (crtc)) 1705#define radeon_wait_for_vblank(rdev, crtc) rdev->asic->wait_for_vblank((rdev), (crtc))
1704#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev)) 1706#define radeon_mc_wait_for_idle(rdev) rdev->asic->mc_wait_for_idle((rdev))
1705 1707
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index b780edbf3af6..839b18831699 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -177,9 +177,11 @@ static struct radeon_asic r100_asic = {
177 .pm_finish = &r100_pm_finish, 177 .pm_finish = &r100_pm_finish,
178 .pm_init_profile = &r100_pm_init_profile, 178 .pm_init_profile = &r100_pm_init_profile,
179 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 179 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
180 .pre_page_flip = &r100_pre_page_flip, 180 .pflip = {
181 .page_flip = &r100_page_flip, 181 .pre_page_flip = &r100_pre_page_flip,
182 .post_page_flip = &r100_post_page_flip, 182 .page_flip = &r100_page_flip,
183 .post_page_flip = &r100_post_page_flip,
184 },
183 .wait_for_vblank = &r100_wait_for_vblank, 185 .wait_for_vblank = &r100_wait_for_vblank,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle, 186 .mc_wait_for_idle = &r100_mc_wait_for_idle,
185}; 187};
@@ -232,9 +234,11 @@ static struct radeon_asic r200_asic = {
232 .pm_finish = &r100_pm_finish, 234 .pm_finish = &r100_pm_finish,
233 .pm_init_profile = &r100_pm_init_profile, 235 .pm_init_profile = &r100_pm_init_profile,
234 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 236 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
235 .pre_page_flip = &r100_pre_page_flip, 237 .pflip = {
236 .page_flip = &r100_page_flip, 238 .pre_page_flip = &r100_pre_page_flip,
237 .post_page_flip = &r100_post_page_flip, 239 .page_flip = &r100_page_flip,
240 .post_page_flip = &r100_post_page_flip,
241 },
238 .wait_for_vblank = &r100_wait_for_vblank, 242 .wait_for_vblank = &r100_wait_for_vblank,
239 .mc_wait_for_idle = &r100_mc_wait_for_idle, 243 .mc_wait_for_idle = &r100_mc_wait_for_idle,
240}; 244};
@@ -288,9 +292,11 @@ static struct radeon_asic r300_asic = {
288 .pm_finish = &r100_pm_finish, 292 .pm_finish = &r100_pm_finish,
289 .pm_init_profile = &r100_pm_init_profile, 293 .pm_init_profile = &r100_pm_init_profile,
290 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 294 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
291 .pre_page_flip = &r100_pre_page_flip, 295 .pflip = {
292 .page_flip = &r100_page_flip, 296 .pre_page_flip = &r100_pre_page_flip,
293 .post_page_flip = &r100_post_page_flip, 297 .page_flip = &r100_page_flip,
298 .post_page_flip = &r100_post_page_flip,
299 },
294 .wait_for_vblank = &r100_wait_for_vblank, 300 .wait_for_vblank = &r100_wait_for_vblank,
295 .mc_wait_for_idle = &r300_mc_wait_for_idle, 301 .mc_wait_for_idle = &r300_mc_wait_for_idle,
296}; 302};
@@ -343,9 +349,11 @@ static struct radeon_asic r300_asic_pcie = {
343 .pm_finish = &r100_pm_finish, 349 .pm_finish = &r100_pm_finish,
344 .pm_init_profile = &r100_pm_init_profile, 350 .pm_init_profile = &r100_pm_init_profile,
345 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 351 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
346 .pre_page_flip = &r100_pre_page_flip, 352 .pflip = {
347 .page_flip = &r100_page_flip, 353 .pre_page_flip = &r100_pre_page_flip,
348 .post_page_flip = &r100_post_page_flip, 354 .page_flip = &r100_page_flip,
355 .post_page_flip = &r100_post_page_flip,
356 },
349 .wait_for_vblank = &r100_wait_for_vblank, 357 .wait_for_vblank = &r100_wait_for_vblank,
350 .mc_wait_for_idle = &r300_mc_wait_for_idle, 358 .mc_wait_for_idle = &r300_mc_wait_for_idle,
351}; 359};
@@ -399,9 +407,11 @@ static struct radeon_asic r420_asic = {
399 .pm_finish = &r100_pm_finish, 407 .pm_finish = &r100_pm_finish,
400 .pm_init_profile = &r420_pm_init_profile, 408 .pm_init_profile = &r420_pm_init_profile,
401 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 409 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
402 .pre_page_flip = &r100_pre_page_flip, 410 .pflip = {
403 .page_flip = &r100_page_flip, 411 .pre_page_flip = &r100_pre_page_flip,
404 .post_page_flip = &r100_post_page_flip, 412 .page_flip = &r100_page_flip,
413 .post_page_flip = &r100_post_page_flip,
414 },
405 .wait_for_vblank = &r100_wait_for_vblank, 415 .wait_for_vblank = &r100_wait_for_vblank,
406 .mc_wait_for_idle = &r300_mc_wait_for_idle, 416 .mc_wait_for_idle = &r300_mc_wait_for_idle,
407}; 417};
@@ -455,9 +465,11 @@ static struct radeon_asic rs400_asic = {
455 .pm_finish = &r100_pm_finish, 465 .pm_finish = &r100_pm_finish,
456 .pm_init_profile = &r100_pm_init_profile, 466 .pm_init_profile = &r100_pm_init_profile,
457 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 467 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
458 .pre_page_flip = &r100_pre_page_flip, 468 .pflip = {
459 .page_flip = &r100_page_flip, 469 .pre_page_flip = &r100_pre_page_flip,
460 .post_page_flip = &r100_post_page_flip, 470 .page_flip = &r100_page_flip,
471 .post_page_flip = &r100_post_page_flip,
472 },
461 .wait_for_vblank = &r100_wait_for_vblank, 473 .wait_for_vblank = &r100_wait_for_vblank,
462 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 474 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
463}; 475};
@@ -511,9 +523,11 @@ static struct radeon_asic rs600_asic = {
511 .pm_finish = &rs600_pm_finish, 523 .pm_finish = &rs600_pm_finish,
512 .pm_init_profile = &r420_pm_init_profile, 524 .pm_init_profile = &r420_pm_init_profile,
513 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 525 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
514 .pre_page_flip = &rs600_pre_page_flip, 526 .pflip = {
515 .page_flip = &rs600_page_flip, 527 .pre_page_flip = &rs600_pre_page_flip,
516 .post_page_flip = &rs600_post_page_flip, 528 .page_flip = &rs600_page_flip,
529 .post_page_flip = &rs600_post_page_flip,
530 },
517 .wait_for_vblank = &avivo_wait_for_vblank, 531 .wait_for_vblank = &avivo_wait_for_vblank,
518 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 532 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
519}; 533};
@@ -567,9 +581,11 @@ static struct radeon_asic rs690_asic = {
567 .pm_finish = &rs600_pm_finish, 581 .pm_finish = &rs600_pm_finish,
568 .pm_init_profile = &r420_pm_init_profile, 582 .pm_init_profile = &r420_pm_init_profile,
569 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 583 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
570 .pre_page_flip = &rs600_pre_page_flip, 584 .pflip = {
571 .page_flip = &rs600_page_flip, 585 .pre_page_flip = &rs600_pre_page_flip,
572 .post_page_flip = &rs600_post_page_flip, 586 .page_flip = &rs600_page_flip,
587 .post_page_flip = &rs600_post_page_flip,
588 },
573 .wait_for_vblank = &avivo_wait_for_vblank, 589 .wait_for_vblank = &avivo_wait_for_vblank,
574 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 590 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
575}; 591};
@@ -623,9 +639,11 @@ static struct radeon_asic rv515_asic = {
623 .pm_finish = &rs600_pm_finish, 639 .pm_finish = &rs600_pm_finish,
624 .pm_init_profile = &r420_pm_init_profile, 640 .pm_init_profile = &r420_pm_init_profile,
625 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 641 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
626 .pre_page_flip = &rs600_pre_page_flip, 642 .pflip = {
627 .page_flip = &rs600_page_flip, 643 .pre_page_flip = &rs600_pre_page_flip,
628 .post_page_flip = &rs600_post_page_flip, 644 .page_flip = &rs600_page_flip,
645 .post_page_flip = &rs600_post_page_flip,
646 },
629 .wait_for_vblank = &avivo_wait_for_vblank, 647 .wait_for_vblank = &avivo_wait_for_vblank,
630 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 648 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
631}; 649};
@@ -679,9 +697,11 @@ static struct radeon_asic r520_asic = {
679 .pm_finish = &rs600_pm_finish, 697 .pm_finish = &rs600_pm_finish,
680 .pm_init_profile = &r420_pm_init_profile, 698 .pm_init_profile = &r420_pm_init_profile,
681 .pm_get_dynpm_state = &r100_pm_get_dynpm_state, 699 .pm_get_dynpm_state = &r100_pm_get_dynpm_state,
682 .pre_page_flip = &rs600_pre_page_flip, 700 .pflip = {
683 .page_flip = &rs600_page_flip, 701 .pre_page_flip = &rs600_pre_page_flip,
684 .post_page_flip = &rs600_post_page_flip, 702 .page_flip = &rs600_page_flip,
703 .post_page_flip = &rs600_post_page_flip,
704 },
685 .wait_for_vblank = &avivo_wait_for_vblank, 705 .wait_for_vblank = &avivo_wait_for_vblank,
686 .mc_wait_for_idle = &r520_mc_wait_for_idle, 706 .mc_wait_for_idle = &r520_mc_wait_for_idle,
687}; 707};
@@ -734,9 +754,11 @@ static struct radeon_asic r600_asic = {
734 .pm_finish = &rs600_pm_finish, 754 .pm_finish = &rs600_pm_finish,
735 .pm_init_profile = &r600_pm_init_profile, 755 .pm_init_profile = &r600_pm_init_profile,
736 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 756 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
737 .pre_page_flip = &rs600_pre_page_flip, 757 .pflip = {
738 .page_flip = &rs600_page_flip, 758 .pre_page_flip = &rs600_pre_page_flip,
739 .post_page_flip = &rs600_post_page_flip, 759 .page_flip = &rs600_page_flip,
760 .post_page_flip = &rs600_post_page_flip,
761 },
740 .wait_for_vblank = &avivo_wait_for_vblank, 762 .wait_for_vblank = &avivo_wait_for_vblank,
741 .mc_wait_for_idle = &r600_mc_wait_for_idle, 763 .mc_wait_for_idle = &r600_mc_wait_for_idle,
742}; 764};
@@ -789,9 +811,11 @@ static struct radeon_asic rs780_asic = {
789 .pm_finish = &rs600_pm_finish, 811 .pm_finish = &rs600_pm_finish,
790 .pm_init_profile = &rs780_pm_init_profile, 812 .pm_init_profile = &rs780_pm_init_profile,
791 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 813 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
792 .pre_page_flip = &rs600_pre_page_flip, 814 .pflip = {
793 .page_flip = &rs600_page_flip, 815 .pre_page_flip = &rs600_pre_page_flip,
794 .post_page_flip = &rs600_post_page_flip, 816 .page_flip = &rs600_page_flip,
817 .post_page_flip = &rs600_post_page_flip,
818 },
795 .wait_for_vblank = &avivo_wait_for_vblank, 819 .wait_for_vblank = &avivo_wait_for_vblank,
796 .mc_wait_for_idle = &r600_mc_wait_for_idle, 820 .mc_wait_for_idle = &r600_mc_wait_for_idle,
797}; 821};
@@ -844,9 +868,11 @@ static struct radeon_asic rv770_asic = {
844 .pm_finish = &rs600_pm_finish, 868 .pm_finish = &rs600_pm_finish,
845 .pm_init_profile = &r600_pm_init_profile, 869 .pm_init_profile = &r600_pm_init_profile,
846 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 870 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
847 .pre_page_flip = &rs600_pre_page_flip, 871 .pflip = {
848 .page_flip = &rv770_page_flip, 872 .pre_page_flip = &rs600_pre_page_flip,
849 .post_page_flip = &rs600_post_page_flip, 873 .page_flip = &rv770_page_flip,
874 .post_page_flip = &rs600_post_page_flip,
875 },
850 .wait_for_vblank = &avivo_wait_for_vblank, 876 .wait_for_vblank = &avivo_wait_for_vblank,
851 .mc_wait_for_idle = &r600_mc_wait_for_idle, 877 .mc_wait_for_idle = &r600_mc_wait_for_idle,
852}; 878};
@@ -899,9 +925,11 @@ static struct radeon_asic evergreen_asic = {
899 .pm_finish = &evergreen_pm_finish, 925 .pm_finish = &evergreen_pm_finish,
900 .pm_init_profile = &r600_pm_init_profile, 926 .pm_init_profile = &r600_pm_init_profile,
901 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 927 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
902 .pre_page_flip = &evergreen_pre_page_flip, 928 .pflip = {
903 .page_flip = &evergreen_page_flip, 929 .pre_page_flip = &evergreen_pre_page_flip,
904 .post_page_flip = &evergreen_post_page_flip, 930 .page_flip = &evergreen_page_flip,
931 .post_page_flip = &evergreen_post_page_flip,
932 },
905 .wait_for_vblank = &dce4_wait_for_vblank, 933 .wait_for_vblank = &dce4_wait_for_vblank,
906 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 934 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
907}; 935};
@@ -954,9 +982,11 @@ static struct radeon_asic sumo_asic = {
954 .pm_finish = &evergreen_pm_finish, 982 .pm_finish = &evergreen_pm_finish,
955 .pm_init_profile = &sumo_pm_init_profile, 983 .pm_init_profile = &sumo_pm_init_profile,
956 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 984 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
957 .pre_page_flip = &evergreen_pre_page_flip, 985 .pflip = {
958 .page_flip = &evergreen_page_flip, 986 .pre_page_flip = &evergreen_pre_page_flip,
959 .post_page_flip = &evergreen_post_page_flip, 987 .page_flip = &evergreen_page_flip,
988 .post_page_flip = &evergreen_post_page_flip,
989 },
960 .wait_for_vblank = &dce4_wait_for_vblank, 990 .wait_for_vblank = &dce4_wait_for_vblank,
961 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 991 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
962}; 992};
@@ -1009,9 +1039,11 @@ static struct radeon_asic btc_asic = {
1009 .pm_finish = &evergreen_pm_finish, 1039 .pm_finish = &evergreen_pm_finish,
1010 .pm_init_profile = &r600_pm_init_profile, 1040 .pm_init_profile = &r600_pm_init_profile,
1011 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 1041 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
1012 .pre_page_flip = &evergreen_pre_page_flip, 1042 .pflip = {
1013 .page_flip = &evergreen_page_flip, 1043 .pre_page_flip = &evergreen_pre_page_flip,
1014 .post_page_flip = &evergreen_post_page_flip, 1044 .page_flip = &evergreen_page_flip,
1045 .post_page_flip = &evergreen_post_page_flip,
1046 },
1015 .wait_for_vblank = &dce4_wait_for_vblank, 1047 .wait_for_vblank = &dce4_wait_for_vblank,
1016 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1048 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1017}; 1049};
@@ -1087,9 +1119,11 @@ static struct radeon_asic cayman_asic = {
1087 .pm_finish = &evergreen_pm_finish, 1119 .pm_finish = &evergreen_pm_finish,
1088 .pm_init_profile = &r600_pm_init_profile, 1120 .pm_init_profile = &r600_pm_init_profile,
1089 .pm_get_dynpm_state = &r600_pm_get_dynpm_state, 1121 .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
1090 .pre_page_flip = &evergreen_pre_page_flip, 1122 .pflip = {
1091 .page_flip = &evergreen_page_flip, 1123 .pre_page_flip = &evergreen_pre_page_flip,
1092 .post_page_flip = &evergreen_post_page_flip, 1124 .page_flip = &evergreen_page_flip,
1125 .post_page_flip = &evergreen_post_page_flip,
1126 },
1093 .wait_for_vblank = &dce4_wait_for_vblank, 1127 .wait_for_vblank = &dce4_wait_for_vblank,
1094 .mc_wait_for_idle = &evergreen_mc_wait_for_idle, 1128 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1095}; 1129};