drm/i915: Add Display Port register defines

This adds the register definitions for the display port enable register
along with those for the GMCH and Link M/N ratios required to drive display
port outputs.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

1 files changed, 163 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 79df9e9c38e4..f6237a0b1133 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -638,8 +638,11 @@
 /* Hotplug control (945+ only) */
 #define PORT_HOTPLUG_EN         0x61110
 #define   HDMIB_HOTPLUG_INT_EN                  (1 << 29)
+#define   DPB_HOTPLUG_INT_EN                    (1 << 29)
 #define   HDMIC_HOTPLUG_INT_EN                  (1 << 28)
+#define   DPC_HOTPLUG_INT_EN                    (1 << 28)
 #define   HDMID_HOTPLUG_INT_EN                  (1 << 27)
+#define   DPD_HOTPLUG_INT_EN                    (1 << 27)
 #define   SDVOB_HOTPLUG_INT_EN                  (1 << 26)
 #define   SDVOC_HOTPLUG_INT_EN                  (1 << 25)
 #define   TV_HOTPLUG_INT_EN                     (1 << 18)
@@ -672,8 +675,11 @@
 
 #define PORT_HOTPLUG_STAT       0x61114
 #define   HDMIB_HOTPLUG_INT_STATUS              (1 << 29)
+#define   DPB_HOTPLUG_INT_STATUS                (1 << 29)
 #define   HDMIC_HOTPLUG_INT_STATUS              (1 << 28)
+#define   DPC_HOTPLUG_INT_STATUS                (1 << 28)
 #define   HDMID_HOTPLUG_INT_STATUS              (1 << 27)
+#define   DPD_HOTPLUG_INT_STATUS                (1 << 27)
 #define   CRT_HOTPLUG_INT_STATUS                (1 << 11)
 #define   TV_HOTPLUG_INT_STATUS                 (1 << 10)
 #define   CRT_HOTPLUG_MONITOR_MASK              (3 << 8)
@@ -1335,6 +1341,163 @@
 #define TV_V_CHROMA_0           0x68400
 #define TV_V_CHROMA_42          0x684a8
 
+/* Display Port */
+#define DP_B                            0x64100
+#define DP_C                            0x64200
+#define DP_D                            0x64300
+
+#define   DP_PORT_EN                    (1 << 31)
+#define   DP_PIPEB_SELECT               (1 << 30)
+
+/* Link training mode - select a suitable mode for each stage */
+#define   DP_LINK_TRAIN_PAT_1           (0 << 28)
+#define   DP_LINK_TRAIN_PAT_2           (1 << 28)
+#define   DP_LINK_TRAIN_PAT_IDLE        (2 << 28)
+#define   DP_LINK_TRAIN_OFF             (3 << 28)
+#define   DP_LINK_TRAIN_MASK            (3 << 28)
+#define   DP_LINK_TRAIN_SHIFT           28
+
+/* Signal voltages. These are mostly controlled by the other end */
+#define   DP_VOLTAGE_0_4                (0 << 25)
+#define   DP_VOLTAGE_0_6                (1 << 25)
+#define   DP_VOLTAGE_0_8                (2 << 25)
+#define   DP_VOLTAGE_1_2                (3 << 25)
+#define   DP_VOLTAGE_MASK               (7 << 25)
+#define   DP_VOLTAGE_SHIFT              25
+
+/* Signal pre-emphasis levels, like voltages, the other end tells us what
+ * they want
+ */
+#define   DP_PRE_EMPHASIS_0             (0 << 22)
+#define   DP_PRE_EMPHASIS_3_5           (1 << 22)
+#define   DP_PRE_EMPHASIS_6             (2 << 22)
+#define   DP_PRE_EMPHASIS_9_5           (3 << 22)
+#define   DP_PRE_EMPHASIS_MASK          (7 << 22)
+#define   DP_PRE_EMPHASIS_SHIFT         22
+
+/* How many wires to use. I guess 3 was too hard */
+#define   DP_PORT_WIDTH_1               (0 << 19)
+#define   DP_PORT_WIDTH_2               (1 << 19)
+#define   DP_PORT_WIDTH_4               (3 << 19)
+#define   DP_PORT_WIDTH_MASK            (7 << 19)
+
+/* Mystic DPCD version 1.1 special mode */
+#define   DP_ENHANCED_FRAMING           (1 << 18)
+
+/** locked once port is enabled */
+#define   DP_PORT_REVERSAL              (1 << 15)
+
+/** sends the clock on lane 15 of the PEG for debug */
+#define   DP_CLOCK_OUTPUT_ENABLE        (1 << 13)
+
+#define   DP_SCRAMBLING_DISABLE         (1 << 12)
+
+/** limit RGB values to avoid confusing TVs */
+#define   DP_COLOR_RANGE_16_235         (1 << 8)
+
+/** Turn on the audio link */
+#define   DP_AUDIO_OUTPUT_ENABLE        (1 << 6)
+
+/** vs and hs sync polarity */
+#define   DP_SYNC_VS_HIGH               (1 << 4)
+#define   DP_SYNC_HS_HIGH               (1 << 3)
+
+/** A fantasy */
+#define   DP_DETECTED                   (1 << 2)
+
+/** The aux channel provides a way to talk to the
+ * signal sink for DDC etc. Max packet size supported
+ * is 20 bytes in each direction, hence the 5 fixed
+ * data registers
+ */
+#define DPB_AUX_CH_CTL                  0x64110
+#define DPB_AUX_CH_DATA1                0x64114
+#define DPB_AUX_CH_DATA2                0x64118
+#define DPB_AUX_CH_DATA3                0x6411c
+#define DPB_AUX_CH_DATA4                0x64120
+#define DPB_AUX_CH_DATA5                0x64124
+
+#define DPC_AUX_CH_CTL                  0x64210
+#define DPC_AUX_CH_DATA1                0x64214
+#define DPC_AUX_CH_DATA2                0x64218
+#define DPC_AUX_CH_DATA3                0x6421c
+#define DPC_AUX_CH_DATA4                0x64220
+#define DPC_AUX_CH_DATA5                0x64224
+
+#define DPD_AUX_CH_CTL                  0x64310
+#define DPD_AUX_CH_DATA1                0x64314
+#define DPD_AUX_CH_DATA2                0x64318
+#define DPD_AUX_CH_DATA3                0x6431c
+#define DPD_AUX_CH_DATA4                0x64320
+#define DPD_AUX_CH_DATA5                0x64324
+
+#define   DP_AUX_CH_CTL_SEND_BUSY           (1 << 31)
+#define   DP_AUX_CH_CTL_DONE                (1 << 30)
+#define   DP_AUX_CH_CTL_INTERRUPT           (1 << 29)
+#define   DP_AUX_CH_CTL_TIME_OUT_ERROR      (1 << 28)
+#define   DP_AUX_CH_CTL_TIME_OUT_400us      (0 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_600us      (1 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_800us      (2 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_1600us     (3 << 26)
+#define   DP_AUX_CH_CTL_TIME_OUT_MASK       (3 << 26)
+#define   DP_AUX_CH_CTL_RECEIVE_ERROR       (1 << 25)
+#define   DP_AUX_CH_CTL_MESSAGE_SIZE_MASK    (0x1f << 20)
+#define   DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT   20
+#define   DP_AUX_CH_CTL_PRECHARGE_2US_MASK   (0xf << 16)
+#define   DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT  16
+#define   DP_AUX_CH_CTL_AUX_AKSV_SELECT     (1 << 15)
+#define   DP_AUX_CH_CTL_MANCHESTER_TEST     (1 << 14)
+#define   DP_AUX_CH_CTL_SYNC_TEST           (1 << 13)
+#define   DP_AUX_CH_CTL_DEGLITCH_TEST       (1 << 12)
+#define   DP_AUX_CH_CTL_PRECHARGE_TEST      (1 << 11)
+#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK    (0x7ff)
+#define   DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT   0
+
+/*
+ * Computing GMCH M and N values for the Display Port link
+ *
+ * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
+ *
+ * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
+ *
+ * The GMCH value is used internally
+ *
+ * bytes_per_pixel is the number of bytes coming out of the plane,
+ * which is after the LUTs, so we want the bytes for our color format.
+ * For our current usage, this is always 3, one byte for R, G and B.
+ */
+#define PIPEA_GMCH_DATA_M                       0x70050
+#define PIPEB_GMCH_DATA_M                       0x71050
+
+/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
+#define   PIPE_GMCH_DATA_M_TU_SIZE_MASK         (0x3f << 25)
+#define   PIPE_GMCH_DATA_M_TU_SIZE_SHIFT        25
+
+#define   PIPE_GMCH_DATA_M_MASK                 (0xffffff)
+
+#define PIPEA_GMCH_DATA_N                       0x70054
+#define PIPEB_GMCH_DATA_N                       0x71054
+#define   PIPE_GMCH_DATA_N_MASK                 (0xffffff)
+
+/*
+ * Computing Link M and N values for the Display Port link
+ *
+ * Link M / N = pixel_clock / ls_clk
+ *
+ * (the DP spec calls pixel_clock the 'strm_clk')
+ *
+ * The Link value is transmitted in the Main Stream
+ * Attributes and VB-ID.
+ */
+
+#define PIPEA_DP_LINK_M                         0x70060
+#define PIPEB_DP_LINK_M                         0x71060
+#define   PIPEA_DP_LINK_M_MASK                  (0xffffff)
+
+#define PIPEA_DP_LINK_N                         0x70064
+#define PIPEB_DP_LINK_N                         0x71064
+#define   PIPEA_DP_LINK_N_MASK                  (0xffffff)
+
 /* Display & cursor control */
 
 /* Pipe A */