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authorRob Clark <robdclark@gmail.com>2013-11-30 12:45:48 -0500
committerRob Clark <robdclark@gmail.com>2014-01-09 14:38:59 -0500
commitfacb4f4e7fae93ddfcfc2a5f2d0417185a7029ed (patch)
tree8f8d12c091997d7d5871a0e0f9ae704a960e0615 /drivers/gpu/drm
parent2e54a92ff2ec6cd70f748d990a3f6646f9b691f3 (diff)
drm/msm: resync generated headers
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h125
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h116
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h171
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h30
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h8
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h8
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h8
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h83
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h8
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h88
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c2
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h7
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h1036
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp_common.xml.h78
14 files changed, 1525 insertions, 243 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 9588098741b5..85d615e7d62f 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
16- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
17 18
18Copyright (C) 2013 by the following authors: 19Copyright (C) 2013 by the following authors:
19- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
@@ -202,6 +203,12 @@ enum a2xx_rb_copy_sample_select {
202 SAMPLE_0123 = 6, 203 SAMPLE_0123 = 6,
203}; 204};
204 205
206enum adreno_mmu_clnt_beh {
207 BEH_NEVR = 0,
208 BEH_TRAN_RNG = 1,
209 BEH_TRAN_FLT = 2,
210};
211
205enum sq_tex_clamp { 212enum sq_tex_clamp {
206 SQ_TEX_WRAP = 0, 213 SQ_TEX_WRAP = 0,
207 SQ_TEX_MIRROR = 1, 214 SQ_TEX_MIRROR = 1,
@@ -238,6 +245,92 @@ enum sq_tex_filter {
238 245
239#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 246#define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1
240 247
248#define REG_A2XX_MH_MMU_CONFIG 0x00000040
249#define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
250#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
251#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
252#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
253static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
254{
255 return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
256}
257#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
258#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
259static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
260{
261 return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
262}
263#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
264#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
265static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
266{
267 return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
268}
269#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
270#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
271static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
272{
273 return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
274}
275#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
276#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
277static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
278{
279 return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
280}
281#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
282#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
283static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
284{
285 return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
286}
287#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
288#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
289static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
290{
291 return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
292}
293#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
294#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
295static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
296{
297 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
298}
299#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
300#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
301static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
302{
303 return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
304}
305#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
306#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
307static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
308{
309 return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
310}
311#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
312#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
313static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
314{
315 return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
316}
317
318#define REG_A2XX_MH_MMU_VA_RANGE 0x00000041
319
320#define REG_A2XX_MH_MMU_PT_BASE 0x00000042
321
322#define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043
323
324#define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044
325
326#define REG_A2XX_MH_MMU_INVALIDATE 0x00000045
327
328#define REG_A2XX_MH_MMU_MPU_BASE 0x00000046
329
330#define REG_A2XX_MH_MMU_MPU_END 0x00000047
331
332#define REG_A2XX_NQWAIT_UNTIL 0x00000394
333
241#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395 334#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000395
242 335
243#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397 336#define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000397
@@ -276,20 +369,6 @@ enum sq_tex_filter {
276 369
277#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 370#define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447
278 371
279#define REG_A2XX_CP_ST_BASE 0x0000044d
280
281#define REG_A2XX_CP_ST_BUFSZ 0x0000044e
282
283#define REG_A2XX_CP_IB1_BASE 0x00000458
284
285#define REG_A2XX_CP_IB1_BUFSZ 0x00000459
286
287#define REG_A2XX_CP_IB2_BASE 0x0000045a
288
289#define REG_A2XX_CP_IB2_BUFSZ 0x0000045b
290
291#define REG_A2XX_CP_STAT 0x0000047f
292
293#define REG_A2XX_RBBM_STATUS 0x000005d0 372#define REG_A2XX_RBBM_STATUS 0x000005d0
294#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 373#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f
295#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 374#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0
@@ -808,6 +887,12 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
808 887
809#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 888#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
810 889
890#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
891
892#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
893
894#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
895
811#define REG_A2XX_RB_DEPTHCONTROL 0x00002200 896#define REG_A2XX_RB_DEPTHCONTROL 0x00002200
812#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 897#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001
813#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 898#define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index d4afdf657559..a7be56163d23 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
16- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
17 18
18Copyright (C) 2013 by the following authors: 19Copyright (C) 2013 by the following authors:
19- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
@@ -292,6 +293,8 @@ enum a3xx_tex_type {
292#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 293#define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
293#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 294#define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
294 295
296#define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
297
295#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 298#define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
296 299
297#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 300#define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
@@ -304,6 +307,8 @@ enum a3xx_tex_type {
304 307
305#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a 308#define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
306 309
310#define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
311
307#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 312#define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
308 313
309#define REG_A3XX_RBBM_INT_0_MASK 0x00000063 314#define REG_A3XX_RBBM_INT_0_MASK 0x00000063
@@ -937,13 +942,13 @@ static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
937 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; 942 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
938} 943}
939 944
940#define REG_A3XX_UNKNOWN_20E8 0x000020e8 945#define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
941 946
942#define REG_A3XX_UNKNOWN_20E9 0x000020e9 947#define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
943 948
944#define REG_A3XX_UNKNOWN_20EA 0x000020ea 949#define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
945 950
946#define REG_A3XX_UNKNOWN_20EB 0x000020eb 951#define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
947 952
948#define REG_A3XX_RB_COPY_CONTROL 0x000020ec 953#define REG_A3XX_RB_COPY_CONTROL 0x000020ec
949#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 954#define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
@@ -1026,7 +1031,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1026#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080 1031#define A3XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1027#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000 1032#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1028 1033
1029#define REG_A3XX_UNKNOWN_2101 0x00002101 1034#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
1030 1035
1031#define REG_A3XX_RB_DEPTH_INFO 0x00002102 1036#define REG_A3XX_RB_DEPTH_INFO 0x00002102
1032#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1037#define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001
@@ -1103,11 +1108,11 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
1103 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; 1108 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1104} 1109}
1105 1110
1106#define REG_A3XX_UNKNOWN_2105 0x00002105 1111#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
1107 1112
1108#define REG_A3XX_UNKNOWN_2106 0x00002106 1113#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106
1109 1114
1110#define REG_A3XX_UNKNOWN_2107 0x00002107 1115#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107
1111 1116
1112#define REG_A3XX_RB_STENCILREFMASK 0x00002108 1117#define REG_A3XX_RB_STENCILREFMASK 0x00002108
1113#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1118#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
@@ -1149,20 +1154,31 @@ static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1149 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1154 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1150} 1155}
1151 1156
1152#define REG_A3XX_PA_SC_WINDOW_OFFSET 0x0000210e 1157#define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
1153#define A3XX_PA_SC_WINDOW_OFFSET_X__MASK 0x0000ffff 1158#define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
1154#define A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 1159
1155static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_X(uint32_t val) 1160#define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
1161#define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
1162#define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
1163static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
1156{ 1164{
1157 return ((val) << A3XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_X__MASK; 1165 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
1158} 1166}
1159#define A3XX_PA_SC_WINDOW_OFFSET_Y__MASK 0xffff0000 1167#define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
1160#define A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 1168#define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
1161static inline uint32_t A3XX_PA_SC_WINDOW_OFFSET_Y(uint32_t val) 1169static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1162{ 1170{
1163 return ((val) << A3XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A3XX_PA_SC_WINDOW_OFFSET_Y__MASK; 1171 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
1164} 1172}
1165 1173
1174#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
1175
1176#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
1177
1178#define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
1179
1180#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
1181
1166#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1182#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1167 1183
1168#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1184#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
@@ -1309,6 +1325,8 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1309 1325
1310#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215 1326#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215
1311 1327
1328#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
1329
1312#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 1330#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1313 1331
1314#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a 1332#define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
@@ -1491,12 +1509,13 @@ static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0
1491 1509
1492#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 1510#define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
1493#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 1511#define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
1494#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x000c0000 1512#define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
1495#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 1513#define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
1496static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) 1514static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
1497{ 1515{
1498 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; 1516 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
1499} 1517}
1518#define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
1500#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 1519#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
1501#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 1520#define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
1502static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) 1521static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
@@ -1669,7 +1688,7 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1669 1688
1670#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 1689#define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
1671 1690
1672#define REG_A3XX_SP_VS_PVT_MEM_CTRL_REG 0x000022d6 1691#define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
1673 1692
1674#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 1693#define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
1675 1694
@@ -1772,7 +1791,7 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1772 1791
1773#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 1792#define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
1774 1793
1775#define REG_A3XX_SP_FS_PVT_MEM_CTRL_REG 0x000022e4 1794#define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
1776 1795
1777#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 1796#define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
1778 1797
@@ -1943,6 +1962,9 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00
1943 1962
1944static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1963static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
1945 1964
1965#define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
1966#define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
1967
1946#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d 1968#define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
1947 1969
1948#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 1970#define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
@@ -1953,7 +1975,7 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
1953 1975
1954#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b 1976#define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
1955 1977
1956#define REG_A3XX_UNKNOWN_0C81 0x00000c81 1978#define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
1957 1979
1958#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 1980#define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
1959 1981
@@ -1975,22 +1997,24 @@ static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x000
1975 1997
1976#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 1998#define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
1977 1999
2000#define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
2001
1978#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 2002#define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
1979 2003
1980#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 2004#define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
1981 2005
1982#define REG_A3XX_RB_WINDOW_SIZE 0x00000ce0 2006#define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
1983#define A3XX_RB_WINDOW_SIZE_WIDTH__MASK 0x00003fff 2007#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
1984#define A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT 0 2008#define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
1985static inline uint32_t A3XX_RB_WINDOW_SIZE_WIDTH(uint32_t val) 2009static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
1986{ 2010{
1987 return ((val) << A3XX_RB_WINDOW_SIZE_WIDTH__SHIFT) & A3XX_RB_WINDOW_SIZE_WIDTH__MASK; 2011 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
1988} 2012}
1989#define A3XX_RB_WINDOW_SIZE_HEIGHT__MASK 0x0fffc000 2013#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
1990#define A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT 14 2014#define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
1991static inline uint32_t A3XX_RB_WINDOW_SIZE_HEIGHT(uint32_t val) 2015static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
1992{ 2016{
1993 return ((val) << A3XX_RB_WINDOW_SIZE_HEIGHT__SHIFT) & A3XX_RB_WINDOW_SIZE_HEIGHT__MASK; 2017 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
1994} 2018}
1995 2019
1996#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 2020#define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
@@ -2088,6 +2112,14 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
2088 2112
2089#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 2113#define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
2090 2114
2115#define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
2116
2117#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
2118
2119#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
2120
2121#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
2122
2091#define REG_A3XX_TEX_SAMP_0 0x00000000 2123#define REG_A3XX_TEX_SAMP_0 0x00000000
2092#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 2124#define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
2093#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c 2125#define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
@@ -2123,6 +2155,18 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
2123#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2155#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2124 2156
2125#define REG_A3XX_TEX_SAMP_1 0x00000001 2157#define REG_A3XX_TEX_SAMP_1 0x00000001
2158#define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
2159#define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
2160static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
2161{
2162 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
2163}
2164#define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
2165#define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
2166static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
2167{
2168 return ((((uint32_t)(val * 12.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
2169}
2126 2170
2127#define REG_A3XX_TEX_CONST_0 0x00000000 2171#define REG_A3XX_TEX_CONST_0 0x00000000
2128#define A3XX_TEX_CONST_0_TILED 0x00000001 2172#define A3XX_TEX_CONST_0_TILED 0x00000001
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index 33dcc606c7c5..d6e6ce2d1abd 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
16- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
17 18
18Copyright (C) 2013 by the following authors: 19Copyright (C) 2013 by the following authors:
19- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
@@ -115,96 +116,6 @@ enum adreno_rb_depth_format {
115 DEPTHX_24_8 = 1, 116 DEPTHX_24_8 = 1,
116}; 117};
117 118
118enum adreno_mmu_clnt_beh {
119 BEH_NEVR = 0,
120 BEH_TRAN_RNG = 1,
121 BEH_TRAN_FLT = 2,
122};
123
124#define REG_AXXX_MH_MMU_CONFIG 0x00000040
125#define AXXX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001
126#define AXXX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002
127#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030
128#define AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4
129static inline uint32_t AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
130{
131 return ((val) << AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
132}
133#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0
134#define AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6
135static inline uint32_t AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
136{
137 return ((val) << AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
138}
139#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300
140#define AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8
141static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
142{
143 return ((val) << AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
144}
145#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00
146#define AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10
147static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
148{
149 return ((val) << AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
150}
151#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000
152#define AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12
153static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
154{
155 return ((val) << AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
156}
157#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000
158#define AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14
159static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
160{
161 return ((val) << AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
162}
163#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000
164#define AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16
165static inline uint32_t AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
166{
167 return ((val) << AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
168}
169#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000
170#define AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18
171static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
172{
173 return ((val) << AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
174}
175#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000
176#define AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20
177static inline uint32_t AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
178{
179 return ((val) << AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
180}
181#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000
182#define AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22
183static inline uint32_t AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
184{
185 return ((val) << AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
186}
187#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000
188#define AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24
189static inline uint32_t AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
190{
191 return ((val) << AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & AXXX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
192}
193
194#define REG_AXXX_MH_MMU_VA_RANGE 0x00000041
195
196#define REG_AXXX_MH_MMU_PT_BASE 0x00000042
197
198#define REG_AXXX_MH_MMU_PAGE_FAULT 0x00000043
199
200#define REG_AXXX_MH_MMU_TRAN_ERROR 0x00000044
201
202#define REG_AXXX_MH_MMU_INVALIDATE 0x00000045
203
204#define REG_AXXX_MH_MMU_MPU_BASE 0x00000046
205
206#define REG_AXXX_MH_MMU_MPU_END 0x00000047
207
208#define REG_AXXX_CP_RB_BASE 0x000001c0 119#define REG_AXXX_CP_RB_BASE 0x000001c0
209 120
210#define REG_AXXX_CP_RB_CNTL 0x000001c1 121#define REG_AXXX_CP_RB_CNTL 0x000001c1
@@ -275,6 +186,18 @@ static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val)
275} 186}
276 187
277#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 188#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
189#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
190#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
191static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val)
192{
193 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK;
194}
195#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
196#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
197static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val)
198{
199 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK;
200}
278 201
279#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 202#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
280#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 203#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
@@ -402,6 +325,36 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
402 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 325 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK;
403} 326}
404 327
328#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
329
330#define REG_AXXX_CP_STQ_ST_STAT 0x00000443
331
332#define REG_AXXX_CP_ST_BASE 0x0000044d
333
334#define REG_AXXX_CP_ST_BUFSZ 0x0000044e
335
336#define REG_AXXX_CP_MEQ_STAT 0x0000044f
337
338#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
339
340#define REG_AXXX_CP_BIN_MASK_LO 0x00000454
341
342#define REG_AXXX_CP_BIN_MASK_HI 0x00000455
343
344#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
345
346#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
347
348#define REG_AXXX_CP_IB1_BASE 0x00000458
349
350#define REG_AXXX_CP_IB1_BUFSZ 0x00000459
351
352#define REG_AXXX_CP_IB2_BASE 0x0000045a
353
354#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
355
356#define REG_AXXX_CP_STAT 0x0000047f
357
405#define REG_AXXX_CP_SCRATCH_REG0 0x00000578 358#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
406 359
407#define REG_AXXX_CP_SCRATCH_REG1 0x00000579 360#define REG_AXXX_CP_SCRATCH_REG1 0x00000579
@@ -418,6 +371,26 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
418 371
419#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 372#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
420 373
374#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
375
376#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
377
378#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
379
380#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
381
382#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
383
384#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
385
386#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
387
388#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
389
390#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
391
392#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
393
421#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 394#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
422 395
423#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 396#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
@@ -428,5 +401,11 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
428 401
429#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 402#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
430 403
404#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
405
406#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
407
408#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
409
431 410
432#endif /* ADRENO_COMMON_XML */ 411#endif /* ADRENO_COMMON_XML */
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index 259ad709b0cc..ae992c71703f 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,12 +8,13 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 327 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/a2xx/a2xx.xml ( 31003 bytes, from 2013-09-19 18:50:16) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml ( 8983 bytes, from 2013-07-24 01:38:36) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml ( 9759 bytes, from 2013-09-10 00:52:33) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45)
16- /home/robclark/src/freedreno/envytools/rnndb/a3xx/a3xx.xml ( 51983 bytes, from 2013-09-10 00:52:32) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
17 18
18Copyright (C) 2013 by the following authors: 19Copyright (C) 2013 by the following authors:
19- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
@@ -66,13 +67,15 @@ enum vgt_event_type {
66 67
67enum pc_di_primtype { 68enum pc_di_primtype {
68 DI_PT_NONE = 0, 69 DI_PT_NONE = 0,
69 DI_PT_POINTLIST = 1, 70 DI_PT_POINTLIST_A2XX = 1,
70 DI_PT_LINELIST = 2, 71 DI_PT_LINELIST = 2,
71 DI_PT_LINESTRIP = 3, 72 DI_PT_LINESTRIP = 3,
72 DI_PT_TRILIST = 4, 73 DI_PT_TRILIST = 4,
73 DI_PT_TRIFAN = 5, 74 DI_PT_TRIFAN = 5,
74 DI_PT_TRISTRIP = 6, 75 DI_PT_TRISTRIP = 6,
76 DI_PT_LINELOOP = 7,
75 DI_PT_RECTLIST = 8, 77 DI_PT_RECTLIST = 8,
78 DI_PT_POINTLIST_A3XX = 9,
76 DI_PT_QUADLIST = 13, 79 DI_PT_QUADLIST = 13,
77 DI_PT_QUADSTRIP = 14, 80 DI_PT_QUADSTRIP = 14,
78 DI_PT_POLYGON = 15, 81 DI_PT_POLYGON = 15,
@@ -119,7 +122,7 @@ enum adreno_pm4_type3_packets {
119 CP_WAIT_FOR_IDLE = 38, 122 CP_WAIT_FOR_IDLE = 38,
120 CP_WAIT_REG_MEM = 60, 123 CP_WAIT_REG_MEM = 60,
121 CP_WAIT_REG_EQ = 82, 124 CP_WAIT_REG_EQ = 82,
122 CP_WAT_REG_GTE = 83, 125 CP_WAIT_REG_GTE = 83,
123 CP_WAIT_UNTIL_READ = 92, 126 CP_WAIT_UNTIL_READ = 92,
124 CP_WAIT_IB_PFD_COMPLETE = 93, 127 CP_WAIT_IB_PFD_COMPLETE = 93,
125 CP_REG_RMW = 33, 128 CP_REG_RMW = 33,
@@ -151,7 +154,6 @@ enum adreno_pm4_type3_packets {
151 CP_CONTEXT_UPDATE = 94, 154 CP_CONTEXT_UPDATE = 94,
152 CP_INTERRUPT = 64, 155 CP_INTERRUPT = 64,
153 CP_IM_STORE = 44, 156 CP_IM_STORE = 44,
154 CP_SET_BIN_BASE_OFFSET = 75,
155 CP_SET_DRAW_INIT_FLAGS = 75, 157 CP_SET_DRAW_INIT_FLAGS = 75,
156 CP_SET_PROTECTED_MODE = 95, 158 CP_SET_PROTECTED_MODE = 95,
157 CP_LOAD_STATE = 48, 159 CP_LOAD_STATE = 48,
@@ -159,6 +161,16 @@ enum adreno_pm4_type3_packets {
159 CP_COND_INDIRECT_BUFFER_PFD = 50, 161 CP_COND_INDIRECT_BUFFER_PFD = 50,
160 CP_INDIRECT_BUFFER_PFE = 63, 162 CP_INDIRECT_BUFFER_PFE = 63,
161 CP_SET_BIN = 76, 163 CP_SET_BIN = 76,
164 CP_TEST_TWO_MEMS = 113,
165 CP_WAIT_FOR_ME = 19,
166 IN_IB_PREFETCH_END = 23,
167 IN_SUBBLK_PREFETCH = 31,
168 IN_INSTR_PREFETCH = 32,
169 IN_INSTR_MATCH = 71,
170 IN_CONST_PREFETCH = 73,
171 IN_INCR_UPDT_STATE = 85,
172 IN_INCR_UPDT_CONST = 86,
173 IN_INCR_UPDT_INSTR = 87,
162}; 174};
163 175
164enum adreno_state_block { 176enum adreno_state_block {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 6d4c62bf70dc..87be647e3825 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
index d1df38bf5747..747a6ef4211f 100644
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
index 0030a111302d..48e03acf19bf 100644
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index 4e939f82918c..e2636582cfd7 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
@@ -212,6 +214,20 @@ static inline uint32_t HDMI_HDCP_LINK0_STATUS_KEY_STATE(enum hdmi_hdcp_key_state
212#define REG_HDMI_HDCP_RESET 0x00000130 214#define REG_HDMI_HDCP_RESET 0x00000130
213#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001 215#define HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE 0x00000001
214 216
217#define REG_HDMI_VENSPEC_INFO0 0x0000016c
218
219#define REG_HDMI_VENSPEC_INFO1 0x00000170
220
221#define REG_HDMI_VENSPEC_INFO2 0x00000174
222
223#define REG_HDMI_VENSPEC_INFO3 0x00000178
224
225#define REG_HDMI_VENSPEC_INFO4 0x0000017c
226
227#define REG_HDMI_VENSPEC_INFO5 0x00000180
228
229#define REG_HDMI_VENSPEC_INFO6 0x00000184
230
215#define REG_HDMI_AUDIO_CFG 0x000001d0 231#define REG_HDMI_AUDIO_CFG 0x000001d0
216#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001 232#define HDMI_AUDIO_CFG_ENGINE_ENABLE 0x00000001
217#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0 233#define HDMI_AUDIO_CFG_FIFO_WATERMARK__MASK 0x000000f0
@@ -235,6 +251,9 @@ static inline uint32_t HDMI_DDC_CTRL_TRANSACTION_CNT(uint32_t val)
235 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK; 251 return ((val) << HDMI_DDC_CTRL_TRANSACTION_CNT__SHIFT) & HDMI_DDC_CTRL_TRANSACTION_CNT__MASK;
236} 252}
237 253
254#define REG_HDMI_DDC_ARBITRATION 0x00000210
255#define HDMI_DDC_ARBITRATION_HW_ARBITRATION 0x00000010
256
238#define REG_HDMI_DDC_INT_CTRL 0x00000214 257#define REG_HDMI_DDC_INT_CTRL 0x00000214
239#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001 258#define HDMI_DDC_INT_CTRL_SW_DONE_INT 0x00000001
240#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002 259#define HDMI_DDC_INT_CTRL_SW_DONE_ACK 0x00000002
@@ -340,6 +359,20 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
340 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK; 359 return ((val) << HDMI_DDC_REF_REFTIMER__SHIFT) & HDMI_DDC_REF_REFTIMER__MASK;
341} 360}
342 361
362#define REG_HDMI_CEC_STATUS 0x00000298
363
364#define REG_HDMI_CEC_INT 0x0000029c
365
366#define REG_HDMI_CEC_ADDR 0x000002a0
367
368#define REG_HDMI_CEC_TIME 0x000002a4
369
370#define REG_HDMI_CEC_REFTIMER 0x000002a8
371
372#define REG_HDMI_CEC_RD_DATA 0x000002ac
373
374#define REG_HDMI_CEC_RD_FILTER 0x000002b0
375
343#define REG_HDMI_ACTIVE_HSYNC 0x000002b4 376#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
344#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff 377#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
345#define HDMI_ACTIVE_HSYNC_START__SHIFT 0 378#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
@@ -410,17 +443,33 @@ static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
410#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000 443#define HDMI_FRAME_CTRL_HSYNC_LOW 0x20000000
411#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000 444#define HDMI_FRAME_CTRL_INTERLACED_EN 0x80000000
412 445
446#define REG_HDMI_AUD_INT 0x000002cc
447#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001
448#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002
449#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004
450#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008
451
413#define REG_HDMI_PHY_CTRL 0x000002d4 452#define REG_HDMI_PHY_CTRL 0x000002d4
414#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001 453#define HDMI_PHY_CTRL_SW_RESET_PLL 0x00000001
415#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002 454#define HDMI_PHY_CTRL_SW_RESET_PLL_LOW 0x00000002
416#define HDMI_PHY_CTRL_SW_RESET 0x00000004 455#define HDMI_PHY_CTRL_SW_RESET 0x00000004
417#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008 456#define HDMI_PHY_CTRL_SW_RESET_LOW 0x00000008
418 457
419#define REG_HDMI_AUD_INT 0x000002cc 458#define REG_HDMI_CEC_WR_RANGE 0x000002dc
420#define HDMI_AUD_INT_AUD_FIFO_URUN_INT 0x00000001 459
421#define HDMI_AUD_INT_AUD_FIFO_URAN_MASK 0x00000002 460#define REG_HDMI_CEC_RD_RANGE 0x000002e0
422#define HDMI_AUD_INT_AUD_SAM_DROP_INT 0x00000004 461
423#define HDMI_AUD_INT_AUD_SAM_DROP_MASK 0x00000008 462#define REG_HDMI_VERSION 0x000002e4
463
464#define REG_HDMI_CEC_COMPL_CTL 0x00000360
465
466#define REG_HDMI_CEC_RD_START_RANGE 0x00000364
467
468#define REG_HDMI_CEC_RD_TOTAL_RANGE 0x00000368
469
470#define REG_HDMI_CEC_RD_ERR_RESP_LO 0x0000036c
471
472#define REG_HDMI_CEC_WR_CHECK_CONFIG 0x00000370
424 473
425#define REG_HDMI_8x60_PHY_REG0 0x00000300 474#define REG_HDMI_8x60_PHY_REG0 0x00000300
426#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c 475#define HDMI_8x60_PHY_REG0_DESER_DEL_CTRL__MASK 0x0000001c
@@ -504,5 +553,23 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
504 553
505#define REG_HDMI_8960_PHY_REG12 0x00000430 554#define REG_HDMI_8960_PHY_REG12 0x00000430
506 555
556#define REG_HDMI_8x74_ANA_CFG0 0x00000000
557
558#define REG_HDMI_8x74_ANA_CFG1 0x00000004
559
560#define REG_HDMI_8x74_PD_CTRL0 0x00000010
561
562#define REG_HDMI_8x74_PD_CTRL1 0x00000014
563
564#define REG_HDMI_8x74_BIST_CFG0 0x00000034
565
566#define REG_HDMI_8x74_BIST_PATN0 0x0000003c
567
568#define REG_HDMI_8x74_BIST_PATN1 0x00000040
569
570#define REG_HDMI_8x74_BIST_PATN2 0x00000044
571
572#define REG_HDMI_8x74_BIST_PATN3 0x00000048
573
507 574
508#endif /* HDMI_XML */ 575#endif /* HDMI_XML */
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
index dbde4f6339b9..d591567173c4 100644
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 9908ffe1c3ad..416a26e1e58d 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -8,14 +8,16 @@ http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git 8git clone https://github.com/freedreno/envytools.git
9 9
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 595 bytes, from 2013-07-05 19:21:12) 11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp4/mdp4.xml ( 19332 bytes, from 2013-10-07 16:36:48) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
14- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
15- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
17- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
18- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 19288 bytes, from 2013-08-11 18:14:15) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
19 21
20Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
21- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
@@ -42,27 +44,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42*/ 44*/
43 45
44 46
45enum mdp4_bpc {
46 BPC1 = 0,
47 BPC5 = 1,
48 BPC6 = 2,
49 BPC8 = 3,
50};
51
52enum mdp4_bpc_alpha {
53 BPC1A = 0,
54 BPC4A = 1,
55 BPC6A = 2,
56 BPC8A = 3,
57};
58
59enum mdp4_alpha_type {
60 FG_CONST = 0,
61 BG_CONST = 1,
62 FG_PIXEL = 2,
63 BG_PIXEL = 3,
64};
65
66enum mdp4_pipe { 47enum mdp4_pipe {
67 VG1 = 0, 48 VG1 = 0,
68 VG2 = 1, 49 VG2 = 1,
@@ -79,15 +60,6 @@ enum mdp4_mixer {
79 MIXER2 = 2, 60 MIXER2 = 2,
80}; 61};
81 62
82enum mdp4_mixer_stage_id {
83 STAGE_UNUSED = 0,
84 STAGE_BASE = 1,
85 STAGE0 = 2,
86 STAGE1 = 3,
87 STAGE2 = 4,
88 STAGE3 = 5,
89};
90
91enum mdp4_intf { 63enum mdp4_intf {
92 INTF_LCDC_DTV = 0, 64 INTF_LCDC_DTV = 0,
93 INTF_DSI_VIDEO = 1, 65 INTF_DSI_VIDEO = 1,
@@ -194,56 +166,56 @@ static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)
194#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0 166#define REG_MDP4_LAYERMIXER2_IN_CFG 0x000100f0
195#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007 167#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK 0x00000007
196#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0 168#define MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT 0
197static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val) 169static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
198{ 170{
199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK; 171 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;
200} 172}
201#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008 173#define MDP4_LAYERMIXER2_IN_CFG_PIPE0_MIXER1 0x00000008
202#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070 174#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK 0x00000070
203#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4 175#define MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT 4
204static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val) 176static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
205{ 177{
206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK; 178 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;
207} 179}
208#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080 180#define MDP4_LAYERMIXER2_IN_CFG_PIPE1_MIXER1 0x00000080
209#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700 181#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK 0x00000700
210#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8 182#define MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT 8
211static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val) 183static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
212{ 184{
213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK; 185 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;
214} 186}
215#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800 187#define MDP4_LAYERMIXER2_IN_CFG_PIPE2_MIXER1 0x00000800
216#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000 188#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK 0x00007000
217#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12 189#define MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT 12
218static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val) 190static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
219{ 191{
220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK; 192 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;
221} 193}
222#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000 194#define MDP4_LAYERMIXER2_IN_CFG_PIPE3_MIXER1 0x00008000
223#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000 195#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK 0x00070000
224#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16 196#define MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT 16
225static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val) 197static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
226{ 198{
227 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK; 199 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;
228} 200}
229#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000 201#define MDP4_LAYERMIXER2_IN_CFG_PIPE4_MIXER1 0x00080000
230#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000 202#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK 0x00700000
231#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20 203#define MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT 20
232static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val) 204static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
233{ 205{
234 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK; 206 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;
235} 207}
236#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000 208#define MDP4_LAYERMIXER2_IN_CFG_PIPE5_MIXER1 0x00800000
237#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000 209#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK 0x07000000
238#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24 210#define MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT 24
239static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val) 211static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
240{ 212{
241 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK; 213 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;
242} 214}
243#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000 215#define MDP4_LAYERMIXER2_IN_CFG_PIPE6_MIXER1 0x08000000
244#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000 216#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK 0x70000000
245#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28 217#define MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT 28
246static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val) 218static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
247{ 219{
248 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK; 220 return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;
249} 221}
@@ -254,56 +226,56 @@ static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp4_mixer_stage_id va
254#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100 226#define REG_MDP4_LAYERMIXER_IN_CFG 0x00010100
255#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007 227#define MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK 0x00000007
256#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0 228#define MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT 0
257static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp4_mixer_stage_id val) 229static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)
258{ 230{
259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK; 231 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;
260} 232}
261#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008 233#define MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1 0x00000008
262#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070 234#define MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK 0x00000070
263#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4 235#define MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT 4
264static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp4_mixer_stage_id val) 236static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)
265{ 237{
266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK; 238 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;
267} 239}
268#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080 240#define MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1 0x00000080
269#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700 241#define MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK 0x00000700
270#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8 242#define MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT 8
271static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp4_mixer_stage_id val) 243static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)
272{ 244{
273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK; 245 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;
274} 246}
275#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800 247#define MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1 0x00000800
276#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000 248#define MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK 0x00007000
277#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12 249#define MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT 12
278static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp4_mixer_stage_id val) 250static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)
279{ 251{
280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK; 252 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;
281} 253}
282#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000 254#define MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1 0x00008000
283#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000 255#define MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK 0x00070000
284#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16 256#define MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT 16
285static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp4_mixer_stage_id val) 257static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)
286{ 258{
287 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK; 259 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;
288} 260}
289#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000 261#define MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1 0x00080000
290#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000 262#define MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK 0x00700000
291#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20 263#define MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT 20
292static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp4_mixer_stage_id val) 264static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)
293{ 265{
294 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK; 266 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;
295} 267}
296#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000 268#define MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1 0x00800000
297#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000 269#define MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK 0x07000000
298#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24 270#define MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT 24
299static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp4_mixer_stage_id val) 271static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)
300{ 272{
301 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK; 273 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;
302} 274}
303#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000 275#define MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1 0x08000000
304#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000 276#define MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK 0x70000000
305#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28 277#define MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT 28
306static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp4_mixer_stage_id val) 278static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)
307{ 279{
308 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK; 280 return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;
309} 281}
@@ -369,7 +341,7 @@ static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x
369static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } 341static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); }
370#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003 342#define MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK 0x00000003
371#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0 343#define MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT 0
372static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val) 344static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)
373{ 345{
374 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK; 346 return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;
375} 347}
@@ -377,7 +349,7 @@ static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp4_alpha_type val)
377#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008 349#define MDP4_OVLP_STAGE_OP_FG_MOD_ALPHA 0x00000008
378#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030 350#define MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK 0x00000030
379#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4 351#define MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT 4
380static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp4_alpha_type val) 352static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)
381{ 353{
382 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK; 354 return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;
383} 355}
@@ -472,19 +444,19 @@ static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __of
472static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } 444static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }
473#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003 445#define MDP4_DMA_CONFIG_G_BPC__MASK 0x00000003
474#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0 446#define MDP4_DMA_CONFIG_G_BPC__SHIFT 0
475static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp4_bpc val) 447static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)
476{ 448{
477 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK; 449 return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;
478} 450}
479#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c 451#define MDP4_DMA_CONFIG_B_BPC__MASK 0x0000000c
480#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2 452#define MDP4_DMA_CONFIG_B_BPC__SHIFT 2
481static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp4_bpc val) 453static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)
482{ 454{
483 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK; 455 return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;
484} 456}
485#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030 457#define MDP4_DMA_CONFIG_R_BPC__MASK 0x00000030
486#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4 458#define MDP4_DMA_CONFIG_R_BPC__SHIFT 4
487static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp4_bpc val) 459static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)
488{ 460{
489 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK; 461 return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;
490} 462}
@@ -710,25 +682,25 @@ static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)
710static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } 682static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; }
711#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 683#define MDP4_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
712#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 684#define MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
713static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp4_bpc val) 685static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
714{ 686{
715 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK; 687 return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;
716} 688}
717#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c 689#define MDP4_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
718#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 690#define MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
719static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp4_bpc val) 691static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
720{ 692{
721 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK; 693 return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;
722} 694}
723#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 695#define MDP4_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
724#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 696#define MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
725static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp4_bpc val) 697static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
726{ 698{
727 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK; 699 return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;
728} 700}
729#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 701#define MDP4_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
730#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 702#define MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
731static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp4_bpc_alpha val) 703static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
732{ 704{
733 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK; 705 return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;
734} 706}
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
index 019d530187ff..d0ff3901bf5a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c
@@ -232,7 +232,7 @@ static void blend_setup(struct drm_crtc *crtc)
232 struct mdp4_kms *mdp4_kms = get_kms(crtc); 232 struct mdp4_kms *mdp4_kms = get_kms(crtc);
233 int i, ovlp = mdp4_crtc->ovlp; 233 int i, ovlp = mdp4_crtc->ovlp;
234 uint32_t mixer_cfg = 0; 234 uint32_t mixer_cfg = 0;
235 static const enum mdp4_mixer_stage_id stages[] = { 235 static const enum mdp_mixer_stage_id stages[] = {
236 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3, 236 STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3,
237 }; 237 };
238 /* statically (for now) map planes to mixer stage (z-order): */ 238 /* statically (for now) map planes to mixer stage (z-order): */
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
index eb015c834087..5da111f372cd 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h
@@ -23,6 +23,7 @@
23#include <linux/regulator/consumer.h> 23#include <linux/regulator/consumer.h>
24 24
25#include "msm_drv.h" 25#include "msm_drv.h"
26#include "mdp/mdp_common.xml.h"
26#include "mdp4.xml.h" 27#include "mdp4.xml.h"
27 28
28 29
@@ -75,8 +76,8 @@ struct mdp4_platform_config {
75 76
76struct mdp4_format { 77struct mdp4_format {
77 struct msm_format base; 78 struct msm_format base;
78 enum mdp4_bpc bpc_r, bpc_g, bpc_b; 79 enum mdp_bpc bpc_r, bpc_g, bpc_b;
79 enum mdp4_bpc_alpha bpc_a; 80 enum mdp_bpc_alpha bpc_a;
80 uint8_t unpack[4]; 81 uint8_t unpack[4];
81 bool alpha_enable, unpack_tight; 82 bool alpha_enable, unpack_tight;
82 uint8_t cpp, unpack_count; 83 uint8_t cpp, unpack_count;
@@ -134,7 +135,7 @@ static inline uint32_t dma2err(enum mdp4_dma dma)
134} 135}
135 136
136static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe, 137static inline uint32_t mixercfg(int mixer, enum mdp4_pipe pipe,
137 enum mdp4_mixer_stage_id stage) 138 enum mdp_mixer_stage_id stage)
138{ 139{
139 uint32_t mixer_cfg = 0; 140 uint32_t mixer_cfg = 0;
140 141
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
new file mode 100644
index 000000000000..0aa51517f826
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -0,0 +1,1036 @@
1#ifndef MDP5_XML
2#define MDP5_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
21
22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark)
24
25Permission is hereby granted, free of charge, to any person obtaining
26a copy of this software and associated documentation files (the
27"Software"), to deal in the Software without restriction, including
28without limitation the rights to use, copy, modify, merge, publish,
29distribute, sublicense, and/or sell copies of the Software, and to
30permit persons to whom the Software is furnished to do so, subject to
31the following conditions:
32
33The above copyright notice and this permission notice (including the
34next paragraph) shall be included in all copies or substantial
35portions of the Software.
36
37THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44*/
45
46
47enum mdp5_intf {
48 INTF_DSI = 1,
49 INTF_HDMI = 3,
50 INTF_LCDC = 5,
51 INTF_eDP = 9,
52};
53
54enum mdp5_intfnum {
55 NO_INTF = 0,
56 INTF0 = 1,
57 INTF1 = 2,
58 INTF2 = 3,
59 INTF3 = 4,
60};
61
62enum mdp5_pipe {
63 SSPP_VIG0 = 0,
64 SSPP_VIG1 = 1,
65 SSPP_VIG2 = 2,
66 SSPP_RGB0 = 3,
67 SSPP_RGB1 = 4,
68 SSPP_RGB2 = 5,
69 SSPP_DMA0 = 6,
70 SSPP_DMA1 = 7,
71};
72
73enum mdp5_ctl_mode {
74 MODE_NONE = 0,
75 MODE_ROT0 = 1,
76 MODE_ROT1 = 2,
77 MODE_WB0 = 3,
78 MODE_WB1 = 4,
79 MODE_WFD = 5,
80};
81
82enum mdp5_pack_3d {
83 PACK_3D_FRAME_INT = 0,
84 PACK_3D_H_ROW_INT = 1,
85 PACK_3D_V_ROW_INT = 2,
86 PACK_3D_COL_INT = 3,
87};
88
89enum mdp5_chroma_samp_type {
90 CHROMA_RGB = 0,
91 CHROMA_H2V1 = 1,
92 CHROMA_H1V2 = 2,
93 CHROMA_420 = 3,
94};
95
96enum mdp5_scale_filter {
97 SCALE_FILTER_NEAREST = 0,
98 SCALE_FILTER_BIL = 1,
99 SCALE_FILTER_PCMN = 2,
100 SCALE_FILTER_CA = 3,
101};
102
103enum mdp5_pipe_bwc {
104 BWC_LOSSLESS = 0,
105 BWC_Q_HIGH = 1,
106 BWC_Q_MED = 2,
107};
108
109enum mdp5_client_id {
110 CID_UNUSED = 0,
111 CID_VIG0_Y = 1,
112 CID_VIG0_CR = 2,
113 CID_VIG0_CB = 3,
114 CID_VIG1_Y = 4,
115 CID_VIG1_CR = 5,
116 CID_VIG1_CB = 6,
117 CID_VIG2_Y = 7,
118 CID_VIG2_CR = 8,
119 CID_VIG2_CB = 9,
120 CID_DMA0_Y = 10,
121 CID_DMA0_CR = 11,
122 CID_DMA0_CB = 12,
123 CID_DMA1_Y = 13,
124 CID_DMA1_CR = 14,
125 CID_DMA1_CB = 15,
126 CID_RGB0 = 16,
127 CID_RGB1 = 17,
128 CID_RGB2 = 18,
129 CID_MAX = 19,
130};
131
132enum mdp5_igc_type {
133 IGC_VIG = 0,
134 IGC_RGB = 1,
135 IGC_DMA = 2,
136 IGC_DSPP = 3,
137};
138
139#define MDP5_IRQ_INTF0_WB_ROT_COMP 0x00000001
140#define MDP5_IRQ_INTF1_WB_ROT_COMP 0x00000002
141#define MDP5_IRQ_INTF2_WB_ROT_COMP 0x00000004
142#define MDP5_IRQ_INTF3_WB_ROT_COMP 0x00000008
143#define MDP5_IRQ_INTF0_WB_WFD 0x00000010
144#define MDP5_IRQ_INTF1_WB_WFD 0x00000020
145#define MDP5_IRQ_INTF2_WB_WFD 0x00000040
146#define MDP5_IRQ_INTF3_WB_WFD 0x00000080
147#define MDP5_IRQ_INTF0_PING_PONG_COMP 0x00000100
148#define MDP5_IRQ_INTF1_PING_PONG_COMP 0x00000200
149#define MDP5_IRQ_INTF2_PING_PONG_COMP 0x00000400
150#define MDP5_IRQ_INTF3_PING_PONG_COMP 0x00000800
151#define MDP5_IRQ_INTF0_PING_PONG_RD_PTR 0x00001000
152#define MDP5_IRQ_INTF1_PING_PONG_RD_PTR 0x00002000
153#define MDP5_IRQ_INTF2_PING_PONG_RD_PTR 0x00004000
154#define MDP5_IRQ_INTF3_PING_PONG_RD_PTR 0x00008000
155#define MDP5_IRQ_INTF0_PING_PONG_WR_PTR 0x00010000
156#define MDP5_IRQ_INTF1_PING_PONG_WR_PTR 0x00020000
157#define MDP5_IRQ_INTF2_PING_PONG_WR_PTR 0x00040000
158#define MDP5_IRQ_INTF3_PING_PONG_WR_PTR 0x00080000
159#define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF 0x00100000
160#define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF 0x00200000
161#define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF 0x00400000
162#define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF 0x00800000
163#define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000
164#define MDP5_IRQ_INTF0_VSYNC 0x02000000
165#define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000
166#define MDP5_IRQ_INTF1_VSYNC 0x08000000
167#define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000
168#define MDP5_IRQ_INTF2_VSYNC 0x20000000
169#define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000
170#define MDP5_IRQ_INTF3_VSYNC 0x80000000
171#define REG_MDP5_HW_VERSION 0x00000000
172
173#define REG_MDP5_HW_INTR_STATUS 0x00000010
174#define MDP5_HW_INTR_STATUS_INTR_MDP 0x00000001
175#define MDP5_HW_INTR_STATUS_INTR_DSI0 0x00000010
176#define MDP5_HW_INTR_STATUS_INTR_DSI1 0x00000020
177#define MDP5_HW_INTR_STATUS_INTR_HDMI 0x00000100
178#define MDP5_HW_INTR_STATUS_INTR_EDP 0x00001000
179
180#define REG_MDP5_MDP_VERSION 0x00000100
181#define MDP5_MDP_VERSION_MINOR__MASK 0x00ff0000
182#define MDP5_MDP_VERSION_MINOR__SHIFT 16
183static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val)
184{
185 return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK;
186}
187#define MDP5_MDP_VERSION_MAJOR__MASK 0xf0000000
188#define MDP5_MDP_VERSION_MAJOR__SHIFT 28
189static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val)
190{
191 return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK;
192}
193
194#define REG_MDP5_DISP_INTF_SEL 0x00000104
195#define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff
196#define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0
197static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val)
198{
199 return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK;
200}
201#define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00
202#define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8
203static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val)
204{
205 return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK;
206}
207#define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000
208#define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16
209static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val)
210{
211 return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK;
212}
213#define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000
214#define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24
215static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val)
216{
217 return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK;
218}
219
220#define REG_MDP5_INTR_EN 0x00000110
221
222#define REG_MDP5_INTR_STATUS 0x00000114
223
224#define REG_MDP5_INTR_CLEAR 0x00000118
225
226#define REG_MDP5_HIST_INTR_EN 0x0000011c
227
228#define REG_MDP5_HIST_INTR_STATUS 0x00000120
229
230#define REG_MDP5_HIST_INTR_CLEAR 0x00000124
231
232static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; }
233
234static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; }
235#define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff
236#define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0
237static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val)
238{
239 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK;
240}
241#define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00
242#define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8
243static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val)
244{
245 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK;
246}
247#define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000
248#define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16
249static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val)
250{
251 return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK;
252}
253
254static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; }
255
256static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; }
257#define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff
258#define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0
259static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val)
260{
261 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK;
262}
263#define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00
264#define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8
265static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val)
266{
267 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK;
268}
269#define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000
270#define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16
271static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val)
272{
273 return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK;
274}
275
276static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)
277{
278 switch (idx) {
279 case IGC_VIG: return 0x00000300;
280 case IGC_RGB: return 0x00000310;
281 case IGC_DMA: return 0x00000320;
282 case IGC_DSPP: return 0x00000400;
283 default: return INVALID_IDX(idx);
284 }
285}
286static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); }
287
288static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
289
290static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; }
291#define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff
292#define MDP5_IGC_LUT_REG_VAL__SHIFT 0
293static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val)
294{
295 return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK;
296}
297#define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000
298#define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000
299#define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000
300#define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000
301
302static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000600 + 0x100*i0; }
303
304static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; }
305
306static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; }
307#define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007
308#define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0
309static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)
310{
311 return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK;
312}
313#define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038
314#define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3
315static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)
316{
317 return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK;
318}
319#define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0
320#define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6
321static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)
322{
323 return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK;
324}
325#define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00
326#define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9
327static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)
328{
329 return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK;
330}
331#define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000
332#define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12
333static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)
334{
335 return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK;
336}
337#define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000
338#define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15
339static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)
340{
341 return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK;
342}
343#define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000
344#define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18
345static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)
346{
347 return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK;
348}
349#define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000
350#define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21
351static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)
352{
353 return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK;
354}
355#define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000
356#define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000
357
358static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000614 + 0x100*i0; }
359#define MDP5_CTL_OP_MODE__MASK 0x0000000f
360#define MDP5_CTL_OP_MODE__SHIFT 0
361static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)
362{
363 return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK;
364}
365#define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070
366#define MDP5_CTL_OP_INTF_NUM__SHIFT 4
367static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)
368{
369 return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK;
370}
371#define MDP5_CTL_OP_CMD_MODE 0x00020000
372#define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000
373#define MDP5_CTL_OP_PACK_3D__MASK 0x00300000
374#define MDP5_CTL_OP_PACK_3D__SHIFT 20
375static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)
376{
377 return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK;
378}
379
380static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000618 + 0x100*i0; }
381#define MDP5_CTL_FLUSH_VIG0 0x00000001
382#define MDP5_CTL_FLUSH_VIG1 0x00000002
383#define MDP5_CTL_FLUSH_VIG2 0x00000004
384#define MDP5_CTL_FLUSH_RGB0 0x00000008
385#define MDP5_CTL_FLUSH_RGB1 0x00000010
386#define MDP5_CTL_FLUSH_RGB2 0x00000020
387#define MDP5_CTL_FLUSH_LM0 0x00000040
388#define MDP5_CTL_FLUSH_LM1 0x00000080
389#define MDP5_CTL_FLUSH_LM2 0x00000100
390#define MDP5_CTL_FLUSH_DMA0 0x00000800
391#define MDP5_CTL_FLUSH_DMA1 0x00001000
392#define MDP5_CTL_FLUSH_DSPP0 0x00002000
393#define MDP5_CTL_FLUSH_DSPP1 0x00004000
394#define MDP5_CTL_FLUSH_DSPP2 0x00008000
395#define MDP5_CTL_FLUSH_CTL 0x00020000
396
397static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000061c + 0x100*i0; }
398
399static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000620 + 0x100*i0; }
400
401static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; }
402
403static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000014c4 + 0x400*i0; }
404
405static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000014f0 + 0x400*i0; }
406
407static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00001500 + 0x400*i0; }
408
409static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; }
410#define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000
411#define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16
412static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)
413{
414 return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK;
415}
416#define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff
417#define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0
418static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)
419{
420 return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK;
421}
422
423static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00001204 + 0x400*i0; }
424#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000
425#define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16
426static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)
427{
428 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK;
429}
430#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff
431#define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0
432static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)
433{
434 return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK;
435}
436
437static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00001208 + 0x400*i0; }
438#define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000
439#define MDP5_PIPE_SRC_XY_Y__SHIFT 16
440static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)
441{
442 return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK;
443}
444#define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff
445#define MDP5_PIPE_SRC_XY_X__SHIFT 0
446static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)
447{
448 return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK;
449}
450
451static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000120c + 0x400*i0; }
452#define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000
453#define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16
454static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)
455{
456 return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK;
457}
458#define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff
459#define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0
460static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)
461{
462 return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK;
463}
464
465static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00001210 + 0x400*i0; }
466#define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000
467#define MDP5_PIPE_OUT_XY_Y__SHIFT 16
468static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)
469{
470 return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK;
471}
472#define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff
473#define MDP5_PIPE_OUT_XY_X__SHIFT 0
474static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)
475{
476 return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK;
477}
478
479static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00001214 + 0x400*i0; }
480
481static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00001218 + 0x400*i0; }
482
483static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000121c + 0x400*i0; }
484
485static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00001220 + 0x400*i0; }
486
487static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00001224 + 0x400*i0; }
488#define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff
489#define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0
490static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)
491{
492 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK;
493}
494#define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000
495#define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16
496static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)
497{
498 return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK;
499}
500
501static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00001228 + 0x400*i0; }
502#define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff
503#define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0
504static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)
505{
506 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK;
507}
508#define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000
509#define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16
510static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)
511{
512 return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK;
513}
514
515static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000122c + 0x400*i0; }
516
517static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00001230 + 0x400*i0; }
518#define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003
519#define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0
520static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)
521{
522 return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK;
523}
524#define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c
525#define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2
526static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)
527{
528 return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK;
529}
530#define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030
531#define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4
532static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)
533{
534 return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK;
535}
536#define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0
537#define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6
538static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)
539{
540 return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK;
541}
542#define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100
543#define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600
544#define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9
545static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)
546{
547 return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK;
548}
549#define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800
550#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000
551#define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12
552static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)
553{
554 return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK;
555}
556#define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000
557#define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000
558#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00780000
559#define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19
560static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val)
561{
562 return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK;
563}
564#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000
565#define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23
566static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val)
567{
568 return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;
569}
570
571static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00001234 + 0x400*i0; }
572#define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff
573#define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0
574static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)
575{
576 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK;
577}
578#define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00
579#define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8
580static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)
581{
582 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK;
583}
584#define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000
585#define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16
586static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)
587{
588 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK;
589}
590#define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000
591#define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24
592static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)
593{
594 return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK;
595}
596
597static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00001238 + 0x400*i0; }
598#define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001
599#define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006
600#define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1
601static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)
602{
603 return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK;
604}
605#define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000
606#define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000
607#define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000
608#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000
609#define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000
610#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000
611#define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000
612
613static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000123c + 0x400*i0; }
614
615static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00001248 + 0x400*i0; }
616
617static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000124c + 0x400*i0; }
618
619static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00001250 + 0x400*i0; }
620
621static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00001254 + 0x400*i0; }
622
623static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00001258 + 0x400*i0; }
624
625static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00001270 + 0x400*i0; }
626
627static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000012a4 + 0x400*i0; }
628
629static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000012a8 + 0x400*i0; }
630
631static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000012ac + 0x400*i0; }
632
633static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000012b0 + 0x400*i0; }
634
635static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000012b4 + 0x400*i0; }
636#define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff
637#define MDP5_PIPE_DECIMATION_VERT__SHIFT 0
638static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)
639{
640 return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK;
641}
642#define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00
643#define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8
644static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)
645{
646 return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK;
647}
648
649static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00001404 + 0x400*i0; }
650#define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001
651#define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002
652#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300
653#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8
654static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)
655{
656 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK;
657}
658#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00
659#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10
660static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)
661{
662 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK;
663}
664#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000
665#define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12
666static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)
667{
668 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK;
669}
670#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000
671#define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14
672static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)
673{
674 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK;
675}
676#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000
677#define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16
678static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)
679{
680 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK;
681}
682#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000
683#define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18
684static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)
685{
686 return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK;
687}
688
689static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00001410 + 0x400*i0; }
690
691static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00001414 + 0x400*i0; }
692
693static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00001420 + 0x400*i0; }
694
695static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00001424 + 0x400*i0; }
696
697static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00003200 + 0x400*i0; }
698
699static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00003200 + 0x400*i0; }
700#define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002
701#define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004
702#define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008
703#define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010
704
705static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00003204 + 0x400*i0; }
706#define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000
707#define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16
708static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)
709{
710 return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK;
711}
712#define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff
713#define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0
714static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)
715{
716 return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK;
717}
718
719static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00003208 + 0x400*i0; }
720
721static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00003210 + 0x400*i0; }
722
723static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; }
724
725static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; }
726#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003
727#define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0
728static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)
729{
730 return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK;
731}
732#define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004
733#define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008
734#define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010
735#define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020
736#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300
737#define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8
738static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)
739{
740 return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK;
741}
742#define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400
743#define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800
744#define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000
745#define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000
746
747static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003224 + 0x400*i0 + 0x30*i1; }
748
749static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003228 + 0x400*i0 + 0x30*i1; }
750
751static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000322c + 0x400*i0 + 0x30*i1; }
752
753static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003230 + 0x400*i0 + 0x30*i1; }
754
755static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003234 + 0x400*i0 + 0x30*i1; }
756
757static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003238 + 0x400*i0 + 0x30*i1; }
758
759static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000323c + 0x400*i0 + 0x30*i1; }
760
761static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003240 + 0x400*i0 + 0x30*i1; }
762
763static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003244 + 0x400*i0 + 0x30*i1; }
764
765static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003248 + 0x400*i0 + 0x30*i1; }
766
767static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000032e0 + 0x400*i0; }
768
769static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000032e4 + 0x400*i0; }
770
771static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000032e8 + 0x400*i0; }
772
773static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000032dc + 0x400*i0; }
774
775static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000032ec + 0x400*i0; }
776
777static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000032f0 + 0x400*i0; }
778
779static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000032f4 + 0x400*i0; }
780
781static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000032f8 + 0x400*i0; }
782
783static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000032fc + 0x400*i0; }
784
785static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00003300 + 0x400*i0; }
786
787static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00003304 + 0x400*i0; }
788
789static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00003308 + 0x400*i0; }
790
791static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000330c + 0x400*i0; }
792
793static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00003310 + 0x400*i0; }
794
795static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00004600 + 0x400*i0; }
796
797static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00004600 + 0x400*i0; }
798#define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001
799#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e
800#define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1
801static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)
802{
803 return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK;
804}
805#define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010
806#define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100
807#define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000
808#define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000
809#define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000
810#define MDP5_DSPP_OP_MODE_PA_EN 0x00100000
811#define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000
812#define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000
813
814static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00004630 + 0x400*i0; }
815
816static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00004750 + 0x400*i0; }
817
818static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00004810 + 0x400*i0; }
819
820static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00004830 + 0x400*i0; }
821
822static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00004834 + 0x400*i0; }
823
824static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00004838 + 0x400*i0; }
825
826static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000048dc + 0x400*i0; }
827
828static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000048b0 + 0x400*i0; }
829
830static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00012500 + 0x200*i0; }
831
832static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00012500 + 0x200*i0; }
833
834static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00012504 + 0x200*i0; }
835
836static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00012508 + 0x200*i0; }
837#define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff
838#define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0
839static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)
840{
841 return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK;
842}
843#define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000
844#define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16
845static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)
846{
847 return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK;
848}
849
850static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0001250c + 0x200*i0; }
851
852static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00012510 + 0x200*i0; }
853
854static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00012514 + 0x200*i0; }
855
856static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00012518 + 0x200*i0; }
857
858static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0001251c + 0x200*i0; }
859
860static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00012520 + 0x200*i0; }
861
862static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00012524 + 0x200*i0; }
863
864static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00012528 + 0x200*i0; }
865
866static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0001252c + 0x200*i0; }
867#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff
868#define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0
869static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)
870{
871 return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK;
872}
873#define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000
874
875static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00012530 + 0x200*i0; }
876#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff
877#define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0
878static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)
879{
880 return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK;
881}
882
883static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00012534 + 0x200*i0; }
884
885static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00012538 + 0x200*i0; }
886
887static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0001253c + 0x200*i0; }
888#define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff
889#define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0
890static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)
891{
892 return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK;
893}
894#define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000
895#define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16
896static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)
897{
898 return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK;
899}
900
901static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00012540 + 0x200*i0; }
902#define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff
903#define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0
904static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)
905{
906 return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK;
907}
908#define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000
909#define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16
910static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)
911{
912 return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK;
913}
914#define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000
915
916static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00012544 + 0x200*i0; }
917
918static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00012548 + 0x200*i0; }
919
920static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0001254c + 0x200*i0; }
921
922static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00012550 + 0x200*i0; }
923#define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001
924#define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002
925#define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004
926
927static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00012554 + 0x200*i0; }
928
929static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00012558 + 0x200*i0; }
930
931static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0001255c + 0x200*i0; }
932
933static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00012584 + 0x200*i0; }
934
935static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00012590 + 0x200*i0; }
936
937static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000125a8 + 0x200*i0; }
938
939static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000125ac + 0x200*i0; }
940
941static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000125b0 + 0x200*i0; }
942
943static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000125f0 + 0x200*i0; }
944
945static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000125f4 + 0x200*i0; }
946
947static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000125f8 + 0x200*i0; }
948
949static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00012600 + 0x200*i0; }
950
951static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00012604 + 0x200*i0; }
952
953static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00012608 + 0x200*i0; }
954
955static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0001260c + 0x200*i0; }
956
957static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00012610 + 0x200*i0; }
958
959static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00012614 + 0x200*i0; }
960
961static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00012618 + 0x200*i0; }
962
963static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0001261c + 0x200*i0; }
964
965static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00013100 + 0x200*i0; }
966
967static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00013100 + 0x200*i0; }
968
969static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00013104 + 0x200*i0; }
970
971static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00013108 + 0x200*i0; }
972
973static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0001310c + 0x200*i0; }
974
975static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00013110 + 0x200*i0; }
976
977static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00013114 + 0x200*i0; }
978
979static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00013118 + 0x200*i0; }
980
981static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0001311c + 0x200*i0; }
982
983static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00013120 + 0x200*i0; }
984
985static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00013124 + 0x200*i0; }
986
987static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00013128 + 0x200*i0; }
988
989static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0001312c + 0x200*i0; }
990
991static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00013130 + 0x200*i0; }
992
993static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00013134 + 0x200*i0; }
994
995static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00013138 + 0x200*i0; }
996
997static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0001317c + 0x200*i0; }
998
999static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000131c8 + 0x200*i0; }
1000
1001static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000131cc + 0x200*i0; }
1002
1003static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000131d0 + 0x200*i0; }
1004
1005static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000131d4 + 0x200*i0; }
1006
1007static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000131d8 + 0x200*i0; }
1008
1009static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000131dc + 0x200*i0; }
1010
1011static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000131e0 + 0x200*i0; }
1012
1013static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000131e8 + 0x200*i0; }
1014
1015static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000131ec + 0x200*i0; }
1016
1017static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000131f0 + 0x200*i0; }
1018
1019static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000131f4 + 0x200*i0; }
1020
1021static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000131f8 + 0x200*i0; }
1022
1023static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00013200 + 0x200*i0; }
1024
1025static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00013244 + 0x200*i0; }
1026
1027static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00013248 + 0x200*i0; }
1028
1029static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0001324c + 0x200*i0; }
1030
1031static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00013254 + 0x200*i0; }
1032
1033static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00013258 + 0x200*i0; }
1034
1035
1036#endif /* MDP5_XML */
diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
new file mode 100644
index 000000000000..a9629b85b983
--- /dev/null
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -0,0 +1,78 @@
1#ifndef MDP_COMMON_XML
2#define MDP_COMMON_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
21
22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark)
24
25Permission is hereby granted, free of charge, to any person obtaining
26a copy of this software and associated documentation files (the
27"Software"), to deal in the Software without restriction, including
28without limitation the rights to use, copy, modify, merge, publish,
29distribute, sublicense, and/or sell copies of the Software, and to
30permit persons to whom the Software is furnished to do so, subject to
31the following conditions:
32
33The above copyright notice and this permission notice (including the
34next paragraph) shall be included in all copies or substantial
35portions of the Software.
36
37THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44*/
45
46
47enum mdp_mixer_stage_id {
48 STAGE_UNUSED = 0,
49 STAGE_BASE = 1,
50 STAGE0 = 2,
51 STAGE1 = 3,
52 STAGE2 = 4,
53 STAGE3 = 5,
54};
55
56enum mdp_alpha_type {
57 FG_CONST = 0,
58 BG_CONST = 1,
59 FG_PIXEL = 2,
60 BG_PIXEL = 3,
61};
62
63enum mdp_bpc {
64 BPC1 = 0,
65 BPC5 = 1,
66 BPC6 = 2,
67 BPC8 = 3,
68};
69
70enum mdp_bpc_alpha {
71 BPC1A = 0,
72 BPC4A = 1,
73 BPC6A = 2,
74 BPC8A = 3,
75};
76
77
78#endif /* MDP_COMMON_XML */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 06:57:26 -0500