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authorBen Widawsky <ben@bwidawsk.net>2012-10-03 22:34:24 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-10-04 12:44:13 -0400
commitf8f2ac9a76b0f80a6763ca316116a7bab8486997 (patch)
tree415fc24b7f28eba79d1818abf9df1b42eedd4c66 /drivers/gpu/drm
parent95cb1b02b0f8e690cbcc479924573b4fb26c2e8f (diff)
drm/i915: Fix GT_MODE default value
I can't even find how I figured this might be needed anymore. But sure enough, the value I'm reading back on platforms doesn't match what the docs recommends. It seemed to fix Chris' GT1 in limited testing as well. Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@vger.kernel.org Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
2 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7637824c6a7d..64c1be0a9cfd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -527,6 +527,9 @@
527# define VS_TIMER_DISPATCH (1 << 6) 527# define VS_TIMER_DISPATCH (1 << 6)
528# define MI_FLUSH_ENABLE (1 << 12) 528# define MI_FLUSH_ENABLE (1 << 12)
529 529
530#define GEN6_GT_MODE 0x20d0
531#define GEN6_GT_MODE_HI (1 << 9)
532
530#define GFX_MODE 0x02520 533#define GFX_MODE 0x02520
531#define GFX_MODE_GEN7 0x0229c 534#define GFX_MODE_GEN7 0x0229c
532#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c) 535#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d69f8f49beb5..b3b4b6cea8b0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3474,6 +3474,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
3474 DISPPLANE_TRICKLE_FEED_DISABLE); 3474 DISPPLANE_TRICKLE_FEED_DISABLE);
3475 intel_flush_display_plane(dev_priv, pipe); 3475 intel_flush_display_plane(dev_priv, pipe);
3476 } 3476 }
3477
3478 /* The default value should be 0x200 according to docs, but the two
3479 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3480 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3481 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3477} 3482}
3478 3483
3479static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 3484static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)