diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-07-25 19:28:25 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-07-25 21:43:57 -0400 |
commit | ee2e013131dcf6427334663662dbe760ccdba735 (patch) | |
tree | 2533973de31a05dbb06465a124087334842c6f37 /drivers/gpu/drm | |
parent | bf563a6b7c7efb283dd4ddf12cc90c2898195c16 (diff) |
drm/nouveau: introduce gpio engine
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/nouveau/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bios.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_dp.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_state.c | 41 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_dac.c | 13 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv10_gpio.c (renamed from drivers/gpu/drm/nouveau/nv17_gpio.c) | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv17_tv.c | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_gpio.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_mc.c | 13 |
11 files changed, 100 insertions, 38 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile index b6ed6051ed3f..2405d5ef0ca7 100644 --- a/drivers/gpu/drm/nouveau/Makefile +++ b/drivers/gpu/drm/nouveau/Makefile | |||
@@ -22,7 +22,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ | |||
22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ | 22 | nv50_cursor.o nv50_display.o nv50_fbcon.o \ |
23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ | 23 | nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ |
24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ | 24 | nv04_crtc.o nv04_display.o nv04_cursor.o nv04_fbcon.o \ |
25 | nv17_gpio.o nv50_gpio.o \ | 25 | nv10_gpio.o nv50_gpio.o \ |
26 | nv50_calc.o | 26 | nv50_calc.o |
27 | 27 | ||
28 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o | 28 | nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o |
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 40231cea465e..b59f348f14fc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c | |||
@@ -3136,6 +3136,7 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |||
3136 | */ | 3136 | */ |
3137 | 3137 | ||
3138 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; | 3138 | struct drm_nouveau_private *dev_priv = bios->dev->dev_private; |
3139 | struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; | ||
3139 | const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; | 3140 | const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c }; |
3140 | int i; | 3141 | int i; |
3141 | 3142 | ||
@@ -3156,7 +3157,7 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |||
3156 | BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", | 3157 | BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n", |
3157 | offset, gpio->tag, gpio->state_default); | 3158 | offset, gpio->tag, gpio->state_default); |
3158 | if (bios->execute) | 3159 | if (bios->execute) |
3159 | nv50_gpio_set(bios->dev, gpio->tag, gpio->state_default); | 3160 | pgpio->set(bios->dev, gpio->tag, gpio->state_default); |
3160 | 3161 | ||
3161 | /* The NVIDIA binary driver doesn't appear to actually do | 3162 | /* The NVIDIA binary driver doesn't appear to actually do |
3162 | * any of this, my VBIOS does however. | 3163 | * any of this, my VBIOS does however. |
diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index 64b43958e582..33742b11188b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c | |||
@@ -272,6 +272,8 @@ bool | |||
272 | nouveau_dp_link_train(struct drm_encoder *encoder) | 272 | nouveau_dp_link_train(struct drm_encoder *encoder) |
273 | { | 273 | { |
274 | struct drm_device *dev = encoder->dev; | 274 | struct drm_device *dev = encoder->dev; |
275 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
276 | struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; | ||
275 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | 277 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
276 | struct nouveau_connector *nv_connector; | 278 | struct nouveau_connector *nv_connector; |
277 | struct bit_displayport_encoder_table *dpe; | 279 | struct bit_displayport_encoder_table *dpe; |
@@ -295,7 +297,7 @@ nouveau_dp_link_train(struct drm_encoder *encoder) | |||
295 | /* disable hotplug detect, this flips around on some panels during | 297 | /* disable hotplug detect, this flips around on some panels during |
296 | * link training. | 298 | * link training. |
297 | */ | 299 | */ |
298 | nv50_gpio_irq_enable(dev, nv_connector->dcb->gpio_tag, false); | 300 | pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false); |
299 | 301 | ||
300 | if (dpe->script0) { | 302 | if (dpe->script0) { |
301 | NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); | 303 | NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or); |
@@ -436,7 +438,7 @@ stop: | |||
436 | } | 438 | } |
437 | 439 | ||
438 | /* re-enable hotplug detect */ | 440 | /* re-enable hotplug detect */ |
439 | nv50_gpio_irq_enable(dev, nv_connector->dcb->gpio_tag, true); | 441 | pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true); |
440 | 442 | ||
441 | return eq_done; | 443 | return eq_done; |
442 | } | 444 | } |
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 0687e6ab9187..d0a35d9ba522 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -359,6 +359,16 @@ struct nouveau_display_engine { | |||
359 | void (*destroy)(struct drm_device *); | 359 | void (*destroy)(struct drm_device *); |
360 | }; | 360 | }; |
361 | 361 | ||
362 | struct nouveau_gpio_engine { | ||
363 | int (*init)(struct drm_device *); | ||
364 | void (*takedown)(struct drm_device *); | ||
365 | |||
366 | int (*get)(struct drm_device *, enum dcb_gpio_tag); | ||
367 | int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); | ||
368 | |||
369 | void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); | ||
370 | }; | ||
371 | |||
362 | struct nouveau_engine { | 372 | struct nouveau_engine { |
363 | struct nouveau_instmem_engine instmem; | 373 | struct nouveau_instmem_engine instmem; |
364 | struct nouveau_mc_engine mc; | 374 | struct nouveau_mc_engine mc; |
@@ -367,6 +377,7 @@ struct nouveau_engine { | |||
367 | struct nouveau_pgraph_engine graph; | 377 | struct nouveau_pgraph_engine graph; |
368 | struct nouveau_fifo_engine fifo; | 378 | struct nouveau_fifo_engine fifo; |
369 | struct nouveau_display_engine display; | 379 | struct nouveau_display_engine display; |
380 | struct nouveau_gpio_engine gpio; | ||
370 | }; | 381 | }; |
371 | 382 | ||
372 | struct nouveau_pll_vals { | 383 | struct nouveau_pll_vals { |
@@ -1149,11 +1160,12 @@ extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |||
1149 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | 1160 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, |
1150 | struct drm_file *); | 1161 | struct drm_file *); |
1151 | 1162 | ||
1152 | /* nv17_gpio.c */ | 1163 | /* nv10_gpio.c */ |
1153 | int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | 1164 | int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1154 | int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | 1165 | int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); |
1155 | 1166 | ||
1156 | /* nv50_gpio.c */ | 1167 | /* nv50_gpio.c */ |
1168 | int nv50_gpio_init(struct drm_device *dev); | ||
1157 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | 1169 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1158 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | 1170 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); |
1159 | void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); | 1171 | void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); |
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c index 17176ad5b22a..ee3729e7823b 100644 --- a/drivers/gpu/drm/nouveau/nouveau_state.c +++ b/drivers/gpu/drm/nouveau/nouveau_state.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include "nv50_display.h" | 38 | #include "nv50_display.h" |
39 | 39 | ||
40 | static void nouveau_stub_takedown(struct drm_device *dev) {} | 40 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
41 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } | ||
41 | 42 | ||
42 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | 43 | static int nouveau_init_engine_ptrs(struct drm_device *dev) |
43 | { | 44 | { |
@@ -89,6 +90,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
89 | engine->display.create = nv04_display_create; | 90 | engine->display.create = nv04_display_create; |
90 | engine->display.init = nv04_display_init; | 91 | engine->display.init = nv04_display_init; |
91 | engine->display.destroy = nv04_display_destroy; | 92 | engine->display.destroy = nv04_display_destroy; |
93 | engine->gpio.init = nouveau_stub_init; | ||
94 | engine->gpio.takedown = nouveau_stub_takedown; | ||
95 | engine->gpio.get = NULL; | ||
96 | engine->gpio.set = NULL; | ||
97 | engine->gpio.irq_enable = NULL; | ||
92 | break; | 98 | break; |
93 | case 0x10: | 99 | case 0x10: |
94 | engine->instmem.init = nv04_instmem_init; | 100 | engine->instmem.init = nv04_instmem_init; |
@@ -136,6 +142,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
136 | engine->display.create = nv04_display_create; | 142 | engine->display.create = nv04_display_create; |
137 | engine->display.init = nv04_display_init; | 143 | engine->display.init = nv04_display_init; |
138 | engine->display.destroy = nv04_display_destroy; | 144 | engine->display.destroy = nv04_display_destroy; |
145 | engine->gpio.init = nouveau_stub_init; | ||
146 | engine->gpio.takedown = nouveau_stub_takedown; | ||
147 | engine->gpio.get = nv10_gpio_get; | ||
148 | engine->gpio.set = nv10_gpio_set; | ||
149 | engine->gpio.irq_enable = NULL; | ||
139 | break; | 150 | break; |
140 | case 0x20: | 151 | case 0x20: |
141 | engine->instmem.init = nv04_instmem_init; | 152 | engine->instmem.init = nv04_instmem_init; |
@@ -183,6 +194,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
183 | engine->display.create = nv04_display_create; | 194 | engine->display.create = nv04_display_create; |
184 | engine->display.init = nv04_display_init; | 195 | engine->display.init = nv04_display_init; |
185 | engine->display.destroy = nv04_display_destroy; | 196 | engine->display.destroy = nv04_display_destroy; |
197 | engine->gpio.init = nouveau_stub_init; | ||
198 | engine->gpio.takedown = nouveau_stub_takedown; | ||
199 | engine->gpio.get = nv10_gpio_get; | ||
200 | engine->gpio.set = nv10_gpio_set; | ||
201 | engine->gpio.irq_enable = NULL; | ||
186 | break; | 202 | break; |
187 | case 0x30: | 203 | case 0x30: |
188 | engine->instmem.init = nv04_instmem_init; | 204 | engine->instmem.init = nv04_instmem_init; |
@@ -230,6 +246,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
230 | engine->display.create = nv04_display_create; | 246 | engine->display.create = nv04_display_create; |
231 | engine->display.init = nv04_display_init; | 247 | engine->display.init = nv04_display_init; |
232 | engine->display.destroy = nv04_display_destroy; | 248 | engine->display.destroy = nv04_display_destroy; |
249 | engine->gpio.init = nouveau_stub_init; | ||
250 | engine->gpio.takedown = nouveau_stub_takedown; | ||
251 | engine->gpio.get = nv10_gpio_get; | ||
252 | engine->gpio.set = nv10_gpio_set; | ||
253 | engine->gpio.irq_enable = NULL; | ||
233 | break; | 254 | break; |
234 | case 0x40: | 255 | case 0x40: |
235 | case 0x60: | 256 | case 0x60: |
@@ -278,6 +299,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
278 | engine->display.create = nv04_display_create; | 299 | engine->display.create = nv04_display_create; |
279 | engine->display.init = nv04_display_init; | 300 | engine->display.init = nv04_display_init; |
280 | engine->display.destroy = nv04_display_destroy; | 301 | engine->display.destroy = nv04_display_destroy; |
302 | engine->gpio.init = nouveau_stub_init; | ||
303 | engine->gpio.takedown = nouveau_stub_takedown; | ||
304 | engine->gpio.get = nv10_gpio_get; | ||
305 | engine->gpio.set = nv10_gpio_set; | ||
306 | engine->gpio.irq_enable = NULL; | ||
281 | break; | 307 | break; |
282 | case 0x50: | 308 | case 0x50: |
283 | case 0x80: /* gotta love NVIDIA's consistency.. */ | 309 | case 0x80: /* gotta love NVIDIA's consistency.. */ |
@@ -327,6 +353,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) | |||
327 | engine->display.create = nv50_display_create; | 353 | engine->display.create = nv50_display_create; |
328 | engine->display.init = nv50_display_init; | 354 | engine->display.init = nv50_display_init; |
329 | engine->display.destroy = nv50_display_destroy; | 355 | engine->display.destroy = nv50_display_destroy; |
356 | engine->gpio.init = nv50_gpio_init; | ||
357 | engine->gpio.takedown = nouveau_stub_takedown; | ||
358 | engine->gpio.get = nv50_gpio_get; | ||
359 | engine->gpio.set = nv50_gpio_set; | ||
360 | engine->gpio.irq_enable = nv50_gpio_irq_enable; | ||
330 | break; | 361 | break; |
331 | default: | 362 | default: |
332 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | 363 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); |
@@ -485,10 +516,15 @@ nouveau_card_init(struct drm_device *dev) | |||
485 | if (ret) | 516 | if (ret) |
486 | goto out_gpuobj; | 517 | goto out_gpuobj; |
487 | 518 | ||
519 | /* PGPIO */ | ||
520 | ret = engine->gpio.init(dev); | ||
521 | if (ret) | ||
522 | goto out_mc; | ||
523 | |||
488 | /* PTIMER */ | 524 | /* PTIMER */ |
489 | ret = engine->timer.init(dev); | 525 | ret = engine->timer.init(dev); |
490 | if (ret) | 526 | if (ret) |
491 | goto out_mc; | 527 | goto out_gpio; |
492 | 528 | ||
493 | /* PFB */ | 529 | /* PFB */ |
494 | ret = engine->fb.init(dev); | 530 | ret = engine->fb.init(dev); |
@@ -554,6 +590,8 @@ out_fb: | |||
554 | engine->fb.takedown(dev); | 590 | engine->fb.takedown(dev); |
555 | out_timer: | 591 | out_timer: |
556 | engine->timer.takedown(dev); | 592 | engine->timer.takedown(dev); |
593 | out_gpio: | ||
594 | engine->gpio.takedown(dev); | ||
557 | out_mc: | 595 | out_mc: |
558 | engine->mc.takedown(dev); | 596 | engine->mc.takedown(dev); |
559 | out_gpuobj: | 597 | out_gpuobj: |
@@ -592,6 +630,7 @@ static void nouveau_card_takedown(struct drm_device *dev) | |||
592 | } | 630 | } |
593 | engine->fb.takedown(dev); | 631 | engine->fb.takedown(dev); |
594 | engine->timer.takedown(dev); | 632 | engine->timer.takedown(dev); |
633 | engine->gpio.takedown(dev); | ||
595 | engine->mc.takedown(dev); | 634 | engine->mc.takedown(dev); |
596 | engine->display.late_takedown(dev); | 635 | engine->display.late_takedown(dev); |
597 | 636 | ||
diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c index 2d0fee5f09ce..ea3627041ecf 100644 --- a/drivers/gpu/drm/nouveau/nv04_dac.c +++ b/drivers/gpu/drm/nouveau/nv04_dac.c | |||
@@ -220,6 +220,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
220 | { | 220 | { |
221 | struct drm_device *dev = encoder->dev; | 221 | struct drm_device *dev = encoder->dev; |
222 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 222 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
223 | struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio; | ||
223 | struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; | 224 | struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; |
224 | uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); | 225 | uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); |
225 | uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, | 226 | uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, |
@@ -251,11 +252,11 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
251 | nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); | 252 | nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); |
252 | } | 253 | } |
253 | 254 | ||
254 | saved_gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1); | 255 | saved_gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1); |
255 | saved_gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0); | 256 | saved_gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0); |
256 | 257 | ||
257 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, dcb->type == OUTPUT_TV); | 258 | gpio->set(dev, DCB_GPIO_TVDAC1, dcb->type == OUTPUT_TV); |
258 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, dcb->type == OUTPUT_TV); | 259 | gpio->set(dev, DCB_GPIO_TVDAC0, dcb->type == OUTPUT_TV); |
259 | 260 | ||
260 | msleep(4); | 261 | msleep(4); |
261 | 262 | ||
@@ -303,8 +304,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) | |||
303 | nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); | 304 | nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); |
304 | nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); | 305 | nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); |
305 | 306 | ||
306 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, saved_gpio1); | 307 | gpio->set(dev, DCB_GPIO_TVDAC1, saved_gpio1); |
307 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, saved_gpio0); | 308 | gpio->set(dev, DCB_GPIO_TVDAC0, saved_gpio0); |
308 | 309 | ||
309 | return sample; | 310 | return sample; |
310 | } | 311 | } |
diff --git a/drivers/gpu/drm/nouveau/nv17_gpio.c b/drivers/gpu/drm/nouveau/nv10_gpio.c index 2e58c331e9b7..007fc29e2f86 100644 --- a/drivers/gpu/drm/nouveau/nv17_gpio.c +++ b/drivers/gpu/drm/nouveau/nv10_gpio.c | |||
@@ -55,7 +55,7 @@ get_gpio_location(struct dcb_gpio_entry *ent, uint32_t *reg, uint32_t *shift, | |||
55 | } | 55 | } |
56 | 56 | ||
57 | int | 57 | int |
58 | nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) | 58 | nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) |
59 | { | 59 | { |
60 | struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); | 60 | struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); |
61 | uint32_t reg, shift, mask, value; | 61 | uint32_t reg, shift, mask, value; |
@@ -72,7 +72,7 @@ nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) | |||
72 | } | 72 | } |
73 | 73 | ||
74 | int | 74 | int |
75 | nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) | 75 | nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) |
76 | { | 76 | { |
77 | struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); | 77 | struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); |
78 | uint32_t reg, shift, mask, value; | 78 | uint32_t reg, shift, mask, value; |
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c index bb3a284c31e5..44fefb0c7083 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.c +++ b/drivers/gpu/drm/nouveau/nv17_tv.c | |||
@@ -37,6 +37,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) | |||
37 | { | 37 | { |
38 | struct drm_device *dev = encoder->dev; | 38 | struct drm_device *dev = encoder->dev; |
39 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 39 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
40 | struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio; | ||
40 | uint32_t testval, regoffset = nv04_dac_output_offset(encoder); | 41 | uint32_t testval, regoffset = nv04_dac_output_offset(encoder); |
41 | uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, | 42 | uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, |
42 | fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; | 43 | fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; |
@@ -52,8 +53,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) | |||
52 | head = (dacclk & 0x100) >> 8; | 53 | head = (dacclk & 0x100) >> 8; |
53 | 54 | ||
54 | /* Save the previous state. */ | 55 | /* Save the previous state. */ |
55 | gpio1 = nv17_gpio_get(dev, DCB_GPIO_TVDAC1); | 56 | gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1); |
56 | gpio0 = nv17_gpio_get(dev, DCB_GPIO_TVDAC0); | 57 | gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0); |
57 | fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); | 58 | fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); |
58 | fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); | 59 | fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); |
59 | fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); | 60 | fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); |
@@ -64,8 +65,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) | |||
64 | ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); | 65 | ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); |
65 | 66 | ||
66 | /* Prepare the DAC for load detection. */ | 67 | /* Prepare the DAC for load detection. */ |
67 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, true); | 68 | gpio->set(dev, DCB_GPIO_TVDAC1, true); |
68 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, true); | 69 | gpio->set(dev, DCB_GPIO_TVDAC0, true); |
69 | 70 | ||
70 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); | 71 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); |
71 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); | 72 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); |
@@ -110,8 +111,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) | |||
110 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); | 111 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); |
111 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); | 112 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); |
112 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); | 113 | NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); |
113 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, gpio1); | 114 | gpio->set(dev, DCB_GPIO_TVDAC1, gpio1); |
114 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, gpio0); | 115 | gpio->set(dev, DCB_GPIO_TVDAC0, gpio0); |
115 | 116 | ||
116 | return sample; | 117 | return sample; |
117 | } | 118 | } |
@@ -335,6 +336,8 @@ static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, | |||
335 | static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) | 336 | static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) |
336 | { | 337 | { |
337 | struct drm_device *dev = encoder->dev; | 338 | struct drm_device *dev = encoder->dev; |
339 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
340 | struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio; | ||
338 | struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; | 341 | struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; |
339 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); | 342 | struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); |
340 | 343 | ||
@@ -359,8 +362,8 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) | |||
359 | 362 | ||
360 | nv_load_ptv(dev, regs, 200); | 363 | nv_load_ptv(dev, regs, 200); |
361 | 364 | ||
362 | nv17_gpio_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON); | 365 | gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON); |
363 | nv17_gpio_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON); | 366 | gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON); |
364 | 367 | ||
365 | nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); | 368 | nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); |
366 | } | 369 | } |
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 13a448985637..0ab868722114 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -193,6 +193,7 @@ nv50_display_init(struct drm_device *dev) | |||
193 | { | 193 | { |
194 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 194 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
195 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | 195 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; |
196 | struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; | ||
196 | struct nouveau_channel *evo = dev_priv->evo; | 197 | struct nouveau_channel *evo = dev_priv->evo; |
197 | struct drm_connector *connector; | 198 | struct drm_connector *connector; |
198 | uint32_t val, ram_amount; | 199 | uint32_t val, ram_amount; |
@@ -379,7 +380,7 @@ nv50_display_init(struct drm_device *dev) | |||
379 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | 380 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
380 | struct nouveau_connector *conn = nouveau_connector(connector); | 381 | struct nouveau_connector *conn = nouveau_connector(connector); |
381 | 382 | ||
382 | nv50_gpio_irq_enable(dev, conn->dcb->gpio_tag, true); | 383 | pgpio->irq_enable(dev, conn->dcb->gpio_tag, true); |
383 | } | 384 | } |
384 | 385 | ||
385 | return 0; | 386 | return 0; |
diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c index 88715c5003c1..b2fab2bf3d61 100644 --- a/drivers/gpu/drm/nouveau/nv50_gpio.c +++ b/drivers/gpu/drm/nouveau/nv50_gpio.c | |||
@@ -93,3 +93,19 @@ nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on) | |||
93 | nv_wr32(dev, reg + 4, mask); | 93 | nv_wr32(dev, reg + 4, mask); |
94 | nv_mask(dev, reg + 0, mask, on ? mask : 0); | 94 | nv_mask(dev, reg + 0, mask, on ? mask : 0); |
95 | } | 95 | } |
96 | |||
97 | int | ||
98 | nv50_gpio_init(struct drm_device *dev) | ||
99 | { | ||
100 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
101 | |||
102 | /* disable, and ack any pending gpio interrupts */ | ||
103 | nv_wr32(dev, 0xe050, 0x00000000); | ||
104 | nv_wr32(dev, 0xe054, 0xffffffff); | ||
105 | if (dev_priv->chipset >= 0x90) { | ||
106 | nv_wr32(dev, 0xe070, 0x00000000); | ||
107 | nv_wr32(dev, 0xe074, 0xffffffff); | ||
108 | } | ||
109 | |||
110 | return 0; | ||
111 | } | ||
diff --git a/drivers/gpu/drm/nouveau/nv50_mc.c b/drivers/gpu/drm/nouveau/nv50_mc.c index f680e8e121b1..e0a9c3faa202 100644 --- a/drivers/gpu/drm/nouveau/nv50_mc.c +++ b/drivers/gpu/drm/nouveau/nv50_mc.c | |||
@@ -31,20 +31,7 @@ | |||
31 | int | 31 | int |
32 | nv50_mc_init(struct drm_device *dev) | 32 | nv50_mc_init(struct drm_device *dev) |
33 | { | 33 | { |
34 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
35 | |||
36 | nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); | 34 | nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); |
37 | |||
38 | /* disable, and ack any pending gpio interrupts | ||
39 | * XXX doesn't technically belong here, but it'll do for the moment | ||
40 | */ | ||
41 | nv_wr32(dev, 0xe050, 0x00000000); | ||
42 | nv_wr32(dev, 0xe054, 0xffffffff); | ||
43 | if (dev_priv->chipset >= 0x90) { | ||
44 | nv_wr32(dev, 0xe070, 0x00000000); | ||
45 | nv_wr32(dev, 0xe074, 0xffffffff); | ||
46 | } | ||
47 | |||
48 | return 0; | 35 | return 0; |
49 | } | 36 | } |
50 | 37 | ||