diff options
author | Ben Widawsky <benjamin.widawsky@intel.com> | 2012-07-24 23:47:31 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-25 12:23:56 -0400 |
commit | e1ef7cc299839e68dae3f1843f62e52acda04538 (patch) | |
tree | bebf6699022aa920bcbb02adf3c2536194f225f4 /drivers/gpu/drm | |
parent | 2e4291e0bc6cff9514515a899a8158ea62b3ff90 (diff) |
drm/i915: Macro to determine DPF support
Originally I had a macro specifically for DPF support, and Daniel, with
good reason asked me to change it to this. It's not the way I would have
gone (and indeed I didn't), but for now there is no distinction as all
platforms with L3 also have DPF.
Note: The good reasons are that dpf is a l3$ feature (at least on
currrent hw), hence I don't expect one to go without the other.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: added note]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_sysfs.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 6 |
4 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f1765893da60..35a90da64149 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1114,6 +1114,8 @@ struct drm_i915_file_private { | |||
1114 | 1114 | ||
1115 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) | 1115 | #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) |
1116 | 1116 | ||
1117 | #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev)) | ||
1118 | |||
1117 | #include "i915_trace.h" | 1119 | #include "i915_trace.h" |
1118 | 1120 | ||
1119 | /** | 1121 | /** |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 41ed41d70472..440c9051aa9b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -444,7 +444,7 @@ static void ivybridge_handle_parity_error(struct drm_device *dev) | |||
444 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 444 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
445 | unsigned long flags; | 445 | unsigned long flags; |
446 | 446 | ||
447 | if (!IS_IVYBRIDGE(dev)) | 447 | if (!HAS_L3_GPU_CACHE(dev)) |
448 | return; | 448 | return; |
449 | 449 | ||
450 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | 450 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 2f5388af8df9..77a97bfabb6b 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c | |||
@@ -212,7 +212,7 @@ void i915_setup_sysfs(struct drm_device *dev) | |||
212 | DRM_ERROR("RC6 residency sysfs setup failed\n"); | 212 | DRM_ERROR("RC6 residency sysfs setup failed\n"); |
213 | } | 213 | } |
214 | 214 | ||
215 | if (IS_IVYBRIDGE(dev)) { | 215 | if (HAS_L3_GPU_CACHE(dev)) { |
216 | ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs); | 216 | ret = device_create_bin_file(&dev->primary->kdev, &dpf_attrs); |
217 | if (ret) | 217 | if (ret) |
218 | DRM_ERROR("l3 parity sysfs setup failed\n"); | 218 | DRM_ERROR("l3 parity sysfs setup failed\n"); |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 8b7085e4cf84..c58f1b91d08b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -454,7 +454,7 @@ static int init_render_ring(struct intel_ring_buffer *ring) | |||
454 | if (INTEL_INFO(dev)->gen >= 6) | 454 | if (INTEL_INFO(dev)->gen >= 6) |
455 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | 455 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
456 | 456 | ||
457 | if (IS_IVYBRIDGE(dev)) | 457 | if (HAS_L3_GPU_CACHE(dev)) |
458 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); | 458 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
459 | 459 | ||
460 | return ret; | 460 | return ret; |
@@ -844,7 +844,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) | |||
844 | 844 | ||
845 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | 845 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
846 | if (ring->irq_refcount++ == 0) { | 846 | if (ring->irq_refcount++ == 0) { |
847 | if (IS_IVYBRIDGE(dev) && ring->id == RCS) | 847 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
848 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | | 848 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | |
849 | GEN6_RENDER_L3_PARITY_ERROR)); | 849 | GEN6_RENDER_L3_PARITY_ERROR)); |
850 | else | 850 | else |
@@ -867,7 +867,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) | |||
867 | 867 | ||
868 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | 868 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
869 | if (--ring->irq_refcount == 0) { | 869 | if (--ring->irq_refcount == 0) { |
870 | if (IS_IVYBRIDGE(dev) && ring->id == RCS) | 870 | if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS) |
871 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); | 871 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); |
872 | else | 872 | else |
873 | I915_WRITE_IMR(ring, ~0); | 873 | I915_WRITE_IMR(ring, ~0); |