drm/radeon/audio: set up the sads on DCE3.2 asics

This sets up the short audio descriptors properly on
DCE3.2 asics for hdmi audio.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 94 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 6d7128d02493..f443010ce90b 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -322,6 +322,68 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
         kfree(sadb);
 }
 
+static void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder)
+{
+        struct radeon_device *rdev = encoder->dev->dev_private;
+        struct drm_connector *connector;
+        struct radeon_connector *radeon_connector = NULL;
+        struct cea_sad *sads;
+        int i, sad_count;
+
+        static const u16 eld_reg_to_type[][2] = {
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
+                { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
+        };
+
+        list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
+                if (connector->encoder == encoder)
+                        radeon_connector = to_radeon_connector(connector);
+        }
+
+        if (!radeon_connector) {
+                DRM_ERROR("Couldn't find encoder's connector\n");
+                return;
+        }
+
+        sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
+        if (sad_count < 0) {
+                DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
+                return;
+        }
+        BUG_ON(!sads);
+
+        for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
+                u32 value = 0;
+                int j;
+
+                for (j = 0; j < sad_count; j++) {
+                        struct cea_sad *sad = &sads[j];
+
+                        if (sad->format == eld_reg_to_type[i][1]) {
+                                value = MAX_CHANNELS(sad->channels) |
+                                        DESCRIPTOR_BYTE_2(sad->byte2) |
+                                        SUPPORTED_FREQUENCIES(sad->freq);
+                                if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
+                                        value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
+                                break;
+                        }
+                }
+                WREG32(eld_reg_to_type[i][0], value);
+        }
+
+        kfree(sads);
+}
+
 /*
  * update the info frames with the data from the current display mode
  */
@@ -366,8 +428,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
                        HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
         }
 
-        if (ASIC_IS_DCE32(rdev))
+        if (ASIC_IS_DCE32(rdev)) {
                 dce3_2_afmt_write_speaker_allocation(encoder);
+                dce3_2_afmt_write_sad_regs(encoder);
+        }
 
         WREG32(HDMI0_ACR_PACKET_CONTROL + offset,
                HDMI0_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 44ec7a148c3d..454f90a849e4 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -967,6 +967,35 @@
 #define         HDMI_CONNECTION                         (1 << 16)
 #define         DP_CONNECTION                           (1 << 17)
 
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0        0x71c8 /* LPCM */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1        0x71cc /* AC3 */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2        0x71d0 /* MPEG1 */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3        0x71d4 /* MP3 */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4        0x71d8 /* MPEG2 */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5        0x71dc /* AAC */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6        0x71e0 /* DTS */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7        0x71e4 /* ATRAC */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8        0x71e8 /* one bit audio - leave at 0 (default) */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9        0x71ec /* Dolby Digital */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10       0x71f0 /* DTS-HD */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11       0x71f4 /* MAT-MLP */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12       0x71f8 /* DTS */
+#define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13       0x71fc /* WMA Pro */
+#       define MAX_CHANNELS(x)                            (((x) & 0x7) << 0)
+/* max channels minus one.  7 = 8 channels */
+#       define SUPPORTED_FREQUENCIES(x)                   (((x) & 0xff) << 8)
+#       define DESCRIPTOR_BYTE_2(x)                       (((x) & 0xff) << 16)
+#       define SUPPORTED_FREQUENCIES_STEREO(x)            (((x) & 0xff) << 24) /* LPCM only */
+/* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
+ * bit0 = 32 kHz
+ * bit1 = 44.1 kHz
+ * bit2 = 48 kHz
+ * bit3 = 88.2 kHz
+ * bit4 = 96 kHz
+ * bit5 = 176.4 kHz
+ * bit6 = 192 kHz
+ */
+
 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one
  * instance of the blocks while r6xx has 2.  DCE 3.0 cards are slightly
  * different due to the new DIG blocks, but also have 2 instances.