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authorAlex Deucher <alexander.deucher@amd.com>2012-07-26 09:50:57 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-09-20 13:10:34 -0400
commitaf7912e57316caa1b705f06b03592cec0737cb36 (patch)
tree182dd1ef49d138aa7461f9d4a3ace1ef60936553 /drivers/gpu/drm
parentefd4e418f2bb8a8b21f96fd44e775eaf6dd55905 (diff)
drm/radeon: track whether the GPU controls the backlight (v2)
A table in the vbios tells us whether the GPU backlight controller is used or not. If the bit is set, the GPU backlight controller is used; if it is not set, an off-chip backlight controller is used. v2: store all the firmware flags, not just BL control Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h2
2 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index d67d4f3eb6f4..e368b3027cba 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1254,6 +1254,10 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1254 if (rdev->clock.max_pixel_clock == 0) 1254 if (rdev->clock.max_pixel_clock == 0)
1255 rdev->clock.max_pixel_clock = 40000; 1255 rdev->clock.max_pixel_clock = 40000;
1256 1256
1257 /* not technically a clock, but... */
1258 rdev->mode_info.firmware_flags =
1259 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1260
1257 return true; 1261 return true;
1258 } 1262 }
1259 1263
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index d56978949f34..806140d32b5d 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -252,6 +252,8 @@ struct radeon_mode_info {
252 252
253 /* pointer to fbdev info structure */ 253 /* pointer to fbdev info structure */
254 struct radeon_fbdev *rfbdev; 254 struct radeon_fbdev *rfbdev;
255 /* firmware flags */
256 u16 firmware_flags;
255}; 257};
256 258
257#define MAX_H_CODE_TIMING_LEN 32 259#define MAX_H_CODE_TIMING_LEN 32