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authorPaul Bolle <pebolle@tiscali.nl>2011-03-16 17:10:06 -0400
committerDave Airlie <airlied@redhat.com>2011-03-16 23:50:43 -0400
commita3a88a668ffe8f9771a525a2b00570f8a4c29286 (patch)
tree05022f51b985846654634927ce21323faa6bd448 /drivers/gpu/drm
parent3409fc1b22e2717237f9f23112645f5d190cff4d (diff)
drm: radeon: *_cs_packet_parse_vline() cleanup
Simplify the way the return value is set a number of times (mostly on error). Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c24
-rw-r--r--drivers/gpu/drm/radeon/r100.c16
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c25
3 files changed, 23 insertions, 42 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 5e4f9f876d4f..edde90b37554 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -293,33 +293,28 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
293 if (wait_reg_mem.type != PACKET_TYPE3 || 293 if (wait_reg_mem.type != PACKET_TYPE3 ||
294 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 294 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
295 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 295 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
296 r = -EINVAL; 296 return -EINVAL;
297 return r;
298 } 297 }
299 298
300 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 299 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
301 /* bit 4 is reg (0) or mem (1) */ 300 /* bit 4 is reg (0) or mem (1) */
302 if (wait_reg_mem_info & 0x10) { 301 if (wait_reg_mem_info & 0x10) {
303 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 302 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
304 r = -EINVAL; 303 return -EINVAL;
305 return r;
306 } 304 }
307 /* waiting for value to be equal */ 305 /* waiting for value to be equal */
308 if ((wait_reg_mem_info & 0x7) != 0x3) { 306 if ((wait_reg_mem_info & 0x7) != 0x3) {
309 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 307 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
310 r = -EINVAL; 308 return -EINVAL;
311 return r;
312 } 309 }
313 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) { 310 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
314 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 311 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
315 r = -EINVAL; 312 return -EINVAL;
316 return r;
317 } 313 }
318 314
319 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) { 315 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
320 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 316 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
321 r = -EINVAL; 317 return -EINVAL;
322 return r;
323 } 318 }
324 319
325 /* jump over the NOP */ 320 /* jump over the NOP */
@@ -337,8 +332,7 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
337 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 332 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
338 if (!obj) { 333 if (!obj) {
339 DRM_ERROR("cannot find crtc %d\n", crtc_id); 334 DRM_ERROR("cannot find crtc %d\n", crtc_id);
340 r = -EINVAL; 335 return -EINVAL;
341 goto out;
342 } 336 }
343 crtc = obj_to_crtc(obj); 337 crtc = obj_to_crtc(obj);
344 radeon_crtc = to_radeon_crtc(crtc); 338 radeon_crtc = to_radeon_crtc(crtc);
@@ -363,12 +357,10 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
363 break; 357 break;
364 default: 358 default:
365 DRM_ERROR("unknown crtc reloc\n"); 359 DRM_ERROR("unknown crtc reloc\n");
366 r = -EINVAL; 360 return -EINVAL;
367 goto out;
368 } 361 }
369 } 362 }
370out: 363 return 0;
371 return r;
372} 364}
373 365
374static int evergreen_packet0_check(struct radeon_cs_parser *p, 366static int evergreen_packet0_check(struct radeon_cs_parser *p,
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e372f9e1e5ce..fcc23e4e0b3c 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1205,14 +1205,12 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1205 if (waitreloc.reg != RADEON_WAIT_UNTIL || 1205 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1206 waitreloc.count != 0) { 1206 waitreloc.count != 0) {
1207 DRM_ERROR("vline wait had illegal wait until segment\n"); 1207 DRM_ERROR("vline wait had illegal wait until segment\n");
1208 r = -EINVAL; 1208 return -EINVAL;
1209 return r;
1210 } 1209 }
1211 1210
1212 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) { 1211 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1213 DRM_ERROR("vline wait had illegal wait until\n"); 1212 DRM_ERROR("vline wait had illegal wait until\n");
1214 r = -EINVAL; 1213 return -EINVAL;
1215 return r;
1216 } 1214 }
1217 1215
1218 /* jump over the NOP */ 1216 /* jump over the NOP */
@@ -1230,8 +1228,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1230 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1228 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1231 if (!obj) { 1229 if (!obj) {
1232 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1230 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1233 r = -EINVAL; 1231 return -EINVAL;
1234 goto out;
1235 } 1232 }
1236 crtc = obj_to_crtc(obj); 1233 crtc = obj_to_crtc(obj);
1237 radeon_crtc = to_radeon_crtc(crtc); 1234 radeon_crtc = to_radeon_crtc(crtc);
@@ -1253,14 +1250,13 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1253 break; 1250 break;
1254 default: 1251 default:
1255 DRM_ERROR("unknown crtc reloc\n"); 1252 DRM_ERROR("unknown crtc reloc\n");
1256 r = -EINVAL; 1253 return -EINVAL;
1257 goto out;
1258 } 1254 }
1259 ib[h_idx] = header; 1255 ib[h_idx] = header;
1260 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1; 1256 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1261 } 1257 }
1262out: 1258
1263 return r; 1259 return 0;
1264} 1260}
1265 1261
1266/** 1262/**
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0a0848f0346d..3324620b2db6 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -780,33 +780,28 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
780 if (wait_reg_mem.type != PACKET_TYPE3 || 780 if (wait_reg_mem.type != PACKET_TYPE3 ||
781 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 781 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
782 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 782 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
783 r = -EINVAL; 783 return -EINVAL;
784 return r;
785 } 784 }
786 785
787 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 786 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
788 /* bit 4 is reg (0) or mem (1) */ 787 /* bit 4 is reg (0) or mem (1) */
789 if (wait_reg_mem_info & 0x10) { 788 if (wait_reg_mem_info & 0x10) {
790 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 789 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
791 r = -EINVAL; 790 return -EINVAL;
792 return r;
793 } 791 }
794 /* waiting for value to be equal */ 792 /* waiting for value to be equal */
795 if ((wait_reg_mem_info & 0x7) != 0x3) { 793 if ((wait_reg_mem_info & 0x7) != 0x3) {
796 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 794 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
797 r = -EINVAL; 795 return -EINVAL;
798 return r;
799 } 796 }
800 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { 797 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
801 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 798 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
802 r = -EINVAL; 799 return -EINVAL;
803 return r;
804 } 800 }
805 801
806 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { 802 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
807 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 803 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
808 r = -EINVAL; 804 return -EINVAL;
809 return r;
810 } 805 }
811 806
812 /* jump over the NOP */ 807 /* jump over the NOP */
@@ -825,8 +820,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
825 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 820 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
826 if (!obj) { 821 if (!obj) {
827 DRM_ERROR("cannot find crtc %d\n", crtc_id); 822 DRM_ERROR("cannot find crtc %d\n", crtc_id);
828 r = -EINVAL; 823 return -EINVAL;
829 goto out;
830 } 824 }
831 crtc = obj_to_crtc(obj); 825 crtc = obj_to_crtc(obj);
832 radeon_crtc = to_radeon_crtc(crtc); 826 radeon_crtc = to_radeon_crtc(crtc);
@@ -849,14 +843,13 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
849 break; 843 break;
850 default: 844 default:
851 DRM_ERROR("unknown crtc reloc\n"); 845 DRM_ERROR("unknown crtc reloc\n");
852 r = -EINVAL; 846 return -EINVAL;
853 goto out;
854 } 847 }
855 ib[h_idx] = header; 848 ib[h_idx] = header;
856 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; 849 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
857 } 850 }
858out: 851
859 return r; 852 return 0;
860} 853}
861 854
862static int r600_packet0_check(struct radeon_cs_parser *p, 855static int r600_packet0_check(struct radeon_cs_parser *p,