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authorBen Gamari <bgamari.foss@gmail.com>2009-07-01 22:26:53 -0400
committerEric Anholt <eric@anholt.net>2009-09-04 16:05:09 -0400
commit9e3a6d155ed0a7636b926a798dd7221ea107b274 (patch)
tree9bc79e992d908aa3cf2ba4cf35f34df7b3bd956e /drivers/gpu/drm
parent27c202ad7f141d4efa9c64e30bf4a4d3bcd799ae (diff)
drm/i915: Add i915 register dumping debugfs file
Add a debugfs file to dump the entire register range. Here we assume that reading write-only/reserved registers won't make the chip angry. Seems to hold true, thankfully. Signed-off-by: Ben Gamari <bgamari.foss@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c30
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b4f2d6bce15b..49e0d870f493 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -363,7 +363,37 @@ out:
363 return 0; 363 return 0;
364} 364}
365 365
366static int i915_registers_info(struct seq_file *m, void *data) {
367 struct drm_info_node *node = (struct drm_info_node *) m->private;
368 struct drm_device *dev = node->minor->dev;
369 drm_i915_private_t *dev_priv = dev->dev_private;
370 uint32_t reg;
371
372#define DUMP_RANGE(start, end) \
373 for (reg=start; reg < end; reg += 4) \
374 seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
375
376 DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
377 DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
378 DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
379 DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
380 DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
381 DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
382 DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
383 DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
384 DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
385 DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
386 DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
387 DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
388 DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
389 DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
390
391 return 0;
392}
393
394
366static struct drm_info_list i915_debugfs_list[] = { 395static struct drm_info_list i915_debugfs_list[] = {
396 {"i915_regs", i915_registers_info, 0},
367 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, 397 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
368 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, 398 {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
369 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, 399 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},