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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-22 14:10:44 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-23 05:30:57 -0400
commit9b74f7348f214b1f99819f0d0da4a1cbabb1e740 (patch)
treeb6d92f2703d72ceca48b1309274198c174b53c3a /drivers/gpu/drm
parentdb8c076b9206ea35b1f7299708d5510b17674db2 (diff)
drm/i915: Fix 945GM regression in e259befd
A minor typo caused a single fence register to be incorrectly programmed, resulting in occassional tiling corruption. Reported-and-tested-by: Hans de Bruin <bruinjm@xs4all.nl> Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=18962 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index cf4ffbee1c00..bced9b25c71e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2400,7 +2400,7 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2400 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); 2400 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2401 break; 2401 break;
2402 case 3: 2402 case 3:
2403 if (obj_priv->fence_reg > 8) 2403 if (obj_priv->fence_reg >= 8)
2404 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; 2404 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2405 else 2405 else
2406 case 2: 2406 case 2: