diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-04 17:22:17 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-11 15:43:56 -0500 |
commit | 9862e600cef87de0e301bad7d1435b87e03ea84d (patch) | |
tree | 6f0cde94b74885dc8e85a22f1acf9f1474abb135 /drivers/gpu/drm | |
parent | 0f46832fab779a9a3314ce5e833155fe4cf18f6c (diff) |
drm/i915/debugfs: Show the per-ring IMR
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/i915_debugfs.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 5 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 25 |
3 files changed, 24 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 92f75782c332..7243d6418651 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c | |||
@@ -456,8 +456,14 @@ static int i915_interrupt_info(struct seq_file *m, void *data) | |||
456 | } | 456 | } |
457 | seq_printf(m, "Interrupts received: %d\n", | 457 | seq_printf(m, "Interrupts received: %d\n", |
458 | atomic_read(&dev_priv->irq_received)); | 458 | atomic_read(&dev_priv->irq_received)); |
459 | for (i = 0; i < I915_NUM_RINGS; i++) | 459 | for (i = 0; i < I915_NUM_RINGS; i++) { |
460 | if (IS_GEN6(dev)) { | ||
461 | seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", | ||
462 | dev_priv->ring[i].name, | ||
463 | I915_READ_IMR(&dev_priv->ring[i])); | ||
464 | } | ||
460 | i915_ring_seqno_info(m, &dev_priv->ring[i]); | 465 | i915_ring_seqno_info(m, &dev_priv->ring[i]); |
466 | } | ||
461 | mutex_unlock(&dev->struct_mutex); | 467 | mutex_unlock(&dev->struct_mutex); |
462 | 468 | ||
463 | return 0; | 469 | return 0; |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 826873a23db0..c9adcdd6ad6a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -349,9 +349,12 @@ static void notify_ring(struct drm_device *dev, | |||
349 | { | 349 | { |
350 | struct drm_i915_private *dev_priv = dev->dev_private; | 350 | struct drm_i915_private *dev_priv = dev->dev_private; |
351 | u32 seqno = ring->get_seqno(ring); | 351 | u32 seqno = ring->get_seqno(ring); |
352 | ring->irq_seqno = seqno; | 352 | |
353 | trace_i915_gem_request_complete(dev, seqno); | 353 | trace_i915_gem_request_complete(dev, seqno); |
354 | |||
355 | ring->irq_seqno = seqno; | ||
354 | wake_up_all(&ring->irq_queue); | 356 | wake_up_all(&ring->irq_queue); |
357 | |||
355 | dev_priv->hangcheck_count = 0; | 358 | dev_priv->hangcheck_count = 0; |
356 | mod_timer(&dev_priv->hangcheck_timer, | 359 | mod_timer(&dev_priv->hangcheck_timer, |
357 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | 360 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 634f6f84cb57..9b134b8643cb 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -16,23 +16,24 @@ struct intel_hw_status_page { | |||
16 | 16 | ||
17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) | 17 | #define I915_RING_READ(reg) i915_safe_read(dev_priv, reg) |
18 | 18 | ||
19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL(ring->mmio_base)) | 19 | #define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base)) |
20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val) | 20 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) |
21 | 21 | ||
22 | #define I915_READ_START(ring) I915_RING_READ(RING_START(ring->mmio_base)) | 22 | #define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base)) |
23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) | 23 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) |
24 | 24 | ||
25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD(ring->mmio_base)) | 25 | #define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base)) |
26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) | 26 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) |
27 | 27 | ||
28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL(ring->mmio_base)) | 28 | #define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base)) |
29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) | 29 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) |
30 | 30 | ||
31 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR(ring->mmio_base), val) | 31 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
32 | #define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base)) | ||
32 | 33 | ||
33 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID(ring->mmio_base)) | 34 | #define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base)) |
34 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0(ring->mmio_base)) | 35 | #define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base)) |
35 | #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1(ring->mmio_base)) | 36 | #define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base)) |
36 | 37 | ||
37 | struct intel_ring_buffer { | 38 | struct intel_ring_buffer { |
38 | const char *name; | 39 | const char *name; |