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authorAlex Deucher <alexander.deucher@amd.com>2012-08-31 11:56:50 -0400
committerAlex Deucher <alexander.deucher@amd.com>2012-09-13 16:17:49 -0400
commit985f61f7ee647ad570c05eab0b74915da2ac8e19 (patch)
tree3edf54a41d8554452914d57b4f5ae193de40bf85 /drivers/gpu/drm
parentb65523283c6853184f100c2c25642b02001e6364 (diff)
drm/radeon: rework pll selection (v3)
For DP we can use the same PPLL for all active DP encoders. Take advantage of that to prevent cases where we may end up sharing a PPLL between DP and non-DP which won't work. Also clean up the code a bit. v2: - fix missing pll_id assignment in crtc init v3: - fix DP PPLL check - document functions - break in main encoder search loop after matching. no need to keep checking additional encoders. fixes: https://bugs.freedesktop.org/show_bug.cgi?id=54471 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c163
1 files changed, 129 insertions, 34 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 2817101fb167..e721e3087b99 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1479,14 +1479,98 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1479 } 1479 }
1480} 1480}
1481 1481
1482/**
1483 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1484 *
1485 * @crtc: drm crtc
1486 *
1487 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1488 */
1489static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1490{
1491 struct drm_device *dev = crtc->dev;
1492 struct drm_crtc *test_crtc;
1493 struct radeon_crtc *radeon_test_crtc;
1494 u32 pll_in_use = 0;
1495
1496 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1497 if (crtc == test_crtc)
1498 continue;
1499
1500 radeon_test_crtc = to_radeon_crtc(test_crtc);
1501 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1502 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1503 }
1504 return pll_in_use;
1505}
1506
1507/**
1508 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1509 *
1510 * @crtc: drm crtc
1511 *
1512 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1513 * also in DP mode. For DP, a single PPLL can be used for all DP
1514 * crtcs/encoders.
1515 */
1516static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1517{
1518 struct drm_device *dev = crtc->dev;
1519 struct drm_encoder *test_encoder;
1520 struct radeon_crtc *radeon_test_crtc;
1521
1522 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1523 if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
1524 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1525 /* for DP use the same PLL for all */
1526 radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
1527 if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
1528 return radeon_test_crtc->pll_id;
1529 }
1530 }
1531 }
1532 return ATOM_PPLL_INVALID;
1533}
1534
1535/**
1536 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1537 *
1538 * @crtc: drm crtc
1539 *
1540 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1541 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1542 * monitors a dedicated PPLL must be used. If a particular board has
1543 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1544 * as there is no need to program the PLL itself. If we are not able to
1545 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1546 * avoid messing up an existing monitor.
1547 *
1548 * Asic specific PLL information
1549 *
1550 * DCE 6.1
1551 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1552 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1553 *
1554 * DCE 6.0
1555 * - PPLL0 is available to all UNIPHY (DP only)
1556 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1557 *
1558 * DCE 5.0
1559 * - DCPLL is available to all UNIPHY (DP only)
1560 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1561 *
1562 * DCE 3.0/4.0/4.1
1563 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1564 *
1565 */
1482static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1566static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1483{ 1567{
1484 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1568 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1485 struct drm_device *dev = crtc->dev; 1569 struct drm_device *dev = crtc->dev;
1486 struct radeon_device *rdev = dev->dev_private; 1570 struct radeon_device *rdev = dev->dev_private;
1487 struct drm_encoder *test_encoder; 1571 struct drm_encoder *test_encoder;
1488 struct drm_crtc *test_crtc; 1572 u32 pll_in_use;
1489 uint32_t pll_in_use = 0; 1573 int pll;
1490 1574
1491 if (ASIC_IS_DCE61(rdev)) { 1575 if (ASIC_IS_DCE61(rdev)) {
1492 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1576 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
@@ -1498,32 +1582,40 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1498 1582
1499 if ((test_radeon_encoder->encoder_id == 1583 if ((test_radeon_encoder->encoder_id ==
1500 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1584 ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1501 (dig->linkb == false)) /* UNIPHY A uses PPLL2 */ 1585 (dig->linkb == false))
1586 /* UNIPHY A uses PPLL2 */
1502 return ATOM_PPLL2; 1587 return ATOM_PPLL2;
1588 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1589 /* UNIPHY B/C/D/E/F */
1590 if (rdev->clock.dp_extclk)
1591 /* skip PPLL programming if using ext clock */
1592 return ATOM_PPLL_INVALID;
1593 else {
1594 /* use the same PPLL for all DP monitors */
1595 pll = radeon_get_shared_dp_ppll(crtc);
1596 if (pll != ATOM_PPLL_INVALID)
1597 return pll;
1598 }
1599 }
1600 break;
1503 } 1601 }
1504 } 1602 }
1505 /* UNIPHY B/C/D/E/F */ 1603 /* UNIPHY B/C/D/E/F */
1506 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1604 pll_in_use = radeon_get_pll_use_mask(crtc);
1507 struct radeon_crtc *radeon_test_crtc; 1605 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1508
1509 if (crtc == test_crtc)
1510 continue;
1511
1512 radeon_test_crtc = to_radeon_crtc(test_crtc);
1513 if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1514 (radeon_test_crtc->pll_id == ATOM_PPLL1))
1515 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1516 }
1517 if (!(pll_in_use & 4))
1518 return ATOM_PPLL0; 1606 return ATOM_PPLL0;
1519 return ATOM_PPLL1; 1607 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1608 return ATOM_PPLL1;
1609 DRM_ERROR("unable to allocate a PPLL\n");
1610 return ATOM_PPLL_INVALID;
1520 } else if (ASIC_IS_DCE4(rdev)) { 1611 } else if (ASIC_IS_DCE4(rdev)) {
1521 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { 1612 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1522 if (test_encoder->crtc && (test_encoder->crtc == crtc)) { 1613 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1523 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1614 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1524 * depending on the asic: 1615 * depending on the asic:
1525 * DCE4: PPLL or ext clock 1616 * DCE4: PPLL or ext clock
1526 * DCE5: DCPLL or ext clock 1617 * DCE5: PPLL, DCPLL, or ext clock
1618 * DCE6: PPLL, PPLL0, or ext clock
1527 * 1619 *
1528 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1620 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1529 * PPLL/DCPLL programming and only program the DP DTO for the 1621 * PPLL/DCPLL programming and only program the DP DTO for the
@@ -1531,31 +1623,34 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1531 */ 1623 */
1532 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { 1624 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1533 if (rdev->clock.dp_extclk) 1625 if (rdev->clock.dp_extclk)
1626 /* skip PPLL programming if using ext clock */
1534 return ATOM_PPLL_INVALID; 1627 return ATOM_PPLL_INVALID;
1535 else if (ASIC_IS_DCE6(rdev)) 1628 else if (ASIC_IS_DCE6(rdev))
1629 /* use PPLL0 for all DP */
1536 return ATOM_PPLL0; 1630 return ATOM_PPLL0;
1537 else if (ASIC_IS_DCE5(rdev)) 1631 else if (ASIC_IS_DCE5(rdev))
1632 /* use DCPLL for all DP */
1538 return ATOM_DCPLL; 1633 return ATOM_DCPLL;
1634 else {
1635 /* use the same PPLL for all DP monitors */
1636 pll = radeon_get_shared_dp_ppll(crtc);
1637 if (pll != ATOM_PPLL_INVALID)
1638 return pll;
1639 }
1539 } 1640 }
1641 break;
1540 } 1642 }
1541 } 1643 }
1542 1644 /* all other cases */
1543 /* otherwise, pick one of the plls */ 1645 pll_in_use = radeon_get_pll_use_mask(crtc);
1544 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1646 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1545 struct radeon_crtc *radeon_test_crtc; 1647 return ATOM_PPLL2;
1546 1648 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1547 if (crtc == test_crtc)
1548 continue;
1549
1550 radeon_test_crtc = to_radeon_crtc(test_crtc);
1551 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1552 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1553 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1554 }
1555 if (!(pll_in_use & 1))
1556 return ATOM_PPLL1; 1649 return ATOM_PPLL1;
1557 return ATOM_PPLL2; 1650 DRM_ERROR("unable to allocate a PPLL\n");
1651 return ATOM_PPLL_INVALID;
1558 } else 1652 } else
1653 /* use PPLL1 or PPLL2 */
1559 return radeon_crtc->crtc_id; 1654 return radeon_crtc->crtc_id;
1560 1655
1561} 1656}
@@ -1697,7 +1792,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1697 break; 1792 break;
1698 } 1793 }
1699done: 1794done:
1700 radeon_crtc->pll_id = -1; 1795 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1701} 1796}
1702 1797
1703static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 1798static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
@@ -1746,6 +1841,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
1746 else 1841 else
1747 radeon_crtc->crtc_offset = 0; 1842 radeon_crtc->crtc_offset = 0;
1748 } 1843 }
1749 radeon_crtc->pll_id = -1; 1844 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1750 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 1845 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1751} 1846}