diff options
author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-13 18:56:38 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-14 05:34:27 -0400 |
commit | 7213342db58adb7b8e399a00fc423951d7f75369 (patch) | |
tree | a302b3708792f34fed855fe6ce3301de7bea8c64 /drivers/gpu/drm | |
parent | b3b079dbef06c7f775178d561a4c8e47b7447139 (diff) |
drm/i915: Consolidate flushing the display plane
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem.c | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_fb.c | 8 |
4 files changed, 17 insertions, 50 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 70cbe3cee1ab..24b7796c33af 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1024,7 +1024,6 @@ void i915_gem_free_all_phys_object(struct drm_device *dev); | |||
1024 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); | 1024 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
1025 | void i915_gem_object_put_pages(struct drm_gem_object *obj); | 1025 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1026 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); | 1026 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
1027 | int i915_gem_object_flush_write_domain(struct drm_gem_object *obj); | ||
1028 | 1027 | ||
1029 | void i915_gem_shrinker_init(void); | 1028 | void i915_gem_shrinker_init(void); |
1030 | void i915_gem_shrinker_exit(void); | 1029 | void i915_gem_shrinker_exit(void); |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 9391765af70d..328f8c9ee966 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
@@ -2645,26 +2645,6 @@ i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |||
2645 | old_write_domain); | 2645 | old_write_domain); |
2646 | } | 2646 | } |
2647 | 2647 | ||
2648 | int | ||
2649 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) | ||
2650 | { | ||
2651 | int ret = 0; | ||
2652 | |||
2653 | switch (obj->write_domain) { | ||
2654 | case I915_GEM_DOMAIN_GTT: | ||
2655 | i915_gem_object_flush_gtt_write_domain(obj); | ||
2656 | break; | ||
2657 | case I915_GEM_DOMAIN_CPU: | ||
2658 | i915_gem_object_flush_cpu_write_domain(obj); | ||
2659 | break; | ||
2660 | default: | ||
2661 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); | ||
2662 | break; | ||
2663 | } | ||
2664 | |||
2665 | return ret; | ||
2666 | } | ||
2667 | |||
2668 | /** | 2648 | /** |
2669 | * Moves a single object to the GTT read, and possibly write domain. | 2649 | * Moves a single object to the GTT read, and possibly write domain. |
2670 | * | 2650 | * |
@@ -2686,21 +2666,16 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) | |||
2686 | if (ret != 0) | 2666 | if (ret != 0) |
2687 | return ret; | 2667 | return ret; |
2688 | 2668 | ||
2689 | old_write_domain = obj->write_domain; | 2669 | i915_gem_object_flush_cpu_write_domain(obj); |
2690 | old_read_domains = obj->read_domains; | ||
2691 | 2670 | ||
2692 | /* If we're writing through the GTT domain, then CPU and GPU caches | ||
2693 | * will need to be invalidated at next use. | ||
2694 | */ | ||
2695 | if (write) { | 2671 | if (write) { |
2696 | ret = i915_gem_object_wait_rendering(obj); | 2672 | ret = i915_gem_object_wait_rendering(obj); |
2697 | if (ret) | 2673 | if (ret) |
2698 | return ret; | 2674 | return ret; |
2699 | |||
2700 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | ||
2701 | } | 2675 | } |
2702 | 2676 | ||
2703 | i915_gem_object_flush_cpu_write_domain(obj); | 2677 | old_write_domain = obj->write_domain; |
2678 | old_read_domains = obj->read_domains; | ||
2704 | 2679 | ||
2705 | /* It should now be out of any other write domains, and we can update | 2680 | /* It should now be out of any other write domains, and we can update |
2706 | * the domain values for our changes. | 2681 | * the domain values for our changes. |
@@ -2708,6 +2683,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) | |||
2708 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | 2683 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2709 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | 2684 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
2710 | if (write) { | 2685 | if (write) { |
2686 | obj->read_domains = I915_GEM_DOMAIN_GTT; | ||
2711 | obj->write_domain = I915_GEM_DOMAIN_GTT; | 2687 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2712 | obj_priv->dirty = 1; | 2688 | obj_priv->dirty = 1; |
2713 | } | 2689 | } |
@@ -2773,6 +2749,12 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |||
2773 | */ | 2749 | */ |
2774 | i915_gem_object_set_to_full_cpu_read_domain(obj); | 2750 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2775 | 2751 | ||
2752 | if (write) { | ||
2753 | ret = i915_gem_object_wait_rendering(obj); | ||
2754 | if (ret) | ||
2755 | return ret; | ||
2756 | } | ||
2757 | |||
2776 | old_write_domain = obj->write_domain; | 2758 | old_write_domain = obj->write_domain; |
2777 | old_read_domains = obj->read_domains; | 2759 | old_read_domains = obj->read_domains; |
2778 | 2760 | ||
@@ -2792,10 +2774,6 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |||
2792 | * need to be invalidated at next use. | 2774 | * need to be invalidated at next use. |
2793 | */ | 2775 | */ |
2794 | if (write) { | 2776 | if (write) { |
2795 | ret = i915_gem_object_wait_rendering(obj); | ||
2796 | if (ret) | ||
2797 | return ret; | ||
2798 | |||
2799 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | 2777 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
2800 | obj->write_domain = I915_GEM_DOMAIN_CPU; | 2778 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2801 | } | 2779 | } |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 16ae34559caa..810ed2dca4c7 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1448,6 +1448,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj) | |||
1448 | if (ret != 0) | 1448 | if (ret != 0) |
1449 | return ret; | 1449 | return ret; |
1450 | 1450 | ||
1451 | ret = i915_gem_object_set_to_display_plane(obj); | ||
1452 | if (ret != 0) { | ||
1453 | i915_gem_object_unpin(obj); | ||
1454 | return ret; | ||
1455 | } | ||
1456 | |||
1451 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | 1457 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
1452 | * fence, whereas 965+ only requires a fence if using | 1458 | * fence, whereas 965+ only requires a fence if using |
1453 | * framebuffer compression. For simplicity, we always install | 1459 | * framebuffer compression. For simplicity, we always install |
@@ -1589,13 +1595,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, | |||
1589 | return ret; | 1595 | return ret; |
1590 | } | 1596 | } |
1591 | 1597 | ||
1592 | ret = i915_gem_object_set_to_display_plane(obj); | ||
1593 | if (ret != 0) { | ||
1594 | i915_gem_object_unpin(obj); | ||
1595 | mutex_unlock(&dev->struct_mutex); | ||
1596 | return ret; | ||
1597 | } | ||
1598 | |||
1599 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y); | 1598 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y); |
1600 | if (ret) { | 1599 | if (ret) { |
1601 | i915_gem_object_unpin(obj); | 1600 | i915_gem_object_unpin(obj); |
@@ -5043,9 +5042,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc, | |||
5043 | drm_gem_object_reference(obj); | 5042 | drm_gem_object_reference(obj); |
5044 | 5043 | ||
5045 | crtc->fb = fb; | 5044 | crtc->fb = fb; |
5046 | ret = i915_gem_object_flush_write_domain(obj); | ||
5047 | if (ret) | ||
5048 | goto cleanup_objs; | ||
5049 | 5045 | ||
5050 | ret = drm_vblank_get(dev, intel_crtc->pipe); | 5046 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
5051 | if (ret) | 5047 | if (ret) |
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c index 0ee4a8c16608..e2d13e394a0d 100644 --- a/drivers/gpu/drm/i915/intel_fb.c +++ b/drivers/gpu/drm/i915/intel_fb.c | |||
@@ -93,19 +93,13 @@ static int intelfb_create(struct intel_fbdev *ifbdev, | |||
93 | 93 | ||
94 | mutex_lock(&dev->struct_mutex); | 94 | mutex_lock(&dev->struct_mutex); |
95 | 95 | ||
96 | /* Flush everything out, we'll be doing GTT only from now on */ | ||
96 | ret = intel_pin_and_fence_fb_obj(dev, fbo); | 97 | ret = intel_pin_and_fence_fb_obj(dev, fbo); |
97 | if (ret) { | 98 | if (ret) { |
98 | DRM_ERROR("failed to pin fb: %d\n", ret); | 99 | DRM_ERROR("failed to pin fb: %d\n", ret); |
99 | goto out_unref; | 100 | goto out_unref; |
100 | } | 101 | } |
101 | 102 | ||
102 | /* Flush everything out, we'll be doing GTT only from now on */ | ||
103 | ret = i915_gem_object_set_to_gtt_domain(fbo, 1); | ||
104 | if (ret) { | ||
105 | DRM_ERROR("failed to bind fb: %d.\n", ret); | ||
106 | goto out_unpin; | ||
107 | } | ||
108 | |||
109 | info = framebuffer_alloc(0, device); | 103 | info = framebuffer_alloc(0, device); |
110 | if (!info) { | 104 | if (!info) { |
111 | ret = -ENOMEM; | 105 | ret = -ENOMEM; |