drm/radeon: fix surface setup on r1xx

r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.

Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 4 insertions, 7 deletions

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index d0314ecbd7c1..c9affefd79f6 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3077,6 +3077,10 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
                 if (tiling_flags & RADEON_TILING_MACRO)
                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
+                /* setting pitch to 0 disables tiling */
+                if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
+                                == 0)
+                        pitch = 0;
         } else if (rdev->family <= CHIP_RV280) {
                 if (tiling_flags & (RADEON_TILING_MACRO))
                         flags |= R200_SURF_TILE_COLOR_MACRO;
@@ -3094,13 +3098,6 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
 
-        /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
-        if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
-                if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
-                        if (ASIC_IS_RN50(rdev))
-                                pitch /= 16;
-        }
-
         /* r100/r200 divide by 16 */
         if (rdev->family < CHIP_R300)
                 flags |= pitch / 16;