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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-09-03 07:09:53 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-09-03 09:15:10 -0400
commit55522f37817728eff26a75a64c60f07580efa66b (patch)
treeb028dd2ae26b0d851997e62be0cbe5213f0d00b5 /drivers/gpu/drm
parenta3ed6aada3f2aaec6432f5c3380be6e2918af993 (diff)
drm/i915: Check of !HAS_PCH_SPLIT() in PCH transcoder funcs
Check for !HAS_PCH_SPLIT() instead of 'gen < 5' in the PCH transcoder enable functions. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 02b099a93f8e..e245505c867f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1858,7 +1858,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858 uint32_t reg, val, pipeconf_val; 1858 uint32_t reg, val, pipeconf_val;
1859 1859
1860 /* PCH only available on ILK+ */ 1860 /* PCH only available on ILK+ */
1861 BUG_ON(INTEL_INFO(dev)->gen < 5); 1861 BUG_ON(!HAS_PCH_SPLIT(dev));
1862 1862
1863 /* Make sure PCH DPLL is enabled */ 1863 /* Make sure PCH DPLL is enabled */
1864 assert_shared_dpll_enabled(dev_priv, 1864 assert_shared_dpll_enabled(dev_priv,
@@ -1911,7 +1911,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1911 u32 val, pipeconf_val; 1911 u32 val, pipeconf_val;
1912 1912
1913 /* PCH only available on ILK+ */ 1913 /* PCH only available on ILK+ */
1914 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5); 1914 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1915 1915
1916 /* FDI must be feeding us bits for PCH ports */ 1916 /* FDI must be feeding us bits for PCH ports */
1917 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 1917 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);