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authorDave Airlie <airlied@redhat.com>2014-03-03 16:51:41 -0500
committerDave Airlie <airlied@redhat.com>2014-03-03 16:51:41 -0500
commit4d33f3aa1cc7869c5ea4d57f3715b37bdcf515db (patch)
treec729ca22b60ba7fb7d3ce13c1f1d37f312a588f9 /drivers/gpu/drm
parent4d538b79197901fecc42e746d515d07fd1089b62 (diff)
parent4c0e552882114d1edb588242d45035246ab078a0 (diff)
Merge tag 'drm-intel-next-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel into drm-next
- Fix the execbuf rebind performance regression due to topic/ppgtt (Chris). - Fix up the connector cleanup ordering for sdvod i2c and dp aux devices (Imre). - Try to preserve the firmware modeset config on driver load. And a bit of prep work for smooth takeover of the fb contents (Jesse). - Prep cleanup for larger gtt address spaces on bdw (Ben). - Improve our vblank_wait code to make hsw modesets faster (Paulo). - Display debugfs file (Jesse). - DRRS prep work from Vandana Kannan. - pipestat interrupt handler to fix a few races around vblank/pageflip handling on byt (Imre). - Improve display fuse handling for display-less SKUs (Damien). - Drop locks while stalling for the gpu when serving pagefaults to improve interactivity (Chris). - And as usual piles of other improvements and small fixes all over. * tag 'drm-intel-next-2014-02-14' of ssh://git.freedesktop.org/git/drm-intel: (65 commits) drm/i915: fix NULL deref in the load detect code drm/i915: Only bind each object rather than for every execbuffer drm/i915: Directly return the vma from bind_to_vm drm/i915: Simplify i915_gem_object_ggtt_unpin drm/i915: Allow blocking in the PDE alloc when running low on gtt space drm/i915: Don't allocate context pages as mappable drm/i915: Handle set_cache_level errors in the status page setup drm/i915: Don't pin the status page as mappable drm/i915: Don't set PIN_MAPPABLE for legacy ringbuffers drm/i915: Handle set_cache_level errors in the pipe control scratch setup drm/i915: split PIN_GLOBAL out from PIN_MAPPABLE drm/i915: Consolidate binding parameters into flags drm/i915: sdvo: add i2c sysfs symlink to the connector's directory drm/i915: sdvo: fix error path in sdvo_connector_init drm/i915: dp: fix order of dp aux i2c device cleanup drm/i915: add unregister callback to connector drm/i915: don't reference null pointer at i915_sink_crc drm/i915/lvds: Remove dead code from failing case drm/i915: don't preserve inherited configs with nothing on v2 drm/i915/bdw: Split up PPGTT cleanup ...
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/drm_crtc.c23
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c6
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c162
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c81
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h58
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c155
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c9
-rw-r--r--drivers/gpu/drm/i915/i915_gem_evict.c10
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c18
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c61
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c168
-rw-r--r--drivers/gpu/drm/i915/i915_params.c4
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h181
-rw-r--r--drivers/gpu/drm/i915/i915_trace.h20
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c1
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c257
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c25
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h20
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c3
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c1
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c171
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c32
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c13
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c2
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c4
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c51
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c22
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c70
-rw-r--r--drivers/gpu/drm/i915/intel_tv.c9
30 files changed, 1117 insertions, 522 deletions
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 3b7d32da1604..35ea15d5ffff 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -215,6 +215,16 @@ static const struct drm_prop_enum_list drm_encoder_enum_list[] =
215 { DRM_MODE_ENCODER_DSI, "DSI" }, 215 { DRM_MODE_ENCODER_DSI, "DSI" },
216}; 216};
217 217
218static const struct drm_prop_enum_list drm_subpixel_enum_list[] =
219{
220 { SubPixelUnknown, "Unknown" },
221 { SubPixelHorizontalRGB, "Horizontal RGB" },
222 { SubPixelHorizontalBGR, "Horizontal BGR" },
223 { SubPixelVerticalRGB, "Vertical RGB" },
224 { SubPixelVerticalBGR, "Vertical BGR" },
225 { SubPixelNone, "None" },
226};
227
218void drm_connector_ida_init(void) 228void drm_connector_ida_init(void)
219{ 229{
220 int i; 230 int i;
@@ -264,6 +274,19 @@ const char *drm_get_connector_status_name(enum drm_connector_status status)
264} 274}
265EXPORT_SYMBOL(drm_get_connector_status_name); 275EXPORT_SYMBOL(drm_get_connector_status_name);
266 276
277/**
278 * drm_get_subpixel_order_name - return a string for a given subpixel enum
279 * @order: enum of subpixel_order
280 *
281 * Note you could abuse this and return something out of bounds, but that
282 * would be a caller error. No unscrubbed user data should make it here.
283 */
284const char *drm_get_subpixel_order_name(enum subpixel_order order)
285{
286 return drm_subpixel_enum_list[order].name;
287}
288EXPORT_SYMBOL(drm_get_subpixel_order_name);
289
267static char printable_char(int c) 290static char printable_char(int c)
268{ 291{
269 return isascii(c) && isprint(c) ? c : '?'; 292 return isascii(c) && isprint(c) ? c : '?';
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 98a03639b413..d99df15a78bc 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -1136,7 +1136,7 @@ static int drm_fb_helper_probe_connector_modes(struct drm_fb_helper *fb_helper,
1136 return count; 1136 return count;
1137} 1137}
1138 1138
1139static struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_connector *fb_connector, int width, int height) 1139struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_connector *fb_connector, int width, int height)
1140{ 1140{
1141 struct drm_display_mode *mode; 1141 struct drm_display_mode *mode;
1142 1142
@@ -1149,6 +1149,7 @@ static struct drm_display_mode *drm_has_preferred_mode(struct drm_fb_helper_conn
1149 } 1149 }
1150 return NULL; 1150 return NULL;
1151} 1151}
1152EXPORT_SYMBOL(drm_has_preferred_mode);
1152 1153
1153static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector) 1154static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector)
1154{ 1155{
@@ -1157,7 +1158,7 @@ static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector)
1157 return cmdline_mode->specified; 1158 return cmdline_mode->specified;
1158} 1159}
1159 1160
1160static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn, 1161struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
1161 int width, int height) 1162 int width, int height)
1162{ 1163{
1163 struct drm_cmdline_mode *cmdline_mode; 1164 struct drm_cmdline_mode *cmdline_mode;
@@ -1197,6 +1198,7 @@ create_mode:
1197 list_add(&mode->head, &fb_helper_conn->connector->modes); 1198 list_add(&mode->head, &fb_helper_conn->connector->modes);
1198 return mode; 1199 return mode;
1199} 1200}
1201EXPORT_SYMBOL(drm_pick_cmdline_mode);
1200 1202
1201static bool drm_connector_enabled(struct drm_connector *connector, bool strict) 1203static bool drm_connector_enabled(struct drm_connector *connector, bool strict)
1202{ 1204{
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2dc05c30b800..d90a70744d93 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1937,6 +1937,9 @@ static int i915_sink_crc(struct seq_file *m, void *data)
1937 if (connector->base.dpms != DRM_MODE_DPMS_ON) 1937 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1938 continue; 1938 continue;
1939 1939
1940 if (!connector->base.encoder)
1941 continue;
1942
1940 encoder = to_intel_encoder(connector->base.encoder); 1943 encoder = to_intel_encoder(connector->base.encoder);
1941 if (encoder->type != INTEL_OUTPUT_EDP) 1944 if (encoder->type != INTEL_OUTPUT_EDP)
1942 continue; 1945 continue;
@@ -2074,6 +2077,164 @@ static int i915_power_domain_info(struct seq_file *m, void *unused)
2074 return 0; 2077 return 0;
2075} 2078}
2076 2079
2080static void intel_seq_print_mode(struct seq_file *m, int tabs,
2081 struct drm_display_mode *mode)
2082{
2083 int i;
2084
2085 for (i = 0; i < tabs; i++)
2086 seq_putc(m, '\t');
2087
2088 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2089 mode->base.id, mode->name,
2090 mode->vrefresh, mode->clock,
2091 mode->hdisplay, mode->hsync_start,
2092 mode->hsync_end, mode->htotal,
2093 mode->vdisplay, mode->vsync_start,
2094 mode->vsync_end, mode->vtotal,
2095 mode->type, mode->flags);
2096}
2097
2098static void intel_encoder_info(struct seq_file *m,
2099 struct intel_crtc *intel_crtc,
2100 struct intel_encoder *intel_encoder)
2101{
2102 struct drm_info_node *node = (struct drm_info_node *) m->private;
2103 struct drm_device *dev = node->minor->dev;
2104 struct drm_crtc *crtc = &intel_crtc->base;
2105 struct intel_connector *intel_connector;
2106 struct drm_encoder *encoder;
2107
2108 encoder = &intel_encoder->base;
2109 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2110 encoder->base.id, drm_get_encoder_name(encoder));
2111 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2112 struct drm_connector *connector = &intel_connector->base;
2113 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2114 connector->base.id,
2115 drm_get_connector_name(connector),
2116 drm_get_connector_status_name(connector->status));
2117 if (connector->status == connector_status_connected) {
2118 struct drm_display_mode *mode = &crtc->mode;
2119 seq_printf(m, ", mode:\n");
2120 intel_seq_print_mode(m, 2, mode);
2121 } else {
2122 seq_putc(m, '\n');
2123 }
2124 }
2125}
2126
2127static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2128{
2129 struct drm_info_node *node = (struct drm_info_node *) m->private;
2130 struct drm_device *dev = node->minor->dev;
2131 struct drm_crtc *crtc = &intel_crtc->base;
2132 struct intel_encoder *intel_encoder;
2133
2134 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2135 crtc->fb->base.id, crtc->x, crtc->y,
2136 crtc->fb->width, crtc->fb->height);
2137 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2138 intel_encoder_info(m, intel_crtc, intel_encoder);
2139}
2140
2141static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2142{
2143 struct drm_display_mode *mode = panel->fixed_mode;
2144
2145 seq_printf(m, "\tfixed mode:\n");
2146 intel_seq_print_mode(m, 2, mode);
2147}
2148
2149static void intel_dp_info(struct seq_file *m,
2150 struct intel_connector *intel_connector)
2151{
2152 struct intel_encoder *intel_encoder = intel_connector->encoder;
2153 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2154
2155 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2156 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2157 "no");
2158 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2159 intel_panel_info(m, &intel_connector->panel);
2160}
2161
2162static void intel_hdmi_info(struct seq_file *m,
2163 struct intel_connector *intel_connector)
2164{
2165 struct intel_encoder *intel_encoder = intel_connector->encoder;
2166 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2167
2168 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2169 "no");
2170}
2171
2172static void intel_lvds_info(struct seq_file *m,
2173 struct intel_connector *intel_connector)
2174{
2175 intel_panel_info(m, &intel_connector->panel);
2176}
2177
2178static void intel_connector_info(struct seq_file *m,
2179 struct drm_connector *connector)
2180{
2181 struct intel_connector *intel_connector = to_intel_connector(connector);
2182 struct intel_encoder *intel_encoder = intel_connector->encoder;
2183
2184 seq_printf(m, "connector %d: type %s, status: %s\n",
2185 connector->base.id, drm_get_connector_name(connector),
2186 drm_get_connector_status_name(connector->status));
2187 if (connector->status == connector_status_connected) {
2188 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2189 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2190 connector->display_info.width_mm,
2191 connector->display_info.height_mm);
2192 seq_printf(m, "\tsubpixel order: %s\n",
2193 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2194 seq_printf(m, "\tCEA rev: %d\n",
2195 connector->display_info.cea_rev);
2196 }
2197 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2198 intel_encoder->type == INTEL_OUTPUT_EDP)
2199 intel_dp_info(m, intel_connector);
2200 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2201 intel_hdmi_info(m, intel_connector);
2202 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2203 intel_lvds_info(m, intel_connector);
2204
2205}
2206
2207static int i915_display_info(struct seq_file *m, void *unused)
2208{
2209 struct drm_info_node *node = (struct drm_info_node *) m->private;
2210 struct drm_device *dev = node->minor->dev;
2211 struct drm_crtc *crtc;
2212 struct drm_connector *connector;
2213
2214 drm_modeset_lock_all(dev);
2215 seq_printf(m, "CRTC info\n");
2216 seq_printf(m, "---------\n");
2217 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2219
2220 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2221 crtc->base.id, pipe_name(intel_crtc->pipe),
2222 intel_crtc->active ? "yes" : "no");
2223 if (intel_crtc->active)
2224 intel_crtc_info(m, intel_crtc);
2225 }
2226
2227 seq_printf(m, "\n");
2228 seq_printf(m, "Connector info\n");
2229 seq_printf(m, "--------------\n");
2230 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2231 intel_connector_info(m, connector);
2232 }
2233 drm_modeset_unlock_all(dev);
2234
2235 return 0;
2236}
2237
2077struct pipe_crc_info { 2238struct pipe_crc_info {
2078 const char *name; 2239 const char *name;
2079 struct drm_device *dev; 2240 struct drm_device *dev;
@@ -3519,6 +3680,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
3519 {"i915_energy_uJ", i915_energy_uJ, 0}, 3680 {"i915_energy_uJ", i915_energy_uJ, 0},
3520 {"i915_pc8_status", i915_pc8_status, 0}, 3681 {"i915_pc8_status", i915_pc8_status, 0},
3521 {"i915_power_domain_info", i915_power_domain_info, 0}, 3682 {"i915_power_domain_info", i915_power_domain_info, 0},
3683 {"i915_display_info", i915_display_info, 0},
3522}; 3684};
3523#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 3685#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3524 3686
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 258b1be20db3..7688abc83fc0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -626,9 +626,8 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
626 struct drm_file *file_priv) 626 struct drm_file *file_priv)
627{ 627{
628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
629 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 629 struct drm_i915_master_private *master_priv;
630 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 630 drm_i915_sarea_t *sarea_priv;
631 master_priv->sarea_priv;
632 drm_i915_batchbuffer_t *batch = data; 631 drm_i915_batchbuffer_t *batch = data;
633 int ret; 632 int ret;
634 struct drm_clip_rect *cliprects = NULL; 633 struct drm_clip_rect *cliprects = NULL;
@@ -636,6 +635,9 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
636 if (drm_core_check_feature(dev, DRIVER_MODESET)) 635 if (drm_core_check_feature(dev, DRIVER_MODESET))
637 return -ENODEV; 636 return -ENODEV;
638 637
638 master_priv = dev->primary->master->driver_priv;
639 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
640
639 if (!dev_priv->dri1.allow_batchbuffer) { 641 if (!dev_priv->dri1.allow_batchbuffer) {
640 DRM_ERROR("Batchbuffer ioctl disabled\n"); 642 DRM_ERROR("Batchbuffer ioctl disabled\n");
641 return -EINVAL; 643 return -EINVAL;
@@ -682,9 +684,8 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
682 struct drm_file *file_priv) 684 struct drm_file *file_priv)
683{ 685{
684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 686 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
685 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 687 struct drm_i915_master_private *master_priv;
686 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *) 688 drm_i915_sarea_t *sarea_priv;
687 master_priv->sarea_priv;
688 drm_i915_cmdbuffer_t *cmdbuf = data; 689 drm_i915_cmdbuffer_t *cmdbuf = data;
689 struct drm_clip_rect *cliprects = NULL; 690 struct drm_clip_rect *cliprects = NULL;
690 void *batch_data; 691 void *batch_data;
@@ -696,6 +697,9 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
696 if (drm_core_check_feature(dev, DRIVER_MODESET)) 697 if (drm_core_check_feature(dev, DRIVER_MODESET))
697 return -ENODEV; 698 return -ENODEV;
698 699
700 master_priv = dev->primary->master->driver_priv;
701 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
702
699 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 703 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
700 704
701 if (cmdbuf->num_cliprects < 0) 705 if (cmdbuf->num_cliprects < 0)
@@ -1442,7 +1446,7 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1442 1446
1443static void i915_dump_device_info(struct drm_i915_private *dev_priv) 1447static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1444{ 1448{
1445 const struct intel_device_info *info = dev_priv->info; 1449 const struct intel_device_info *info = &dev_priv->info;
1446 1450
1447#define PRINT_S(name) "%s" 1451#define PRINT_S(name) "%s"
1448#define SEP_EMPTY 1452#define SEP_EMPTY
@@ -1459,6 +1463,58 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1459#undef SEP_COMMA 1463#undef SEP_COMMA
1460} 1464}
1461 1465
1466/*
1467 * Determine various intel_device_info fields at runtime.
1468 *
1469 * Use it when either:
1470 * - it's judged too laborious to fill n static structures with the limit
1471 * when a simple if statement does the job,
1472 * - run-time checks (eg read fuse/strap registers) are needed.
1473 *
1474 * This function needs to be called:
1475 * - after the MMIO has been setup as we are reading registers,
1476 * - after the PCH has been detected,
1477 * - before the first usage of the fields it can tweak.
1478 */
1479static void intel_device_info_runtime_init(struct drm_device *dev)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct intel_device_info *info;
1483
1484 info = (struct intel_device_info *)&dev_priv->info;
1485
1486 info->num_sprites = 1;
1487 if (IS_VALLEYVIEW(dev))
1488 info->num_sprites = 2;
1489
1490 if (i915.disable_display) {
1491 DRM_INFO("Display disabled (module parameter)\n");
1492 info->num_pipes = 0;
1493 } else if (info->num_pipes > 0 &&
1494 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1495 !IS_VALLEYVIEW(dev)) {
1496 u32 fuse_strap = I915_READ(FUSE_STRAP);
1497 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1498
1499 /*
1500 * SFUSE_STRAP is supposed to have a bit signalling the display
1501 * is fused off. Unfortunately it seems that, at least in
1502 * certain cases, fused off display means that PCH display
1503 * reads don't land anywhere. In that case, we read 0s.
1504 *
1505 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1506 * should be set when taking over after the firmware.
1507 */
1508 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1509 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1510 (dev_priv->pch_type == PCH_CPT &&
1511 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1512 DRM_INFO("Display fused off, disabling\n");
1513 info->num_pipes = 0;
1514 }
1515 }
1516}
1517
1462/** 1518/**
1463 * i915_driver_load - setup chip and create an initial config 1519 * i915_driver_load - setup chip and create an initial config
1464 * @dev: DRM device 1520 * @dev: DRM device
@@ -1473,7 +1529,7 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1473int i915_driver_load(struct drm_device *dev, unsigned long flags) 1529int i915_driver_load(struct drm_device *dev, unsigned long flags)
1474{ 1530{
1475 struct drm_i915_private *dev_priv; 1531 struct drm_i915_private *dev_priv;
1476 struct intel_device_info *info; 1532 struct intel_device_info *info, *device_info;
1477 int ret = 0, mmio_bar, mmio_size; 1533 int ret = 0, mmio_bar, mmio_size;
1478 uint32_t aperture_size; 1534 uint32_t aperture_size;
1479 1535
@@ -1496,7 +1552,10 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1496 1552
1497 dev->dev_private = (void *)dev_priv; 1553 dev->dev_private = (void *)dev_priv;
1498 dev_priv->dev = dev; 1554 dev_priv->dev = dev;
1499 dev_priv->info = info; 1555
1556 /* copy initial configuration to dev_priv->info */
1557 device_info = (struct intel_device_info *)&dev_priv->info;
1558 *device_info = *info;
1500 1559
1501 spin_lock_init(&dev_priv->irq_lock); 1560 spin_lock_init(&dev_priv->irq_lock);
1502 spin_lock_init(&dev_priv->gpu_error.lock); 1561 spin_lock_init(&dev_priv->gpu_error.lock);
@@ -1635,9 +1694,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1635 if (!IS_I945G(dev) && !IS_I945GM(dev)) 1694 if (!IS_I945G(dev) && !IS_I945GM(dev))
1636 pci_enable_msi(dev->pdev); 1695 pci_enable_msi(dev->pdev);
1637 1696
1638 dev_priv->num_plane = 1; 1697 intel_device_info_runtime_init(dev);
1639 if (IS_VALLEYVIEW(dev))
1640 dev_priv->num_plane = 2;
1641 1698
1642 if (INTEL_INFO(dev)->num_pipes) { 1699 if (INTEL_INFO(dev)->num_pipes) {
1643 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes); 1700 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9d8ca2a36fde..05cfcc163a72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -79,7 +79,7 @@ enum plane {
79}; 79};
80#define plane_name(p) ((p) + 'A') 80#define plane_name(p) ((p) + 'A')
81 81
82#define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') 82#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites + (s) + 'A')
83 83
84enum port { 84enum port {
85 PORT_A = 0, 85 PORT_A = 0,
@@ -164,6 +164,10 @@ enum hpd_pin {
164 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 164 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
165 if ((intel_encoder)->base.crtc == (__crtc)) 165 if ((intel_encoder)->base.crtc == (__crtc))
166 166
167#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
168 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
169 if ((intel_connector)->base.encoder == (__encoder))
170
167struct drm_i915_private; 171struct drm_i915_private;
168 172
169enum intel_dpll_id { 173enum intel_dpll_id {
@@ -530,6 +534,7 @@ struct intel_uncore {
530struct intel_device_info { 534struct intel_device_info {
531 u32 display_mmio_offset; 535 u32 display_mmio_offset;
532 u8 num_pipes:3; 536 u8 num_pipes:3;
537 u8 num_sprites:2;
533 u8 gen; 538 u8 gen;
534 u8 ring_mask; /* Rings supported by the HW */ 539 u8 ring_mask; /* Rings supported by the HW */
535 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 540 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
@@ -1390,7 +1395,7 @@ typedef struct drm_i915_private {
1390 struct drm_device *dev; 1395 struct drm_device *dev;
1391 struct kmem_cache *slab; 1396 struct kmem_cache *slab;
1392 1397
1393 const struct intel_device_info *info; 1398 const struct intel_device_info info;
1394 1399
1395 int relative_constants_mode; 1400 int relative_constants_mode;
1396 1401
@@ -1435,6 +1440,7 @@ typedef struct drm_i915_private {
1435 }; 1440 };
1436 u32 gt_irq_mask; 1441 u32 gt_irq_mask;
1437 u32 pm_irq_mask; 1442 u32 pm_irq_mask;
1443 u32 pipestat_irq_mask[I915_MAX_PIPES];
1438 1444
1439 struct work_struct hotplug_work; 1445 struct work_struct hotplug_work;
1440 bool enable_hotplug_processing; 1446 bool enable_hotplug_processing;
@@ -1450,8 +1456,6 @@ typedef struct drm_i915_private {
1450 u32 hpd_event_bits; 1456 u32 hpd_event_bits;
1451 struct timer_list hotplug_reenable_timer; 1457 struct timer_list hotplug_reenable_timer;
1452 1458
1453 int num_plane;
1454
1455 struct i915_fbc fbc; 1459 struct i915_fbc fbc;
1456 struct intel_opregion opregion; 1460 struct intel_opregion opregion;
1457 struct intel_vbt_data vbt; 1461 struct intel_vbt_data vbt;
@@ -1501,8 +1505,8 @@ typedef struct drm_i915_private {
1501 1505
1502 struct sdvo_device_mapping sdvo_mappings[2]; 1506 struct sdvo_device_mapping sdvo_mappings[2];
1503 1507
1504 struct drm_crtc *plane_to_crtc_mapping[3]; 1508 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1505 struct drm_crtc *pipe_to_crtc_mapping[3]; 1509 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1506 wait_queue_head_t pending_flip_queue; 1510 wait_queue_head_t pending_flip_queue;
1507 1511
1508#ifdef CONFIG_DEBUG_FS 1512#ifdef CONFIG_DEBUG_FS
@@ -1799,7 +1803,7 @@ struct drm_i915_file_private {
1799 atomic_t rps_wait_boost; 1803 atomic_t rps_wait_boost;
1800}; 1804};
1801 1805
1802#define INTEL_INFO(dev) (to_i915(dev)->info) 1806#define INTEL_INFO(dev) (&to_i915(dev)->info)
1803 1807
1804#define IS_I830(dev) ((dev)->pdev->device == 0x3577) 1808#define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1805#define IS_845G(dev) ((dev)->pdev->device == 0x2562) 1809#define IS_845G(dev) ((dev)->pdev->device == 0x2562)
@@ -1953,18 +1957,20 @@ struct i915_params {
1953 int vbt_sdvo_panel_type; 1957 int vbt_sdvo_panel_type;
1954 int enable_rc6; 1958 int enable_rc6;
1955 int enable_fbc; 1959 int enable_fbc;
1956 bool enable_hangcheck;
1957 int enable_ppgtt; 1960 int enable_ppgtt;
1958 int enable_psr; 1961 int enable_psr;
1959 unsigned int preliminary_hw_support; 1962 unsigned int preliminary_hw_support;
1960 int disable_power_well; 1963 int disable_power_well;
1961 int enable_ips; 1964 int enable_ips;
1962 bool fastboot;
1963 int enable_pc8; 1965 int enable_pc8;
1964 int pc8_timeout; 1966 int pc8_timeout;
1967 int invert_brightness;
1968 /* leave bools at the end to not create holes */
1969 bool enable_hangcheck;
1970 bool fastboot;
1965 bool prefault_disable; 1971 bool prefault_disable;
1966 bool reset; 1972 bool reset;
1967 int invert_brightness; 1973 bool disable_display;
1968}; 1974};
1969extern struct i915_params i915 __read_mostly; 1975extern struct i915_params i915 __read_mostly;
1970 1976
@@ -2012,10 +2018,12 @@ extern void intel_uncore_check_errors(struct drm_device *dev);
2012extern void intel_uncore_fini(struct drm_device *dev); 2018extern void intel_uncore_fini(struct drm_device *dev);
2013 2019
2014void 2020void
2015i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); 2021i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2022 u32 status_mask);
2016 2023
2017void 2024void
2018i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); 2025i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe,
2026 u32 status_mask);
2019 2027
2020/* i915_gem.c */ 2028/* i915_gem.c */
2021int i915_gem_init_ioctl(struct drm_device *dev, void *data, 2029int i915_gem_init_ioctl(struct drm_device *dev, void *data,
@@ -2076,14 +2084,14 @@ void i915_init_vm(struct drm_i915_private *dev_priv,
2076void i915_gem_free_object(struct drm_gem_object *obj); 2084void i915_gem_free_object(struct drm_gem_object *obj);
2077void i915_gem_vma_destroy(struct i915_vma *vma); 2085void i915_gem_vma_destroy(struct i915_vma *vma);
2078 2086
2087#define PIN_MAPPABLE 0x1
2088#define PIN_NONBLOCK 0x2
2089#define PIN_GLOBAL 0x4
2079int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2090int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2080 struct i915_address_space *vm, 2091 struct i915_address_space *vm,
2081 uint32_t alignment, 2092 uint32_t alignment,
2082 bool map_and_fenceable, 2093 unsigned flags);
2083 bool nonblocking);
2084void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2085int __must_check i915_vma_unbind(struct i915_vma *vma); 2094int __must_check i915_vma_unbind(struct i915_vma *vma);
2086int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj);
2087int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2095int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2088void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2096void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2089void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2097void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
@@ -2283,13 +2291,19 @@ i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2283static inline int __must_check 2291static inline int __must_check
2284i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2292i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2285 uint32_t alignment, 2293 uint32_t alignment,
2286 bool map_and_fenceable, 2294 unsigned flags)
2287 bool nonblocking)
2288{ 2295{
2289 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, 2296 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2290 map_and_fenceable, nonblocking);
2291} 2297}
2292 2298
2299static inline int
2300i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2301{
2302 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2303}
2304
2305void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2306
2293/* i915_gem_context.c */ 2307/* i915_gem_context.c */
2294#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) 2308#define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2295int __must_check i915_gem_context_init(struct drm_device *dev); 2309int __must_check i915_gem_context_init(struct drm_device *dev);
@@ -2331,8 +2345,7 @@ int __must_check i915_gem_evict_something(struct drm_device *dev,
2331 int min_size, 2345 int min_size,
2332 unsigned alignment, 2346 unsigned alignment,
2333 unsigned cache_level, 2347 unsigned cache_level,
2334 bool mappable, 2348 unsigned flags);
2335 bool nonblock);
2336int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2349int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2337int i915_gem_evict_everything(struct drm_device *dev); 2350int i915_gem_evict_everything(struct drm_device *dev);
2338 2351
@@ -2547,6 +2560,7 @@ extern void intel_modeset_suspend_hw(struct drm_device *dev);
2547extern void intel_modeset_init(struct drm_device *dev); 2560extern void intel_modeset_init(struct drm_device *dev);
2548extern void intel_modeset_gem_init(struct drm_device *dev); 2561extern void intel_modeset_gem_init(struct drm_device *dev);
2549extern void intel_modeset_cleanup(struct drm_device *dev); 2562extern void intel_modeset_cleanup(struct drm_device *dev);
2563extern void intel_connector_unregister(struct intel_connector *);
2550extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2564extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2551extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2565extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2552 bool force_restore); 2566 bool force_restore);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index a8a069f97c56..3618bb0cda0a 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -43,12 +43,6 @@ static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *o
43static __must_check int 43static __must_check int
44i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 44i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
45 bool readonly); 45 bool readonly);
46static __must_check int
47i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
48 struct i915_address_space *vm,
49 unsigned alignment,
50 bool map_and_fenceable,
51 bool nonblocking);
52static int i915_gem_phys_pwrite(struct drm_device *dev, 46static int i915_gem_phys_pwrite(struct drm_device *dev,
53 struct drm_i915_gem_object *obj, 47 struct drm_i915_gem_object *obj,
54 struct drm_i915_gem_pwrite *args, 48 struct drm_i915_gem_pwrite *args,
@@ -605,7 +599,7 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev,
605 char __user *user_data; 599 char __user *user_data;
606 int page_offset, page_length, ret; 600 int page_offset, page_length, ret;
607 601
608 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); 602 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
609 if (ret) 603 if (ret)
610 goto out; 604 goto out;
611 605
@@ -1014,7 +1008,8 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1014 struct timespec *timeout, 1008 struct timespec *timeout,
1015 struct drm_i915_file_private *file_priv) 1009 struct drm_i915_file_private *file_priv)
1016{ 1010{
1017 drm_i915_private_t *dev_priv = ring->dev->dev_private; 1011 struct drm_device *dev = ring->dev;
1012 drm_i915_private_t *dev_priv = dev->dev_private;
1018 const bool irq_test_in_progress = 1013 const bool irq_test_in_progress =
1019 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); 1014 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1020 struct timespec before, now; 1015 struct timespec before, now;
@@ -1029,7 +1024,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1029 1024
1030 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0; 1025 timeout_expire = timeout ? jiffies + timespec_to_jiffies_timeout(timeout) : 0;
1031 1026
1032 if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) { 1027 if (INTEL_INFO(dev)->gen >= 6 && can_wait_boost(file_priv)) {
1033 gen6_rps_boost(dev_priv); 1028 gen6_rps_boost(dev_priv);
1034 if (file_priv) 1029 if (file_priv)
1035 mod_delayed_work(dev_priv->wq, 1030 mod_delayed_work(dev_priv->wq,
@@ -1184,7 +1179,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1184 */ 1179 */
1185static __must_check int 1180static __must_check int
1186i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, 1181i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1187 struct drm_file *file, 1182 struct drm_i915_file_private *file_priv,
1188 bool readonly) 1183 bool readonly)
1189{ 1184{
1190 struct drm_device *dev = obj->base.dev; 1185 struct drm_device *dev = obj->base.dev;
@@ -1211,7 +1206,7 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1211 1206
1212 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 1207 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1213 mutex_unlock(&dev->struct_mutex); 1208 mutex_unlock(&dev->struct_mutex);
1214 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv); 1209 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1215 mutex_lock(&dev->struct_mutex); 1210 mutex_lock(&dev->struct_mutex);
1216 if (ret) 1211 if (ret)
1217 return ret; 1212 return ret;
@@ -1260,7 +1255,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1260 * We will repeat the flush holding the lock in the normal manner 1255 * We will repeat the flush holding the lock in the normal manner
1261 * to catch cases where we are gazumped. 1256 * to catch cases where we are gazumped.
1262 */ 1257 */
1263 ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain); 1258 ret = i915_gem_object_wait_rendering__nonblocking(obj,
1259 file->driver_priv,
1260 !write_domain);
1264 if (ret) 1261 if (ret)
1265 goto unref; 1262 goto unref;
1266 1263
@@ -1392,6 +1389,15 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1392 1389
1393 trace_i915_gem_object_fault(obj, page_offset, true, write); 1390 trace_i915_gem_object_fault(obj, page_offset, true, write);
1394 1391
1392 /* Try to flush the object off the GPU first without holding the lock.
1393 * Upon reacquiring the lock, we will perform our sanity checks and then
1394 * repeat the flush holding the lock in the normal manner to catch cases
1395 * where we are gazumped.
1396 */
1397 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1398 if (ret)
1399 goto unlock;
1400
1395 /* Access to snoopable pages through the GTT is incoherent. */ 1401 /* Access to snoopable pages through the GTT is incoherent. */
1396 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { 1402 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1397 ret = -EINVAL; 1403 ret = -EINVAL;
@@ -1399,7 +1405,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1399 } 1405 }
1400 1406
1401 /* Now bind it into the GTT if needed */ 1407 /* Now bind it into the GTT if needed */
1402 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); 1408 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1403 if (ret) 1409 if (ret)
1404 goto unlock; 1410 goto unlock;
1405 1411
@@ -1618,7 +1624,7 @@ i915_gem_mmap_gtt(struct drm_file *file,
1618 } 1624 }
1619 1625
1620 if (obj->madv != I915_MADV_WILLNEED) { 1626 if (obj->madv != I915_MADV_WILLNEED) {
1621 DRM_ERROR("Attempting to mmap a purgeable buffer\n"); 1627 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1622 ret = -EFAULT; 1628 ret = -EFAULT;
1623 goto out; 1629 goto out;
1624 } 1630 }
@@ -1972,7 +1978,7 @@ i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
1972 return 0; 1978 return 0;
1973 1979
1974 if (obj->madv != I915_MADV_WILLNEED) { 1980 if (obj->madv != I915_MADV_WILLNEED) {
1975 DRM_ERROR("Attempting to obtain a purgeable object\n"); 1981 DRM_DEBUG("Attempting to obtain a purgeable object\n");
1976 return -EFAULT; 1982 return -EFAULT;
1977 } 1983 }
1978 1984
@@ -2709,7 +2715,6 @@ int i915_vma_unbind(struct i915_vma *vma)
2709 2715
2710 if (!drm_mm_node_allocated(&vma->node)) { 2716 if (!drm_mm_node_allocated(&vma->node)) {
2711 i915_gem_vma_destroy(vma); 2717 i915_gem_vma_destroy(vma);
2712
2713 return 0; 2718 return 0;
2714 } 2719 }
2715 2720
@@ -2761,26 +2766,6 @@ int i915_vma_unbind(struct i915_vma *vma)
2761 return 0; 2766 return 0;
2762} 2767}
2763 2768
2764/**
2765 * Unbinds an object from the global GTT aperture.
2766 */
2767int
2768i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2769{
2770 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2771 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2772
2773 if (!i915_gem_obj_ggtt_bound(obj))
2774 return 0;
2775
2776 if (i915_gem_obj_to_ggtt(obj)->pin_count)
2777 return -EBUSY;
2778
2779 BUG_ON(obj->pages == NULL);
2780
2781 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2782}
2783
2784int i915_gpu_idle(struct drm_device *dev) 2769int i915_gpu_idle(struct drm_device *dev)
2785{ 2770{
2786 drm_i915_private_t *dev_priv = dev->dev_private; 2771 drm_i915_private_t *dev_priv = dev->dev_private;
@@ -3203,18 +3188,17 @@ static void i915_gem_verify_gtt(struct drm_device *dev)
3203/** 3188/**
3204 * Finds free space in the GTT aperture and binds the object there. 3189 * Finds free space in the GTT aperture and binds the object there.
3205 */ 3190 */
3206static int 3191static struct i915_vma *
3207i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, 3192i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3208 struct i915_address_space *vm, 3193 struct i915_address_space *vm,
3209 unsigned alignment, 3194 unsigned alignment,
3210 bool map_and_fenceable, 3195 unsigned flags)
3211 bool nonblocking)
3212{ 3196{
3213 struct drm_device *dev = obj->base.dev; 3197 struct drm_device *dev = obj->base.dev;
3214 drm_i915_private_t *dev_priv = dev->dev_private; 3198 drm_i915_private_t *dev_priv = dev->dev_private;
3215 u32 size, fence_size, fence_alignment, unfenced_alignment; 3199 u32 size, fence_size, fence_alignment, unfenced_alignment;
3216 size_t gtt_max = 3200 size_t gtt_max =
3217 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; 3201 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3218 struct i915_vma *vma; 3202 struct i915_vma *vma;
3219 int ret; 3203 int ret;
3220 3204
@@ -3226,41 +3210,39 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3226 obj->tiling_mode, true); 3210 obj->tiling_mode, true);
3227 unfenced_alignment = 3211 unfenced_alignment =
3228 i915_gem_get_gtt_alignment(dev, 3212 i915_gem_get_gtt_alignment(dev,
3229 obj->base.size, 3213 obj->base.size,
3230 obj->tiling_mode, false); 3214 obj->tiling_mode, false);
3231 3215
3232 if (alignment == 0) 3216 if (alignment == 0)
3233 alignment = map_and_fenceable ? fence_alignment : 3217 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3234 unfenced_alignment; 3218 unfenced_alignment;
3235 if (map_and_fenceable && alignment & (fence_alignment - 1)) { 3219 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3236 DRM_ERROR("Invalid object alignment requested %u\n", alignment); 3220 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3237 return -EINVAL; 3221 return ERR_PTR(-EINVAL);
3238 } 3222 }
3239 3223
3240 size = map_and_fenceable ? fence_size : obj->base.size; 3224 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3241 3225
3242 /* If the object is bigger than the entire aperture, reject it early 3226 /* If the object is bigger than the entire aperture, reject it early
3243 * before evicting everything in a vain attempt to find space. 3227 * before evicting everything in a vain attempt to find space.
3244 */ 3228 */
3245 if (obj->base.size > gtt_max) { 3229 if (obj->base.size > gtt_max) {
3246 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", 3230 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3247 obj->base.size, 3231 obj->base.size,
3248 map_and_fenceable ? "mappable" : "total", 3232 flags & PIN_MAPPABLE ? "mappable" : "total",
3249 gtt_max); 3233 gtt_max);
3250 return -E2BIG; 3234 return ERR_PTR(-E2BIG);
3251 } 3235 }
3252 3236
3253 ret = i915_gem_object_get_pages(obj); 3237 ret = i915_gem_object_get_pages(obj);
3254 if (ret) 3238 if (ret)
3255 return ret; 3239 return ERR_PTR(ret);
3256 3240
3257 i915_gem_object_pin_pages(obj); 3241 i915_gem_object_pin_pages(obj);
3258 3242
3259 vma = i915_gem_obj_lookup_or_create_vma(obj, vm); 3243 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3260 if (IS_ERR(vma)) { 3244 if (IS_ERR(vma))
3261 ret = PTR_ERR(vma);
3262 goto err_unpin; 3245 goto err_unpin;
3263 }
3264 3246
3265search_free: 3247search_free:
3266 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, 3248 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
@@ -3269,9 +3251,7 @@ search_free:
3269 DRM_MM_SEARCH_DEFAULT); 3251 DRM_MM_SEARCH_DEFAULT);
3270 if (ret) { 3252 if (ret) {
3271 ret = i915_gem_evict_something(dev, vm, size, alignment, 3253 ret = i915_gem_evict_something(dev, vm, size, alignment,
3272 obj->cache_level, 3254 obj->cache_level, flags);
3273 map_and_fenceable,
3274 nonblocking);
3275 if (ret == 0) 3255 if (ret == 0)
3276 goto search_free; 3256 goto search_free;
3277 3257
@@ -3302,19 +3282,23 @@ search_free:
3302 obj->map_and_fenceable = mappable && fenceable; 3282 obj->map_and_fenceable = mappable && fenceable;
3303 } 3283 }
3304 3284
3305 WARN_ON(map_and_fenceable && !obj->map_and_fenceable); 3285 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3286
3287 trace_i915_vma_bind(vma, flags);
3288 vma->bind_vma(vma, obj->cache_level,
3289 flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3306 3290
3307 trace_i915_vma_bind(vma, map_and_fenceable);
3308 i915_gem_verify_gtt(dev); 3291 i915_gem_verify_gtt(dev);
3309 return 0; 3292 return vma;
3310 3293
3311err_remove_node: 3294err_remove_node:
3312 drm_mm_remove_node(&vma->node); 3295 drm_mm_remove_node(&vma->node);
3313err_free_vma: 3296err_free_vma:
3314 i915_gem_vma_destroy(vma); 3297 i915_gem_vma_destroy(vma);
3298 vma = ERR_PTR(ret);
3315err_unpin: 3299err_unpin:
3316 i915_gem_object_unpin_pages(obj); 3300 i915_gem_object_unpin_pages(obj);
3317 return ret; 3301 return vma;
3318} 3302}
3319 3303
3320bool 3304bool
@@ -3506,7 +3490,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3506 } 3490 }
3507 3491
3508 list_for_each_entry(vma, &obj->vma_list, vma_link) 3492 list_for_each_entry(vma, &obj->vma_list, vma_link)
3509 vma->bind_vma(vma, cache_level, 0); 3493 if (drm_mm_node_allocated(&vma->node))
3494 vma->bind_vma(vma, cache_level,
3495 obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3510 } 3496 }
3511 3497
3512 list_for_each_entry(vma, &obj->vma_list, vma_link) 3498 list_for_each_entry(vma, &obj->vma_list, vma_link)
@@ -3675,7 +3661,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3675 * (e.g. libkms for the bootup splash), we have to ensure that we 3661 * (e.g. libkms for the bootup splash), we have to ensure that we
3676 * always use map_and_fenceable for all scanout buffers. 3662 * always use map_and_fenceable for all scanout buffers.
3677 */ 3663 */
3678 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); 3664 ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3679 if (ret) 3665 if (ret)
3680 goto err_unpin_display; 3666 goto err_unpin_display;
3681 3667
@@ -3831,52 +3817,49 @@ int
3831i915_gem_object_pin(struct drm_i915_gem_object *obj, 3817i915_gem_object_pin(struct drm_i915_gem_object *obj,
3832 struct i915_address_space *vm, 3818 struct i915_address_space *vm,
3833 uint32_t alignment, 3819 uint32_t alignment,
3834 bool map_and_fenceable, 3820 unsigned flags)
3835 bool nonblocking)
3836{ 3821{
3837 const u32 flags = map_and_fenceable ? GLOBAL_BIND : 0;
3838 struct i915_vma *vma; 3822 struct i915_vma *vma;
3839 int ret; 3823 int ret;
3840 3824
3841 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); 3825 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
3826 return -EINVAL;
3842 3827
3843 vma = i915_gem_obj_to_vma(obj, vm); 3828 vma = i915_gem_obj_to_vma(obj, vm);
3844
3845 if (vma) { 3829 if (vma) {
3846 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) 3830 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3847 return -EBUSY; 3831 return -EBUSY;
3848 3832
3849 if ((alignment && 3833 if ((alignment &&
3850 vma->node.start & (alignment - 1)) || 3834 vma->node.start & (alignment - 1)) ||
3851 (map_and_fenceable && !obj->map_and_fenceable)) { 3835 (flags & PIN_MAPPABLE && !obj->map_and_fenceable)) {
3852 WARN(vma->pin_count, 3836 WARN(vma->pin_count,
3853 "bo is already pinned with incorrect alignment:" 3837 "bo is already pinned with incorrect alignment:"
3854 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," 3838 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3855 " obj->map_and_fenceable=%d\n", 3839 " obj->map_and_fenceable=%d\n",
3856 i915_gem_obj_offset(obj, vm), alignment, 3840 i915_gem_obj_offset(obj, vm), alignment,
3857 map_and_fenceable, 3841 flags & PIN_MAPPABLE,
3858 obj->map_and_fenceable); 3842 obj->map_and_fenceable);
3859 ret = i915_vma_unbind(vma); 3843 ret = i915_vma_unbind(vma);
3860 if (ret) 3844 if (ret)
3861 return ret; 3845 return ret;
3846
3847 vma = NULL;
3862 } 3848 }
3863 } 3849 }
3864 3850
3865 if (!i915_gem_obj_bound(obj, vm)) { 3851 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
3866 ret = i915_gem_object_bind_to_vm(obj, vm, alignment, 3852 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
3867 map_and_fenceable, 3853 if (IS_ERR(vma))
3868 nonblocking); 3854 return PTR_ERR(vma);
3869 if (ret)
3870 return ret;
3871
3872 } 3855 }
3873 3856
3874 vma = i915_gem_obj_to_vma(obj, vm); 3857 if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
3875 3858 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
3876 vma->bind_vma(vma, obj->cache_level, flags);
3877 3859
3878 i915_gem_obj_to_vma(obj, vm)->pin_count++; 3860 vma->pin_count++;
3879 obj->pin_mappable |= map_and_fenceable; 3861 if (flags & PIN_MAPPABLE)
3862 obj->pin_mappable |= true;
3880 3863
3881 return 0; 3864 return 0;
3882} 3865}
@@ -3916,13 +3899,13 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3916 } 3899 }
3917 3900
3918 if (obj->madv != I915_MADV_WILLNEED) { 3901 if (obj->madv != I915_MADV_WILLNEED) {
3919 DRM_ERROR("Attempting to pin a purgeable buffer\n"); 3902 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
3920 ret = -EFAULT; 3903 ret = -EFAULT;
3921 goto out; 3904 goto out;
3922 } 3905 }
3923 3906
3924 if (obj->pin_filp != NULL && obj->pin_filp != file) { 3907 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3925 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", 3908 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
3926 args->handle); 3909 args->handle);
3927 ret = -EINVAL; 3910 ret = -EINVAL;
3928 goto out; 3911 goto out;
@@ -3934,7 +3917,7 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3934 } 3917 }
3935 3918
3936 if (obj->user_pin_count == 0) { 3919 if (obj->user_pin_count == 0) {
3937 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); 3920 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
3938 if (ret) 3921 if (ret)
3939 goto out; 3922 goto out;
3940 } 3923 }
@@ -3969,7 +3952,7 @@ i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3969 } 3952 }
3970 3953
3971 if (obj->pin_filp != file) { 3954 if (obj->pin_filp != file) {
3972 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", 3955 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3973 args->handle); 3956 args->handle);
3974 ret = -EINVAL; 3957 ret = -EINVAL;
3975 goto out; 3958 goto out;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 19fd3629795c..f8c21a6dd663 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -258,8 +258,7 @@ i915_gem_create_context(struct drm_device *dev,
258 * context. 258 * context.
259 */ 259 */
260 ret = i915_gem_obj_ggtt_pin(ctx->obj, 260 ret = i915_gem_obj_ggtt_pin(ctx->obj,
261 get_context_alignment(dev), 261 get_context_alignment(dev), 0);
262 false, false);
263 if (ret) { 262 if (ret) {
264 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); 263 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
265 goto err_destroy; 264 goto err_destroy;
@@ -335,8 +334,7 @@ void i915_gem_context_reset(struct drm_device *dev)
335 334
336 if (i == RCS) { 335 if (i == RCS) {
337 WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj, 336 WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj,
338 get_context_alignment(dev), 337 get_context_alignment(dev), 0));
339 false, false));
340 /* Fake a finish/inactive */ 338 /* Fake a finish/inactive */
341 dctx->obj->base.write_domain = 0; 339 dctx->obj->base.write_domain = 0;
342 dctx->obj->active = 0; 340 dctx->obj->active = 0;
@@ -612,8 +610,7 @@ static int do_switch(struct intel_ring_buffer *ring,
612 /* Trying to pin first makes error handling easier. */ 610 /* Trying to pin first makes error handling easier. */
613 if (ring == &dev_priv->ring[RCS]) { 611 if (ring == &dev_priv->ring[RCS]) {
614 ret = i915_gem_obj_ggtt_pin(to->obj, 612 ret = i915_gem_obj_ggtt_pin(to->obj,
615 get_context_alignment(ring->dev), 613 get_context_alignment(ring->dev), 0);
616 false, false);
617 if (ret) 614 if (ret)
618 return ret; 615 return ret;
619 } 616 }
diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
index 5168d6a08054..8a78f7885cba 100644
--- a/drivers/gpu/drm/i915/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/i915_gem_evict.c
@@ -68,7 +68,7 @@ mark_free(struct i915_vma *vma, struct list_head *unwind)
68int 68int
69i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm, 69i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm,
70 int min_size, unsigned alignment, unsigned cache_level, 70 int min_size, unsigned alignment, unsigned cache_level,
71 bool mappable, bool nonblocking) 71 unsigned flags)
72{ 72{
73 drm_i915_private_t *dev_priv = dev->dev_private; 73 drm_i915_private_t *dev_priv = dev->dev_private;
74 struct list_head eviction_list, unwind_list; 74 struct list_head eviction_list, unwind_list;
@@ -76,7 +76,7 @@ i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm,
76 int ret = 0; 76 int ret = 0;
77 int pass = 0; 77 int pass = 0;
78 78
79 trace_i915_gem_evict(dev, min_size, alignment, mappable); 79 trace_i915_gem_evict(dev, min_size, alignment, flags);
80 80
81 /* 81 /*
82 * The goal is to evict objects and amalgamate space in LRU order. 82 * The goal is to evict objects and amalgamate space in LRU order.
@@ -102,7 +102,7 @@ i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm,
102 */ 102 */
103 103
104 INIT_LIST_HEAD(&unwind_list); 104 INIT_LIST_HEAD(&unwind_list);
105 if (mappable) { 105 if (flags & PIN_MAPPABLE) {
106 BUG_ON(!i915_is_ggtt(vm)); 106 BUG_ON(!i915_is_ggtt(vm));
107 drm_mm_init_scan_with_range(&vm->mm, min_size, 107 drm_mm_init_scan_with_range(&vm->mm, min_size,
108 alignment, cache_level, 0, 108 alignment, cache_level, 0,
@@ -117,7 +117,7 @@ search_again:
117 goto found; 117 goto found;
118 } 118 }
119 119
120 if (nonblocking) 120 if (flags & PIN_NONBLOCK)
121 goto none; 121 goto none;
122 122
123 /* Now merge in the soon-to-be-expired objects... */ 123 /* Now merge in the soon-to-be-expired objects... */
@@ -141,7 +141,7 @@ none:
141 /* Can we unpin some objects such as idle hw contents, 141 /* Can we unpin some objects such as idle hw contents,
142 * or pending flips? 142 * or pending flips?
143 */ 143 */
144 if (nonblocking) 144 if (flags & PIN_NONBLOCK)
145 return -ENOSPC; 145 return -ENOSPC;
146 146
147 /* Only idle the GPU and repeat the search once */ 147 /* Only idle the GPU and repeat the search once */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 032def901f98..d7229ad2bd22 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -544,19 +544,23 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
544 struct drm_i915_gem_object *obj = vma->obj; 544 struct drm_i915_gem_object *obj = vma->obj;
545 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 545 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
546 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; 546 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
547 bool need_fence, need_mappable; 547 bool need_fence;
548 u32 flags = (entry->flags & EXEC_OBJECT_NEEDS_GTT) && 548 unsigned flags;
549 !vma->obj->has_global_gtt_mapping ? GLOBAL_BIND : 0;
550 int ret; 549 int ret;
551 550
551 flags = 0;
552
552 need_fence = 553 need_fence =
553 has_fenced_gpu_access && 554 has_fenced_gpu_access &&
554 entry->flags & EXEC_OBJECT_NEEDS_FENCE && 555 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
555 obj->tiling_mode != I915_TILING_NONE; 556 obj->tiling_mode != I915_TILING_NONE;
556 need_mappable = need_fence || need_reloc_mappable(vma); 557 if (need_fence || need_reloc_mappable(vma))
558 flags |= PIN_MAPPABLE;
557 559
558 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, need_mappable, 560 if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
559 false); 561 flags |= PIN_GLOBAL;
562
563 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
560 if (ret) 564 if (ret)
561 return ret; 565 return ret;
562 566
@@ -585,8 +589,6 @@ i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
585 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; 589 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
586 } 590 }
587 591
588 vma->bind_vma(vma, obj->cache_level, flags);
589
590 return 0; 592 return 0;
591} 593}
592 594
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a4364ae1a2d6..9673cffb07f3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -319,36 +319,53 @@ static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
319 kunmap_atomic(pt_vaddr); 319 kunmap_atomic(pt_vaddr);
320} 320}
321 321
322static void gen8_ppgtt_cleanup(struct i915_address_space *vm) 322static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
323{
324 int i;
325
326 for (i = 0; i < ppgtt->num_pd_pages ; i++)
327 kfree(ppgtt->gen8_pt_dma_addr[i]);
328
329 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
330 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
331}
332
333static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
323{ 334{
324 struct i915_hw_ppgtt *ppgtt =
325 container_of(vm, struct i915_hw_ppgtt, base);
326 int i, j; 335 int i, j;
327 336
328 list_del(&vm->global_link); 337 for (i = 0; i < ppgtt->num_pd_pages; i++) {
329 drm_mm_takedown(&vm->mm); 338 /* TODO: In the future we'll support sparse mappings, so this
339 * will have to change. */
340 if (!ppgtt->pd_dma_addr[i])
341 continue;
330 342
331 for (i = 0; i < ppgtt->num_pd_pages ; i++) { 343 pci_unmap_page(ppgtt->base.dev->pdev,
332 if (ppgtt->pd_dma_addr[i]) { 344 ppgtt->pd_dma_addr[i],
333 pci_unmap_page(ppgtt->base.dev->pdev, 345 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
334 ppgtt->pd_dma_addr[i],
335 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
336 346
337 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { 347 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
338 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j]; 348 dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
339 if (addr) 349 if (addr)
340 pci_unmap_page(ppgtt->base.dev->pdev, 350 pci_unmap_page(ppgtt->base.dev->pdev,
341 addr, 351 addr,
342 PAGE_SIZE, 352 PAGE_SIZE,
343 PCI_DMA_BIDIRECTIONAL); 353 PCI_DMA_BIDIRECTIONAL);
344 354
345 }
346 } 355 }
347 kfree(ppgtt->gen8_pt_dma_addr[i]);
348 } 356 }
357}
349 358
350 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT)); 359static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
351 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT)); 360{
361 struct i915_hw_ppgtt *ppgtt =
362 container_of(vm, struct i915_hw_ppgtt, base);
363
364 list_del(&vm->global_link);
365 drm_mm_takedown(&vm->mm);
366
367 gen8_ppgtt_unmap_pages(ppgtt);
368 gen8_ppgtt_free(ppgtt);
352} 369}
353 370
354/** 371/**
@@ -868,7 +885,7 @@ alloc:
868 if (ret == -ENOSPC && !retried) { 885 if (ret == -ENOSPC && !retried) {
869 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, 886 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
870 GEN6_PD_SIZE, GEN6_PD_ALIGN, 887 GEN6_PD_SIZE, GEN6_PD_ALIGN,
871 I915_CACHE_NONE, false, true); 888 I915_CACHE_NONE, 0);
872 if (ret) 889 if (ret)
873 return ret; 890 return ret;
874 891
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index e9c94c91c6a5..f68aee31e565 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -419,6 +419,16 @@ done:
419 return ret; 419 return ret;
420} 420}
421 421
422static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
423 enum pipe pipe)
424{
425 struct drm_i915_private *dev_priv = dev->dev_private;
426 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
428
429 return !intel_crtc->cpu_fifo_underrun_disabled;
430}
431
422/** 432/**
423 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages 433 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
424 * @dev: drm device 434 * @dev: drm device
@@ -473,38 +483,102 @@ done:
473 483
474 484
475void 485void
476i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) 486__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
487 u32 enable_mask, u32 status_mask)
477{ 488{
478 u32 reg = PIPESTAT(pipe); 489 u32 reg = PIPESTAT(pipe);
479 u32 pipestat = I915_READ(reg) & 0x7fff0000; 490 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
480 491
481 assert_spin_locked(&dev_priv->irq_lock); 492 assert_spin_locked(&dev_priv->irq_lock);
482 493
483 if ((pipestat & mask) == mask) 494 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
495 status_mask & ~PIPESTAT_INT_STATUS_MASK))
496 return;
497
498 if ((pipestat & enable_mask) == enable_mask)
484 return; 499 return;
485 500
501 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
502
486 /* Enable the interrupt, clear any pending status */ 503 /* Enable the interrupt, clear any pending status */
487 pipestat |= mask | (mask >> 16); 504 pipestat |= enable_mask | status_mask;
488 I915_WRITE(reg, pipestat); 505 I915_WRITE(reg, pipestat);
489 POSTING_READ(reg); 506 POSTING_READ(reg);
490} 507}
491 508
492void 509void
493i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask) 510__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
511 u32 enable_mask, u32 status_mask)
494{ 512{
495 u32 reg = PIPESTAT(pipe); 513 u32 reg = PIPESTAT(pipe);
496 u32 pipestat = I915_READ(reg) & 0x7fff0000; 514 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
497 515
498 assert_spin_locked(&dev_priv->irq_lock); 516 assert_spin_locked(&dev_priv->irq_lock);
499 517
500 if ((pipestat & mask) == 0) 518 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
519 status_mask & ~PIPESTAT_INT_STATUS_MASK))
520 return;
521
522 if ((pipestat & enable_mask) == 0)
501 return; 523 return;
502 524
503 pipestat &= ~mask; 525 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
526
527 pipestat &= ~enable_mask;
504 I915_WRITE(reg, pipestat); 528 I915_WRITE(reg, pipestat);
505 POSTING_READ(reg); 529 POSTING_READ(reg);
506} 530}
507 531
532static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
533{
534 u32 enable_mask = status_mask << 16;
535
536 /*
537 * On pipe A we don't support the PSR interrupt yet, on pipe B the
538 * same bit MBZ.
539 */
540 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
541 return 0;
542
543 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
544 SPRITE0_FLIP_DONE_INT_EN_VLV |
545 SPRITE1_FLIP_DONE_INT_EN_VLV);
546 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
547 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
548 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
549 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
550
551 return enable_mask;
552}
553
554void
555i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
556 u32 status_mask)
557{
558 u32 enable_mask;
559
560 if (IS_VALLEYVIEW(dev_priv->dev))
561 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
562 status_mask);
563 else
564 enable_mask = status_mask << 16;
565 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
566}
567
568void
569i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
570 u32 status_mask)
571{
572 u32 enable_mask;
573
574 if (IS_VALLEYVIEW(dev_priv->dev))
575 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
576 status_mask);
577 else
578 enable_mask = status_mask << 16;
579 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
580}
581
508/** 582/**
509 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 583 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
510 */ 584 */
@@ -518,10 +592,10 @@ static void i915_enable_asle_pipestat(struct drm_device *dev)
518 592
519 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 593 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
520 594
521 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); 595 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
522 if (INTEL_INFO(dev)->gen >= 4) 596 if (INTEL_INFO(dev)->gen >= 4)
523 i915_enable_pipestat(dev_priv, PIPE_A, 597 i915_enable_pipestat(dev_priv, PIPE_A,
524 PIPE_LEGACY_BLC_EVENT_ENABLE); 598 PIPE_LEGACY_BLC_EVENT_STATUS);
525 599
526 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 600 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
527} 601}
@@ -1479,18 +1553,48 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1479static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) 1553static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1480{ 1554{
1481 struct drm_i915_private *dev_priv = dev->dev_private; 1555 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 pipe_stats[I915_MAX_PIPES]; 1556 u32 pipe_stats[I915_MAX_PIPES] = { };
1483 int pipe; 1557 int pipe;
1484 1558
1485 spin_lock(&dev_priv->irq_lock); 1559 spin_lock(&dev_priv->irq_lock);
1486 for_each_pipe(pipe) { 1560 for_each_pipe(pipe) {
1487 int reg = PIPESTAT(pipe); 1561 int reg;
1488 pipe_stats[pipe] = I915_READ(reg); 1562 u32 mask, iir_bit = 0;
1563
1564 /*
1565 * PIPESTAT bits get signalled even when the interrupt is
1566 * disabled with the mask bits, and some of the status bits do
1567 * not generate interrupts at all (like the underrun bit). Hence
1568 * we need to be careful that we only handle what we want to
1569 * handle.
1570 */
1571 mask = 0;
1572 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1573 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1574
1575 switch (pipe) {
1576 case PIPE_A:
1577 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1578 break;
1579 case PIPE_B:
1580 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1581 break;
1582 }
1583 if (iir & iir_bit)
1584 mask |= dev_priv->pipestat_irq_mask[pipe];
1585
1586 if (!mask)
1587 continue;
1588
1589 reg = PIPESTAT(pipe);
1590 mask |= PIPESTAT_INT_ENABLE_MASK;
1591 pipe_stats[pipe] = I915_READ(reg) & mask;
1489 1592
1490 /* 1593 /*
1491 * Clear the PIPE*STAT regs before the IIR 1594 * Clear the PIPE*STAT regs before the IIR
1492 */ 1595 */
1493 if (pipe_stats[pipe] & 0x8000ffff) 1596 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1597 PIPESTAT_INT_STATUS_MASK))
1494 I915_WRITE(reg, pipe_stats[pipe]); 1598 I915_WRITE(reg, pipe_stats[pipe]);
1495 } 1599 }
1496 spin_unlock(&dev_priv->irq_lock); 1600 spin_unlock(&dev_priv->irq_lock);
@@ -2269,13 +2373,13 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe)
2269 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2373 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2270 if (INTEL_INFO(dev)->gen >= 4) 2374 if (INTEL_INFO(dev)->gen >= 4)
2271 i915_enable_pipestat(dev_priv, pipe, 2375 i915_enable_pipestat(dev_priv, pipe,
2272 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2376 PIPE_START_VBLANK_INTERRUPT_STATUS);
2273 else 2377 else
2274 i915_enable_pipestat(dev_priv, pipe, 2378 i915_enable_pipestat(dev_priv, pipe,
2275 PIPE_VBLANK_INTERRUPT_ENABLE); 2379 PIPE_VBLANK_INTERRUPT_STATUS);
2276 2380
2277 /* maintain vblank delivery even in deep C-states */ 2381 /* maintain vblank delivery even in deep C-states */
2278 if (dev_priv->info->gen == 3) 2382 if (INTEL_INFO(dev)->gen == 3)
2279 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 2383 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
2280 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2384 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2281 2385
@@ -2309,7 +2413,7 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2309 2413
2310 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2414 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2311 i915_enable_pipestat(dev_priv, pipe, 2415 i915_enable_pipestat(dev_priv, pipe,
2312 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2416 PIPE_START_VBLANK_INTERRUPT_STATUS);
2313 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2417 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2314 2418
2315 return 0; 2419 return 0;
@@ -2340,12 +2444,12 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe)
2340 unsigned long irqflags; 2444 unsigned long irqflags;
2341 2445
2342 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2446 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2343 if (dev_priv->info->gen == 3) 2447 if (INTEL_INFO(dev)->gen == 3)
2344 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 2448 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
2345 2449
2346 i915_disable_pipestat(dev_priv, pipe, 2450 i915_disable_pipestat(dev_priv, pipe,
2347 PIPE_VBLANK_INTERRUPT_ENABLE | 2451 PIPE_VBLANK_INTERRUPT_STATUS |
2348 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2452 PIPE_START_VBLANK_INTERRUPT_STATUS);
2349 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2453 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2350} 2454}
2351 2455
@@ -2368,7 +2472,7 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2368 2472
2369 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 2473 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2370 i915_disable_pipestat(dev_priv, pipe, 2474 i915_disable_pipestat(dev_priv, pipe,
2371 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2475 PIPE_START_VBLANK_INTERRUPT_STATUS);
2372 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 2476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2373} 2477}
2374 2478
@@ -2916,8 +3020,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
2916{ 3020{
2917 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3021 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2918 u32 enable_mask; 3022 u32 enable_mask;
2919 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | 3023 u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
2920 PIPE_CRC_DONE_ENABLE; 3024 PIPE_CRC_DONE_INTERRUPT_STATUS;
2921 unsigned long irqflags; 3025 unsigned long irqflags;
2922 3026
2923 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 3027 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
@@ -2948,7 +3052,7 @@ static int valleyview_irq_postinstall(struct drm_device *dev)
2948 * just to make the assert_spin_locked check happy. */ 3052 * just to make the assert_spin_locked check happy. */
2949 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3053 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2950 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); 3054 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable);
2951 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 3055 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2952 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); 3056 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable);
2953 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3057 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2954 3058
@@ -3171,8 +3275,8 @@ static int i8xx_irq_postinstall(struct drm_device *dev)
3171 /* Interrupt setup is already guaranteed to be single-threaded, this is 3275 /* Interrupt setup is already guaranteed to be single-threaded, this is
3172 * just to make the assert_spin_locked check happy. */ 3276 * just to make the assert_spin_locked check happy. */
3173 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3277 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3174 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3278 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3175 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3279 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3176 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3280 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3177 3281
3178 return 0; 3282 return 0;
@@ -3354,8 +3458,8 @@ static int i915_irq_postinstall(struct drm_device *dev)
3354 /* Interrupt setup is already guaranteed to be single-threaded, this is 3458 /* Interrupt setup is already guaranteed to be single-threaded, this is
3355 * just to make the assert_spin_locked check happy. */ 3459 * just to make the assert_spin_locked check happy. */
3356 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3460 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3357 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3461 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3358 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3462 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3359 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3360 3464
3361 return 0; 3465 return 0;
@@ -3564,9 +3668,9 @@ static int i965_irq_postinstall(struct drm_device *dev)
3564 /* Interrupt setup is already guaranteed to be single-threaded, this is 3668 /* Interrupt setup is already guaranteed to be single-threaded, this is
3565 * just to make the assert_spin_locked check happy. */ 3669 * just to make the assert_spin_locked check happy. */
3566 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 3670 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3567 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 3671 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3568 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3672 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3569 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3673 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3570 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 3674 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3571 3675
3572 /* 3676 /*
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index c743057b6511..3b482585c5ae 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -47,6 +47,7 @@ struct i915_params i915 __read_mostly = {
47 .prefault_disable = 0, 47 .prefault_disable = 0,
48 .reset = true, 48 .reset = true,
49 .invert_brightness = 0, 49 .invert_brightness = 0,
50 .disable_display = 0,
50}; 51};
51 52
52module_param_named(modeset, i915.modeset, int, 0400); 53module_param_named(modeset, i915.modeset, int, 0400);
@@ -153,3 +154,6 @@ MODULE_PARM_DESC(invert_brightness,
153 "report PCI device ID, subsystem vendor and subsystem device ID " 154 "report PCI device ID, subsystem vendor and subsystem device ID "
154 "to dri-devel@lists.freedesktop.org, if your machine needs it. " 155 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
155 "It will then be included in an upcoming module version."); 156 "It will then be included in an upcoming module version.");
157
158module_param_named(disable_display, i915.disable_display, bool, 0600);
159MODULE_PARM_DESC(disable_display, "Disable display (default: false)");
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cc3ea049269b..2f564ce37d2c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -789,7 +789,8 @@
789#define _3D_CHICKEN3 0x02090 789#define _3D_CHICKEN3 0x02090
790#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 790#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
791#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 791#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
792#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) 792#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
793#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
793 794
794#define MI_MODE 0x0209c 795#define MI_MODE 0x0209c
795# define VS_TIMER_DISPATCH (1 << 6) 796# define VS_TIMER_DISPATCH (1 << 6)
@@ -1204,8 +1205,8 @@
1204 */ 1205 */
1205#define DPLL_A_OFFSET 0x6014 1206#define DPLL_A_OFFSET 0x6014
1206#define DPLL_B_OFFSET 0x6018 1207#define DPLL_B_OFFSET 0x6018
1207#define DPLL(pipe) (dev_priv->info->dpll_offsets[pipe] + \ 1208#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
1208 dev_priv->info->display_mmio_offset) 1209 dev_priv->info.display_mmio_offset)
1209 1210
1210#define VGA0 0x6000 1211#define VGA0 0x6000
1211#define VGA1 0x6004 1212#define VGA1 0x6004
@@ -1282,8 +1283,8 @@
1282 1283
1283#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */ 1284#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1284#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */ 1285#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
1285#define DPLL_MD(pipe) (dev_priv->info->dpll_md_offsets[pipe] + \ 1286#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
1286 dev_priv->info->display_mmio_offset) 1287 dev_priv->info.display_mmio_offset)
1287 1288
1288/* 1289/*
1289 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 1290 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
@@ -1352,7 +1353,7 @@
1352#define DSTATE_PLL_D3_OFF (1<<3) 1353#define DSTATE_PLL_D3_OFF (1<<3)
1353#define DSTATE_GFX_CLOCK_GATING (1<<1) 1354#define DSTATE_GFX_CLOCK_GATING (1<<1)
1354#define DSTATE_DOT_CLOCK_GATING (1<<0) 1355#define DSTATE_DOT_CLOCK_GATING (1<<0)
1355#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) 1356#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
1356# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ 1357# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1357# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ 1358# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1358# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ 1359# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
@@ -1478,8 +1479,8 @@
1478 */ 1479 */
1479#define PALETTE_A_OFFSET 0xa000 1480#define PALETTE_A_OFFSET 0xa000
1480#define PALETTE_B_OFFSET 0xa800 1481#define PALETTE_B_OFFSET 0xa800
1481#define PALETTE(pipe) (dev_priv->info->palette_offsets[pipe] + \ 1482#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1482 dev_priv->info->display_mmio_offset) 1483 dev_priv->info.display_mmio_offset)
1483 1484
1484/* MCH MMIO space */ 1485/* MCH MMIO space */
1485 1486
@@ -1969,9 +1970,9 @@
1969#define TRANSCODER_C_OFFSET 0x62000 1970#define TRANSCODER_C_OFFSET 0x62000
1970#define TRANSCODER_EDP_OFFSET 0x6f000 1971#define TRANSCODER_EDP_OFFSET 0x6f000
1971 1972
1972#define _TRANSCODER2(pipe, reg) (dev_priv->info->trans_offsets[(pipe)] - \ 1973#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
1973 dev_priv->info->trans_offsets[TRANSCODER_A] + (reg) + \ 1974 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
1974 dev_priv->info->display_mmio_offset) 1975 dev_priv->info.display_mmio_offset)
1975 1976
1976#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A) 1977#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
1977#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A) 1978#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
@@ -2098,7 +2099,7 @@
2098 2099
2099 2100
2100/* Hotplug control (945+ only) */ 2101/* Hotplug control (945+ only) */
2101#define PORT_HOTPLUG_EN (dev_priv->info->display_mmio_offset + 0x61110) 2102#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2102#define PORTB_HOTPLUG_INT_EN (1 << 29) 2103#define PORTB_HOTPLUG_INT_EN (1 << 29)
2103#define PORTC_HOTPLUG_INT_EN (1 << 28) 2104#define PORTC_HOTPLUG_INT_EN (1 << 28)
2104#define PORTD_HOTPLUG_INT_EN (1 << 27) 2105#define PORTD_HOTPLUG_INT_EN (1 << 27)
@@ -2128,7 +2129,7 @@
2128#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) 2129#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2129#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) 2130#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2130 2131
2131#define PORT_HOTPLUG_STAT (dev_priv->info->display_mmio_offset + 0x61114) 2132#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2132/* 2133/*
2133 * HDMI/DP bits are gen4+ 2134 * HDMI/DP bits are gen4+
2134 * 2135 *
@@ -2346,9 +2347,7 @@
2346#define VIDEO_DIP_CTL 0x61170 2347#define VIDEO_DIP_CTL 0x61170
2347/* Pre HSW: */ 2348/* Pre HSW: */
2348#define VIDEO_DIP_ENABLE (1 << 31) 2349#define VIDEO_DIP_ENABLE (1 << 31)
2349#define VIDEO_DIP_PORT_B (1 << 29) 2350#define VIDEO_DIP_PORT(port) ((port) << 29)
2350#define VIDEO_DIP_PORT_C (2 << 29)
2351#define VIDEO_DIP_PORT_D (3 << 29)
2352#define VIDEO_DIP_PORT_MASK (3 << 29) 2351#define VIDEO_DIP_PORT_MASK (3 << 29)
2353#define VIDEO_DIP_ENABLE_GCP (1 << 25) 2352#define VIDEO_DIP_ENABLE_GCP (1 << 25)
2354#define VIDEO_DIP_ENABLE_AVI (1 << 21) 2353#define VIDEO_DIP_ENABLE_AVI (1 << 21)
@@ -2405,7 +2404,7 @@
2405#define PP_DIVISOR 0x61210 2404#define PP_DIVISOR 0x61210
2406 2405
2407/* Panel fitting */ 2406/* Panel fitting */
2408#define PFIT_CONTROL (dev_priv->info->display_mmio_offset + 0x61230) 2407#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
2409#define PFIT_ENABLE (1 << 31) 2408#define PFIT_ENABLE (1 << 31)
2410#define PFIT_PIPE_MASK (3 << 29) 2409#define PFIT_PIPE_MASK (3 << 29)
2411#define PFIT_PIPE_SHIFT 29 2410#define PFIT_PIPE_SHIFT 29
@@ -2423,7 +2422,7 @@
2423#define PFIT_SCALING_PROGRAMMED (1 << 26) 2422#define PFIT_SCALING_PROGRAMMED (1 << 26)
2424#define PFIT_SCALING_PILLAR (2 << 26) 2423#define PFIT_SCALING_PILLAR (2 << 26)
2425#define PFIT_SCALING_LETTER (3 << 26) 2424#define PFIT_SCALING_LETTER (3 << 26)
2426#define PFIT_PGM_RATIOS (dev_priv->info->display_mmio_offset + 0x61234) 2425#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
2427/* Pre-965 */ 2426/* Pre-965 */
2428#define PFIT_VERT_SCALE_SHIFT 20 2427#define PFIT_VERT_SCALE_SHIFT 20
2429#define PFIT_VERT_SCALE_MASK 0xfff00000 2428#define PFIT_VERT_SCALE_MASK 0xfff00000
@@ -2435,25 +2434,25 @@
2435#define PFIT_HORIZ_SCALE_SHIFT_965 0 2434#define PFIT_HORIZ_SCALE_SHIFT_965 0
2436#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff 2435#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2437 2436
2438#define PFIT_AUTO_RATIOS (dev_priv->info->display_mmio_offset + 0x61238) 2437#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
2439 2438
2440#define _VLV_BLC_PWM_CTL2_A (dev_priv->info->display_mmio_offset + 0x61250) 2439#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2441#define _VLV_BLC_PWM_CTL2_B (dev_priv->info->display_mmio_offset + 0x61350) 2440#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
2442#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \ 2441#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2443 _VLV_BLC_PWM_CTL2_B) 2442 _VLV_BLC_PWM_CTL2_B)
2444 2443
2445#define _VLV_BLC_PWM_CTL_A (dev_priv->info->display_mmio_offset + 0x61254) 2444#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2446#define _VLV_BLC_PWM_CTL_B (dev_priv->info->display_mmio_offset + 0x61354) 2445#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
2447#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \ 2446#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2448 _VLV_BLC_PWM_CTL_B) 2447 _VLV_BLC_PWM_CTL_B)
2449 2448
2450#define _VLV_BLC_HIST_CTL_A (dev_priv->info->display_mmio_offset + 0x61260) 2449#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2451#define _VLV_BLC_HIST_CTL_B (dev_priv->info->display_mmio_offset + 0x61360) 2450#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
2452#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \ 2451#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2453 _VLV_BLC_HIST_CTL_B) 2452 _VLV_BLC_HIST_CTL_B)
2454 2453
2455/* Backlight control */ 2454/* Backlight control */
2456#define BLC_PWM_CTL2 (dev_priv->info->display_mmio_offset + 0x61250) /* 965+ only */ 2455#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
2457#define BLM_PWM_ENABLE (1 << 31) 2456#define BLM_PWM_ENABLE (1 << 31)
2458#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */ 2457#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2459#define BLM_PIPE_SELECT (1 << 29) 2458#define BLM_PIPE_SELECT (1 << 29)
@@ -2476,7 +2475,7 @@
2476#define BLM_PHASE_IN_COUNT_MASK (0xff << 8) 2475#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2477#define BLM_PHASE_IN_INCR_SHIFT (0) 2476#define BLM_PHASE_IN_INCR_SHIFT (0)
2478#define BLM_PHASE_IN_INCR_MASK (0xff << 0) 2477#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
2479#define BLC_PWM_CTL (dev_priv->info->display_mmio_offset + 0x61254) 2478#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
2480/* 2479/*
2481 * This is the most significant 15 bits of the number of backlight cycles in a 2480 * This is the most significant 15 bits of the number of backlight cycles in a
2482 * complete cycle of the modulated backlight control. 2481 * complete cycle of the modulated backlight control.
@@ -2498,7 +2497,7 @@
2498#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe) 2497#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2499#define BLM_POLARITY_PNV (1 << 0) /* pnv only */ 2498#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
2500 2499
2501#define BLC_HIST_CTL (dev_priv->info->display_mmio_offset + 0x61260) 2500#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
2502 2501
2503/* New registers for PCH-split platforms. Safe where new bits show up, the 2502/* New registers for PCH-split platforms. Safe where new bits show up, the
2504 * register layout machtes with gen4 BLC_PWM_CTL[12]. */ 2503 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
@@ -3253,6 +3252,7 @@
3253#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 3252#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3254#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 3253#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3255#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 3254#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3255#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
3256#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */ 3256#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3257#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 3257#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3258#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 3258#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
@@ -3269,13 +3269,18 @@
3269#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 3269#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3270#define PIPE_DPST_EVENT_STATUS (1UL<<7) 3270#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3271#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6) 3271#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3272#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3272#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 3273#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3273#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 3274#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3275#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
3274#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */ 3276#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3275#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 3277#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3276#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 3278#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3277#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 3279#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3278 3280
3281#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3282#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3283
3279#define PIPE_A_OFFSET 0x70000 3284#define PIPE_A_OFFSET 0x70000
3280#define PIPE_B_OFFSET 0x71000 3285#define PIPE_B_OFFSET 0x71000
3281#define PIPE_C_OFFSET 0x72000 3286#define PIPE_C_OFFSET 0x72000
@@ -3287,9 +3292,9 @@
3287 */ 3292 */
3288#define PIPE_EDP_OFFSET 0x7f000 3293#define PIPE_EDP_OFFSET 0x7f000
3289 3294
3290#define _PIPE2(pipe, reg) (dev_priv->info->pipe_offsets[pipe] - \ 3295#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3291 dev_priv->info->pipe_offsets[PIPE_A] + (reg) + \ 3296 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3292 dev_priv->info->display_mmio_offset) 3297 dev_priv->info.display_mmio_offset)
3293 3298
3294#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF) 3299#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3295#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL) 3300#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
@@ -3351,7 +3356,7 @@
3351#define DSPARB_BEND_SHIFT 9 /* on 855 */ 3356#define DSPARB_BEND_SHIFT 9 /* on 855 */
3352#define DSPARB_AEND_SHIFT 0 3357#define DSPARB_AEND_SHIFT 0
3353 3358
3354#define DSPFW1 (dev_priv->info->display_mmio_offset + 0x70034) 3359#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
3355#define DSPFW_SR_SHIFT 23 3360#define DSPFW_SR_SHIFT 23
3356#define DSPFW_SR_MASK (0x1ff<<23) 3361#define DSPFW_SR_MASK (0x1ff<<23)
3357#define DSPFW_CURSORB_SHIFT 16 3362#define DSPFW_CURSORB_SHIFT 16
@@ -3359,11 +3364,11 @@
3359#define DSPFW_PLANEB_SHIFT 8 3364#define DSPFW_PLANEB_SHIFT 8
3360#define DSPFW_PLANEB_MASK (0x7f<<8) 3365#define DSPFW_PLANEB_MASK (0x7f<<8)
3361#define DSPFW_PLANEA_MASK (0x7f) 3366#define DSPFW_PLANEA_MASK (0x7f)
3362#define DSPFW2 (dev_priv->info->display_mmio_offset + 0x70038) 3367#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
3363#define DSPFW_CURSORA_MASK 0x00003f00 3368#define DSPFW_CURSORA_MASK 0x00003f00
3364#define DSPFW_CURSORA_SHIFT 8 3369#define DSPFW_CURSORA_SHIFT 8
3365#define DSPFW_PLANEC_MASK (0x7f) 3370#define DSPFW_PLANEC_MASK (0x7f)
3366#define DSPFW3 (dev_priv->info->display_mmio_offset + 0x7003c) 3371#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
3367#define DSPFW_HPLL_SR_EN (1<<31) 3372#define DSPFW_HPLL_SR_EN (1<<31)
3368#define DSPFW_CURSOR_SR_SHIFT 24 3373#define DSPFW_CURSOR_SR_SHIFT 24
3369#define PINEVIEW_SELF_REFRESH_EN (1<<30) 3374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
@@ -3371,8 +3376,8 @@
3371#define DSPFW_HPLL_CURSOR_SHIFT 16 3376#define DSPFW_HPLL_CURSOR_SHIFT 16
3372#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16) 3377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3373#define DSPFW_HPLL_SR_MASK (0x1ff) 3378#define DSPFW_HPLL_SR_MASK (0x1ff)
3374#define DSPFW4 (dev_priv->info->display_mmio_offset + 0x70070) 3379#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
3375#define DSPFW7 (dev_priv->info->display_mmio_offset + 0x7007c) 3380#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
3376 3381
3377/* drain latency register values*/ 3382/* drain latency register values*/
3378#define DRAIN_LATENCY_PRECISION_32 32 3383#define DRAIN_LATENCY_PRECISION_32 32
@@ -3496,12 +3501,12 @@
3496#define PIPE_PIXEL_MASK 0x00ffffff 3501#define PIPE_PIXEL_MASK 0x00ffffff
3497#define PIPE_PIXEL_SHIFT 0 3502#define PIPE_PIXEL_SHIFT 0
3498/* GM45+ just has to be different */ 3503/* GM45+ just has to be different */
3499#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70040) 3504#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
3500#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x70044) 3505#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
3501#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45) 3506#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3502 3507
3503/* Cursor A & B regs */ 3508/* Cursor A & B regs */
3504#define _CURACNTR (dev_priv->info->display_mmio_offset + 0x70080) 3509#define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
3505/* Old style CUR*CNTR flags (desktop 8xx) */ 3510/* Old style CUR*CNTR flags (desktop 8xx) */
3506#define CURSOR_ENABLE 0x80000000 3511#define CURSOR_ENABLE 0x80000000
3507#define CURSOR_GAMMA_ENABLE 0x40000000 3512#define CURSOR_GAMMA_ENABLE 0x40000000
@@ -3524,16 +3529,16 @@
3524#define MCURSOR_PIPE_B (1 << 28) 3529#define MCURSOR_PIPE_B (1 << 28)
3525#define MCURSOR_GAMMA_ENABLE (1 << 26) 3530#define MCURSOR_GAMMA_ENABLE (1 << 26)
3526#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14) 3531#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
3527#define _CURABASE (dev_priv->info->display_mmio_offset + 0x70084) 3532#define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
3528#define _CURAPOS (dev_priv->info->display_mmio_offset + 0x70088) 3533#define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
3529#define CURSOR_POS_MASK 0x007FF 3534#define CURSOR_POS_MASK 0x007FF
3530#define CURSOR_POS_SIGN 0x8000 3535#define CURSOR_POS_SIGN 0x8000
3531#define CURSOR_X_SHIFT 0 3536#define CURSOR_X_SHIFT 0
3532#define CURSOR_Y_SHIFT 16 3537#define CURSOR_Y_SHIFT 16
3533#define CURSIZE 0x700a0 3538#define CURSIZE 0x700a0
3534#define _CURBCNTR (dev_priv->info->display_mmio_offset + 0x700c0) 3539#define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
3535#define _CURBBASE (dev_priv->info->display_mmio_offset + 0x700c4) 3540#define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
3536#define _CURBPOS (dev_priv->info->display_mmio_offset + 0x700c8) 3541#define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
3537 3542
3538#define _CURBCNTR_IVB 0x71080 3543#define _CURBCNTR_IVB 0x71080
3539#define _CURBBASE_IVB 0x71084 3544#define _CURBBASE_IVB 0x71084
@@ -3608,44 +3613,44 @@
3608#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK) 3613#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3609 3614
3610/* VBIOS flags */ 3615/* VBIOS flags */
3611#define SWF00 (dev_priv->info->display_mmio_offset + 0x71410) 3616#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
3612#define SWF01 (dev_priv->info->display_mmio_offset + 0x71414) 3617#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
3613#define SWF02 (dev_priv->info->display_mmio_offset + 0x71418) 3618#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
3614#define SWF03 (dev_priv->info->display_mmio_offset + 0x7141c) 3619#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
3615#define SWF04 (dev_priv->info->display_mmio_offset + 0x71420) 3620#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
3616#define SWF05 (dev_priv->info->display_mmio_offset + 0x71424) 3621#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
3617#define SWF06 (dev_priv->info->display_mmio_offset + 0x71428) 3622#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
3618#define SWF10 (dev_priv->info->display_mmio_offset + 0x70410) 3623#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
3619#define SWF11 (dev_priv->info->display_mmio_offset + 0x70414) 3624#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
3620#define SWF14 (dev_priv->info->display_mmio_offset + 0x71420) 3625#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
3621#define SWF30 (dev_priv->info->display_mmio_offset + 0x72414) 3626#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
3622#define SWF31 (dev_priv->info->display_mmio_offset + 0x72418) 3627#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
3623#define SWF32 (dev_priv->info->display_mmio_offset + 0x7241c) 3628#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
3624 3629
3625/* Pipe B */ 3630/* Pipe B */
3626#define _PIPEBDSL (dev_priv->info->display_mmio_offset + 0x71000) 3631#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
3627#define _PIPEBCONF (dev_priv->info->display_mmio_offset + 0x71008) 3632#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
3628#define _PIPEBSTAT (dev_priv->info->display_mmio_offset + 0x71024) 3633#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
3629#define _PIPEBFRAMEHIGH 0x71040 3634#define _PIPEBFRAMEHIGH 0x71040
3630#define _PIPEBFRAMEPIXEL 0x71044 3635#define _PIPEBFRAMEPIXEL 0x71044
3631#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71040) 3636#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
3632#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info->display_mmio_offset + 0x71044) 3637#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
3633 3638
3634 3639
3635/* Display B control */ 3640/* Display B control */
3636#define _DSPBCNTR (dev_priv->info->display_mmio_offset + 0x71180) 3641#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
3637#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 3642#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3638#define DISPPLANE_ALPHA_TRANS_DISABLE 0 3643#define DISPPLANE_ALPHA_TRANS_DISABLE 0
3639#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0 3644#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3640#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 3645#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3641#define _DSPBADDR (dev_priv->info->display_mmio_offset + 0x71184) 3646#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
3642#define _DSPBSTRIDE (dev_priv->info->display_mmio_offset + 0x71188) 3647#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
3643#define _DSPBPOS (dev_priv->info->display_mmio_offset + 0x7118C) 3648#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
3644#define _DSPBSIZE (dev_priv->info->display_mmio_offset + 0x71190) 3649#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
3645#define _DSPBSURF (dev_priv->info->display_mmio_offset + 0x7119C) 3650#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
3646#define _DSPBTILEOFF (dev_priv->info->display_mmio_offset + 0x711A4) 3651#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
3647#define _DSPBOFFSET (dev_priv->info->display_mmio_offset + 0x711A4) 3652#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
3648#define _DSPBSURFLIVE (dev_priv->info->display_mmio_offset + 0x711AC) 3653#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
3649 3654
3650/* Sprite A control */ 3655/* Sprite A control */
3651#define _DVSACNTR 0x72180 3656#define _DVSACNTR 0x72180
@@ -4109,13 +4114,14 @@
4109#define ILK_ELPIN_409_SELECT (1 << 25) 4114#define ILK_ELPIN_409_SELECT (1 << 25)
4110#define ILK_DPARB_GATE (1<<22) 4115#define ILK_DPARB_GATE (1<<22)
4111#define ILK_VSDPFD_FULL (1<<21) 4116#define ILK_VSDPFD_FULL (1<<21)
4112#define ILK_DISPLAY_CHICKEN_FUSES 0x42014 4117#define FUSE_STRAP 0x42014
4113#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31) 4118#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4114#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30) 4119#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4115#define ILK_DISPLAY_DEBUG_DISABLE (1<<29) 4120#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4116#define ILK_HDCP_DISABLE (1<<25) 4121#define ILK_HDCP_DISABLE (1 << 25)
4117#define ILK_eDP_A_DISABLE (1<<24) 4122#define ILK_eDP_A_DISABLE (1 << 24)
4118#define ILK_DESKTOP (1<<23) 4123#define HSW_CDCLK_LIMIT (1 << 24)
4124#define ILK_DESKTOP (1 << 23)
4119 4125
4120#define ILK_DSPCLK_GATE_D 0x42020 4126#define ILK_DSPCLK_GATE_D 0x42020
4121#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) 4127#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
@@ -4178,9 +4184,6 @@
4178#define HSW_SCRATCH1 0xb038 4184#define HSW_SCRATCH1 0xb038
4179#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27) 4185#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4180 4186
4181#define HSW_FUSE_STRAP 0x42014
4182#define HSW_CDCLK_LIMIT (1 << 24)
4183
4184/* PCH */ 4187/* PCH */
4185 4188
4186/* south display engine interrupt: IBX */ 4189/* south display engine interrupt: IBX */
@@ -5051,7 +5054,7 @@
5051#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) 5054#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
5052#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 5055#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
5053 5056
5054#define G4X_AUD_VID_DID (dev_priv->info->display_mmio_offset + 0x62020) 5057#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
5055#define INTEL_AUDIO_DEVCL 0x808629FB 5058#define INTEL_AUDIO_DEVCL 0x808629FB
5056#define INTEL_AUDIO_DEVBLC 0x80862801 5059#define INTEL_AUDIO_DEVBLC 0x80862801
5057#define INTEL_AUDIO_DEVCTG 0x80862802 5060#define INTEL_AUDIO_DEVCTG 0x80862802
@@ -5435,6 +5438,8 @@
5435 5438
5436/* SFUSE_STRAP */ 5439/* SFUSE_STRAP */
5437#define SFUSE_STRAP 0xc2014 5440#define SFUSE_STRAP 0xc2014
5441#define SFUSE_STRAP_FUSE_LOCK (1<<13)
5442#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
5438#define SFUSE_STRAP_DDIB_DETECTED (1<<2) 5443#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5439#define SFUSE_STRAP_DDIC_DETECTED (1<<1) 5444#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5440#define SFUSE_STRAP_DDID_DETECTED (1<<0) 5445#define SFUSE_STRAP_DDID_DETECTED (1<<0)
@@ -5904,11 +5909,11 @@
5904#define READ_DATA_VALID(n) (1 << (n)) 5909#define READ_DATA_VALID(n) (1 << (n))
5905 5910
5906/* For UMS only (deprecated): */ 5911/* For UMS only (deprecated): */
5907#define _PALETTE_A (dev_priv->info->display_mmio_offset + 0xa000) 5912#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
5908#define _PALETTE_B (dev_priv->info->display_mmio_offset + 0xa800) 5913#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
5909#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) 5914#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
5910#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) 5915#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
5911#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) 5916#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
5912#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) 5917#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
5913 5918
5914#endif /* _I915_REG_H_ */ 5919#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 6e580c98dede..b95a380958db 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -34,15 +34,15 @@ TRACE_EVENT(i915_gem_object_create,
34); 34);
35 35
36TRACE_EVENT(i915_vma_bind, 36TRACE_EVENT(i915_vma_bind,
37 TP_PROTO(struct i915_vma *vma, bool mappable), 37 TP_PROTO(struct i915_vma *vma, unsigned flags),
38 TP_ARGS(vma, mappable), 38 TP_ARGS(vma, flags),
39 39
40 TP_STRUCT__entry( 40 TP_STRUCT__entry(
41 __field(struct drm_i915_gem_object *, obj) 41 __field(struct drm_i915_gem_object *, obj)
42 __field(struct i915_address_space *, vm) 42 __field(struct i915_address_space *, vm)
43 __field(u32, offset) 43 __field(u32, offset)
44 __field(u32, size) 44 __field(u32, size)
45 __field(bool, mappable) 45 __field(unsigned, flags)
46 ), 46 ),
47 47
48 TP_fast_assign( 48 TP_fast_assign(
@@ -50,12 +50,12 @@ TRACE_EVENT(i915_vma_bind,
50 __entry->vm = vma->vm; 50 __entry->vm = vma->vm;
51 __entry->offset = vma->node.start; 51 __entry->offset = vma->node.start;
52 __entry->size = vma->node.size; 52 __entry->size = vma->node.size;
53 __entry->mappable = mappable; 53 __entry->flags = flags;
54 ), 54 ),
55 55
56 TP_printk("obj=%p, offset=%08x size=%x%s vm=%p", 56 TP_printk("obj=%p, offset=%08x size=%x%s vm=%p",
57 __entry->obj, __entry->offset, __entry->size, 57 __entry->obj, __entry->offset, __entry->size,
58 __entry->mappable ? ", mappable" : "", 58 __entry->flags & PIN_MAPPABLE ? ", mappable" : "",
59 __entry->vm) 59 __entry->vm)
60); 60);
61 61
@@ -196,26 +196,26 @@ DEFINE_EVENT(i915_gem_object, i915_gem_object_destroy,
196); 196);
197 197
198TRACE_EVENT(i915_gem_evict, 198TRACE_EVENT(i915_gem_evict,
199 TP_PROTO(struct drm_device *dev, u32 size, u32 align, bool mappable), 199 TP_PROTO(struct drm_device *dev, u32 size, u32 align, unsigned flags),
200 TP_ARGS(dev, size, align, mappable), 200 TP_ARGS(dev, size, align, flags),
201 201
202 TP_STRUCT__entry( 202 TP_STRUCT__entry(
203 __field(u32, dev) 203 __field(u32, dev)
204 __field(u32, size) 204 __field(u32, size)
205 __field(u32, align) 205 __field(u32, align)
206 __field(bool, mappable) 206 __field(unsigned, flags)
207 ), 207 ),
208 208
209 TP_fast_assign( 209 TP_fast_assign(
210 __entry->dev = dev->primary->index; 210 __entry->dev = dev->primary->index;
211 __entry->size = size; 211 __entry->size = size;
212 __entry->align = align; 212 __entry->align = align;
213 __entry->mappable = mappable; 213 __entry->flags = flags;
214 ), 214 ),
215 215
216 TP_printk("dev=%d, size=%d, align=%d %s", 216 TP_printk("dev=%d, size=%d, align=%d %s",
217 __entry->dev, __entry->size, __entry->align, 217 __entry->dev, __entry->size, __entry->align,
218 __entry->mappable ? ", mappable" : "") 218 __entry->flags & PIN_MAPPABLE ? ", mappable" : "")
219); 219);
220 220
221TRACE_EVENT(i915_gem_evict_everything, 221TRACE_EVENT(i915_gem_evict_everything,
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5b444a4b625c..9864aa1ccbe8 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -833,6 +833,7 @@ void intel_crt_init(struct drm_device *dev)
833 crt->base.get_hw_state = intel_crt_get_hw_state; 833 crt->base.get_hw_state = intel_crt_get_hw_state;
834 } 834 }
835 intel_connector->get_hw_state = intel_connector_get_hw_state; 835 intel_connector->get_hw_state = intel_connector_get_hw_state;
836 intel_connector->unregister = intel_connector_unregister;
836 837
837 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 838 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
838 839
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cd65dd04ba20..2643d3b8b67d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1415,7 +1415,7 @@ int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
1415 1415
1416 if (lcpll & LCPLL_CD_SOURCE_FCLK) { 1416 if (lcpll & LCPLL_CD_SOURCE_FCLK) {
1417 return 800000; 1417 return 800000;
1418 } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) { 1418 } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) {
1419 return 450000; 1419 return 450000;
1420 } else if (freq == LCPLL_CLK_FREQ_450) { 1420 } else if (freq == LCPLL_CLK_FREQ_450) {
1421 return 450000; 1421 return 450000;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0f4cbd0aa59e..f19e6ea36dc4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -51,7 +51,10 @@ static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 51
52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb); 53 int x, int y, struct drm_framebuffer *old_fb);
54 54static int intel_framebuffer_init(struct drm_device *dev,
55 struct intel_framebuffer *ifb,
56 struct drm_mode_fb_cmd2 *mode_cmd,
57 struct drm_i915_gem_object *obj);
55 58
56typedef struct { 59typedef struct {
57 int min, max; 60 int min, max;
@@ -1030,7 +1033,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1030 u32 val; 1033 u32 val;
1031 1034
1032 /* ILK FDI PLL is always enabled */ 1035 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5) 1036 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1034 return; 1037 return;
1035 1038
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1039 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
@@ -1189,7 +1192,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1189 u32 val; 1192 u32 val;
1190 1193
1191 if (IS_VALLEYVIEW(dev)) { 1194 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) { 1195 for (i = 0; i < INTEL_INFO(dev)->num_sprites; i++) {
1193 reg = SPCNTR(pipe, i); 1196 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg); 1197 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE), 1198 WARN((val & SP_ENABLE),
@@ -1443,7 +1446,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc)
1443 assert_pipe_disabled(dev_priv, crtc->pipe); 1446 assert_pipe_disabled(dev_priv, crtc->pipe);
1444 1447
1445 /* No really, not for ILK+ */ 1448 /* No really, not for ILK+ */
1446 BUG_ON(dev_priv->info->gen >= 5); 1449 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1447 1450
1448 /* PLL is protected by panel, make sure we can write it */ 1451 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev) && !IS_I830(dev)) 1452 if (IS_MOBILE(dev) && !IS_I830(dev))
@@ -1549,11 +1552,12 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1549 */ 1552 */
1550static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) 1553static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1551{ 1554{
1552 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 1555 struct drm_device *dev = crtc->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1553 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); 1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1554 1558
1555 /* PCH PLLs only available on ILK, SNB and IVB */ 1559 /* PCH PLLs only available on ILK, SNB and IVB */
1556 BUG_ON(dev_priv->info->gen < 5); 1560 BUG_ON(INTEL_INFO(dev)->gen < 5);
1557 if (WARN_ON(pll == NULL)) 1561 if (WARN_ON(pll == NULL))
1558 return; 1562 return;
1559 1563
@@ -1578,11 +1582,12 @@ static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1578 1582
1579static void intel_disable_shared_dpll(struct intel_crtc *crtc) 1583static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1580{ 1584{
1581 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 1585 struct drm_device *dev = crtc->base.dev;
1586 struct drm_i915_private *dev_priv = dev->dev_private;
1582 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); 1587 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1583 1588
1584 /* PCH only available on ILK+ */ 1589 /* PCH only available on ILK+ */
1585 BUG_ON(dev_priv->info->gen < 5); 1590 BUG_ON(INTEL_INFO(dev)->gen < 5);
1586 if (WARN_ON(pll == NULL)) 1591 if (WARN_ON(pll == NULL))
1587 return; 1592 return;
1588 1593
@@ -1617,7 +1622,7 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1617 uint32_t reg, val, pipeconf_val; 1622 uint32_t reg, val, pipeconf_val;
1618 1623
1619 /* PCH only available on ILK+ */ 1624 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv->info->gen < 5); 1625 BUG_ON(INTEL_INFO(dev)->gen < 5);
1621 1626
1622 /* Make sure PCH DPLL is enabled */ 1627 /* Make sure PCH DPLL is enabled */
1623 assert_shared_dpll_enabled(dev_priv, 1628 assert_shared_dpll_enabled(dev_priv,
@@ -1670,7 +1675,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1670 u32 val, pipeconf_val; 1675 u32 val, pipeconf_val;
1671 1676
1672 /* PCH only available on ILK+ */ 1677 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv->info->gen < 5); 1678 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1674 1679
1675 /* FDI must be feeding us bits for PCH ports */ 1680 /* FDI must be feeding us bits for PCH ports */
1676 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); 1681 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
@@ -1744,21 +1749,16 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1744 1749
1745/** 1750/**
1746 * intel_enable_pipe - enable a pipe, asserting requirements 1751 * intel_enable_pipe - enable a pipe, asserting requirements
1747 * @dev_priv: i915 private structure 1752 * @crtc: crtc responsible for the pipe
1748 * @pipe: pipe to enable
1749 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1750 * 1753 *
1751 * Enable @pipe, making sure that various hardware specific requirements 1754 * Enable @crtc's pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1755 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1753 *
1754 * @pipe should be %PIPE_A or %PIPE_B.
1755 *
1756 * Will wait until the pipe is actually running (i.e. first vblank) before
1757 * returning.
1758 */ 1756 */
1759static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, 1757static void intel_enable_pipe(struct intel_crtc *crtc)
1760 bool pch_port, bool dsi)
1761{ 1758{
1759 struct drm_device *dev = crtc->base.dev;
1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 enum pipe pipe = crtc->pipe;
1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe); 1763 pipe);
1764 enum pipe pch_transcoder; 1764 enum pipe pch_transcoder;
@@ -1780,12 +1780,12 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1780 * need the check. 1780 * need the check.
1781 */ 1781 */
1782 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1782 if (!HAS_PCH_SPLIT(dev_priv->dev))
1783 if (dsi) 1783 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1784 assert_dsi_pll_enabled(dev_priv); 1784 assert_dsi_pll_enabled(dev_priv);
1785 else 1785 else
1786 assert_pll_enabled(dev_priv, pipe); 1786 assert_pll_enabled(dev_priv, pipe);
1787 else { 1787 else {
1788 if (pch_port) { 1788 if (crtc->config.has_pch_encoder) {
1789 /* if driving the PCH, we need FDI enabled */ 1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); 1790 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1791 assert_fdi_tx_pll_enabled(dev_priv, 1791 assert_fdi_tx_pll_enabled(dev_priv,
@@ -1796,11 +1796,24 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1796 1796
1797 reg = PIPECONF(cpu_transcoder); 1797 reg = PIPECONF(cpu_transcoder);
1798 val = I915_READ(reg); 1798 val = I915_READ(reg);
1799 if (val & PIPECONF_ENABLE) 1799 if (val & PIPECONF_ENABLE) {
1800 WARN_ON(!(pipe == PIPE_A &&
1801 dev_priv->quirks & QUIRK_PIPEA_FORCE));
1800 return; 1802 return;
1803 }
1801 1804
1802 I915_WRITE(reg, val | PIPECONF_ENABLE); 1805 I915_WRITE(reg, val | PIPECONF_ENABLE);
1803 intel_wait_for_vblank(dev_priv->dev, pipe); 1806 POSTING_READ(reg);
1807
1808 /*
1809 * There's no guarantee the pipe will really start running now. It
1810 * depends on the Gen, the output type and the relative order between
1811 * pipe and plane enabling. Avoid waiting on HSW+ since it's not
1812 * necessary.
1813 * TODO: audit the previous gens.
1814 */
1815 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
1816 intel_wait_for_vblank(dev_priv->dev, pipe);
1804} 1817}
1805 1818
1806/** 1819/**
@@ -1851,7 +1864,8 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1851void intel_flush_primary_plane(struct drm_i915_private *dev_priv, 1864void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1852 enum plane plane) 1865 enum plane plane)
1853{ 1866{
1854 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); 1867 struct drm_device *dev = dev_priv->dev;
1868 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1855 1869
1856 I915_WRITE(reg, I915_READ(reg)); 1870 I915_WRITE(reg, I915_READ(reg));
1857 POSTING_READ(reg); 1871 POSTING_READ(reg);
@@ -1929,6 +1943,14 @@ static bool need_vtd_wa(struct drm_device *dev)
1929 return false; 1943 return false;
1930} 1944}
1931 1945
1946static int intel_align_height(struct drm_device *dev, int height, bool tiled)
1947{
1948 int tile_height;
1949
1950 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
1951 return ALIGN(height, tile_height);
1952}
1953
1932int 1954int
1933intel_pin_and_fence_fb_obj(struct drm_device *dev, 1955intel_pin_and_fence_fb_obj(struct drm_device *dev,
1934 struct drm_i915_gem_object *obj, 1956 struct drm_i915_gem_object *obj,
@@ -2299,33 +2321,6 @@ intel_finish_fb(struct drm_framebuffer *old_fb)
2299 return ret; 2321 return ret;
2300} 2322}
2301 2323
2302static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2303{
2304 struct drm_device *dev = crtc->dev;
2305 struct drm_i915_master_private *master_priv;
2306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2307
2308 if (!dev->primary->master)
2309 return;
2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
2313 return;
2314
2315 switch (intel_crtc->pipe) {
2316 case 0:
2317 master_priv->sarea_priv->pipeA_x = x;
2318 master_priv->sarea_priv->pipeA_y = y;
2319 break;
2320 case 1:
2321 master_priv->sarea_priv->pipeB_x = x;
2322 master_priv->sarea_priv->pipeB_y = y;
2323 break;
2324 default:
2325 break;
2326 }
2327}
2328
2329static int 2324static int
2330intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 2325intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2331 struct drm_framebuffer *fb) 2326 struct drm_framebuffer *fb)
@@ -2413,8 +2408,6 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2413 intel_edp_psr_update(dev); 2408 intel_edp_psr_update(dev);
2414 mutex_unlock(&dev->struct_mutex); 2409 mutex_unlock(&dev->struct_mutex);
2415 2410
2416 intel_crtc_update_sarea_pos(crtc, x, y);
2417
2418 return 0; 2411 return 0;
2419} 2412}
2420 2413
@@ -3587,8 +3580,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
3587 intel_crtc_load_lut(crtc); 3580 intel_crtc_load_lut(crtc);
3588 3581
3589 intel_update_watermarks(crtc); 3582 intel_update_watermarks(crtc);
3590 intel_enable_pipe(dev_priv, pipe, 3583 intel_enable_pipe(intel_crtc);
3591 intel_crtc->config.has_pch_encoder, false);
3592 intel_enable_primary_plane(dev_priv, plane, pipe); 3584 intel_enable_primary_plane(dev_priv, plane, pipe);
3593 intel_enable_planes(crtc); 3585 intel_enable_planes(crtc);
3594 intel_crtc_update_cursor(crtc, true); 3586 intel_crtc_update_cursor(crtc, true);
@@ -3733,8 +3725,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3733 intel_ddi_enable_transcoder_func(crtc); 3725 intel_ddi_enable_transcoder_func(crtc);
3734 3726
3735 intel_update_watermarks(crtc); 3727 intel_update_watermarks(crtc);
3736 intel_enable_pipe(dev_priv, pipe, 3728 intel_enable_pipe(intel_crtc);
3737 intel_crtc->config.has_pch_encoder, false);
3738 3729
3739 if (intel_crtc->config.has_pch_encoder) 3730 if (intel_crtc->config.has_pch_encoder)
3740 lpt_pch_enable(crtc); 3731 lpt_pch_enable(crtc);
@@ -3748,16 +3739,6 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
3748 * to change the workaround. */ 3739 * to change the workaround. */
3749 haswell_mode_set_planes_workaround(intel_crtc); 3740 haswell_mode_set_planes_workaround(intel_crtc);
3750 haswell_crtc_enable_planes(crtc); 3741 haswell_crtc_enable_planes(crtc);
3751
3752 /*
3753 * There seems to be a race in PCH platform hw (at least on some
3754 * outputs) where an enabled pipe still completes any pageflip right
3755 * away (as if the pipe is off) instead of waiting for vblank. As soon
3756 * as the first vblank happend, everything works as expected. Hence just
3757 * wait for one vblank before returning to avoid strange things
3758 * happening.
3759 */
3760 intel_wait_for_vblank(dev, intel_crtc->pipe);
3761} 3742}
3762 3743
3763static void ironlake_pfit_disable(struct intel_crtc *crtc) 3744static void ironlake_pfit_disable(struct intel_crtc *crtc)
@@ -4169,7 +4150,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
4169 intel_crtc_load_lut(crtc); 4150 intel_crtc_load_lut(crtc);
4170 4151
4171 intel_update_watermarks(crtc); 4152 intel_update_watermarks(crtc);
4172 intel_enable_pipe(dev_priv, pipe, false, is_dsi); 4153 intel_enable_pipe(intel_crtc);
4173 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4154 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4174 intel_enable_primary_plane(dev_priv, plane, pipe); 4155 intel_enable_primary_plane(dev_priv, plane, pipe);
4175 intel_enable_planes(crtc); 4156 intel_enable_planes(crtc);
@@ -4208,7 +4189,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
4208 intel_crtc_load_lut(crtc); 4189 intel_crtc_load_lut(crtc);
4209 4190
4210 intel_update_watermarks(crtc); 4191 intel_update_watermarks(crtc);
4211 intel_enable_pipe(dev_priv, pipe, false, false); 4192 intel_enable_pipe(intel_crtc);
4212 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); 4193 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4213 intel_enable_primary_plane(dev_priv, plane, pipe); 4194 intel_enable_primary_plane(dev_priv, plane, pipe);
4214 intel_enable_planes(crtc); 4195 intel_enable_planes(crtc);
@@ -5256,25 +5237,23 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc,
5256 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; 5237 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5257} 5238}
5258 5239
5259static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, 5240void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5260 struct intel_crtc_config *pipe_config) 5241 struct intel_crtc_config *pipe_config)
5261{ 5242{
5262 struct drm_crtc *crtc = &intel_crtc->base; 5243 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5244 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5245 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5246 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5263 5247
5264 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; 5248 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5265 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; 5249 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5266 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; 5250 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5267 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; 5251 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5268 5252
5269 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; 5253 mode->flags = pipe_config->adjusted_mode.flags;
5270 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5271 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5272 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5273 5254
5274 crtc->mode.flags = pipe_config->adjusted_mode.flags; 5255 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5275 5256 mode->flags |= pipe_config->adjusted_mode.flags;
5276 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5277 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5278} 5257}
5279 5258
5280static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) 5259static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
@@ -7577,7 +7556,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7577 7556
7578 /* we only need to pin inside GTT if cursor is non-phy */ 7557 /* we only need to pin inside GTT if cursor is non-phy */
7579 mutex_lock(&dev->struct_mutex); 7558 mutex_lock(&dev->struct_mutex);
7580 if (!dev_priv->info->cursor_needs_physical) { 7559 if (!INTEL_INFO(dev)->cursor_needs_physical) {
7581 unsigned alignment; 7560 unsigned alignment;
7582 7561
7583 if (obj->tiling_mode) { 7562 if (obj->tiling_mode) {
@@ -7625,7 +7604,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7625 7604
7626 finish: 7605 finish:
7627 if (intel_crtc->cursor_bo) { 7606 if (intel_crtc->cursor_bo) {
7628 if (dev_priv->info->cursor_needs_physical) { 7607 if (INTEL_INFO(dev)->cursor_needs_physical) {
7629 if (intel_crtc->cursor_bo != obj) 7608 if (intel_crtc->cursor_bo != obj)
7630 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 7609 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7631 } else 7610 } else
@@ -7687,10 +7666,10 @@ static struct drm_display_mode load_detect_mode = {
7687 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 7666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7688}; 7667};
7689 7668
7690static struct drm_framebuffer * 7669struct drm_framebuffer *
7691intel_framebuffer_create(struct drm_device *dev, 7670__intel_framebuffer_create(struct drm_device *dev,
7692 struct drm_mode_fb_cmd2 *mode_cmd, 7671 struct drm_mode_fb_cmd2 *mode_cmd,
7693 struct drm_i915_gem_object *obj) 7672 struct drm_i915_gem_object *obj)
7694{ 7673{
7695 struct intel_framebuffer *intel_fb; 7674 struct intel_framebuffer *intel_fb;
7696 int ret; 7675 int ret;
@@ -7701,12 +7680,7 @@ intel_framebuffer_create(struct drm_device *dev,
7701 return ERR_PTR(-ENOMEM); 7680 return ERR_PTR(-ENOMEM);
7702 } 7681 }
7703 7682
7704 ret = i915_mutex_lock_interruptible(dev);
7705 if (ret)
7706 goto err;
7707
7708 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 7683 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7709 mutex_unlock(&dev->struct_mutex);
7710 if (ret) 7684 if (ret)
7711 goto err; 7685 goto err;
7712 7686
@@ -7718,6 +7692,23 @@ err:
7718 return ERR_PTR(ret); 7692 return ERR_PTR(ret);
7719} 7693}
7720 7694
7695struct drm_framebuffer *
7696intel_framebuffer_create(struct drm_device *dev,
7697 struct drm_mode_fb_cmd2 *mode_cmd,
7698 struct drm_i915_gem_object *obj)
7699{
7700 struct drm_framebuffer *fb;
7701 int ret;
7702
7703 ret = i915_mutex_lock_interruptible(dev);
7704 if (ret)
7705 return ERR_PTR(ret);
7706 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
7707 mutex_unlock(&dev->struct_mutex);
7708
7709 return fb;
7710}
7711
7721static u32 7712static u32
7722intel_framebuffer_pitch_for_width(int width, int bpp) 7713intel_framebuffer_pitch_for_width(int width, int bpp)
7723{ 7714{
@@ -7763,14 +7754,16 @@ mode_fits_in_fbdev(struct drm_device *dev,
7763 struct drm_i915_gem_object *obj; 7754 struct drm_i915_gem_object *obj;
7764 struct drm_framebuffer *fb; 7755 struct drm_framebuffer *fb;
7765 7756
7766 if (dev_priv->fbdev == NULL) 7757 if (!dev_priv->fbdev)
7767 return NULL; 7758 return NULL;
7768 7759
7769 obj = dev_priv->fbdev->ifb.obj; 7760 if (!dev_priv->fbdev->fb)
7770 if (obj == NULL)
7771 return NULL; 7761 return NULL;
7772 7762
7773 fb = &dev_priv->fbdev->ifb.base; 7763 obj = dev_priv->fbdev->fb->obj;
7764 BUG_ON(!obj);
7765
7766 fb = &dev_priv->fbdev->fb->base;
7774 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 7767 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7775 fb->bits_per_pixel)) 7768 fb->bits_per_pixel))
7776 return NULL; 7769 return NULL;
@@ -8220,7 +8213,7 @@ void intel_mark_idle(struct drm_device *dev)
8220 intel_decrease_pllclock(crtc); 8213 intel_decrease_pllclock(crtc);
8221 } 8214 }
8222 8215
8223 if (dev_priv->info->gen >= 6) 8216 if (INTEL_INFO(dev)->gen >= 6)
8224 gen6_rps_idle(dev->dev_private); 8217 gen6_rps_idle(dev->dev_private);
8225} 8218}
8226 8219
@@ -10384,8 +10377,7 @@ static bool has_edp_a(struct drm_device *dev)
10384 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 10377 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10385 return false; 10378 return false;
10386 10379
10387 if (IS_GEN5(dev) && 10380 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
10388 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10389 return false; 10381 return false;
10390 10382
10391 return true; 10383 return true;
@@ -10538,18 +10530,13 @@ static void intel_setup_outputs(struct drm_device *dev)
10538 drm_helper_move_panel_connectors_to_head(dev); 10530 drm_helper_move_panel_connectors_to_head(dev);
10539} 10531}
10540 10532
10541void intel_framebuffer_fini(struct intel_framebuffer *fb)
10542{
10543 drm_framebuffer_cleanup(&fb->base);
10544 WARN_ON(!fb->obj->framebuffer_references--);
10545 drm_gem_object_unreference_unlocked(&fb->obj->base);
10546}
10547
10548static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 10533static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10549{ 10534{
10550 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 10535 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10551 10536
10552 intel_framebuffer_fini(intel_fb); 10537 drm_framebuffer_cleanup(fb);
10538 WARN_ON(!intel_fb->obj->framebuffer_references--);
10539 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
10553 kfree(intel_fb); 10540 kfree(intel_fb);
10554} 10541}
10555 10542
@@ -10573,7 +10560,7 @@ int intel_framebuffer_init(struct drm_device *dev,
10573 struct drm_mode_fb_cmd2 *mode_cmd, 10560 struct drm_mode_fb_cmd2 *mode_cmd,
10574 struct drm_i915_gem_object *obj) 10561 struct drm_i915_gem_object *obj)
10575{ 10562{
10576 int aligned_height, tile_height; 10563 int aligned_height;
10577 int pitch_limit; 10564 int pitch_limit;
10578 int ret; 10565 int ret;
10579 10566
@@ -10667,9 +10654,8 @@ int intel_framebuffer_init(struct drm_device *dev,
10667 if (mode_cmd->offsets[0] != 0) 10654 if (mode_cmd->offsets[0] != 0)
10668 return -EINVAL; 10655 return -EINVAL;
10669 10656
10670 tile_height = IS_GEN2(dev) ? 16 : 8; 10657 aligned_height = intel_align_height(dev, mode_cmd->height,
10671 aligned_height = ALIGN(mode_cmd->height, 10658 obj->tiling_mode);
10672 obj->tiling_mode ? tile_height : 1);
10673 /* FIXME drm helper for size checks (especially planar formats)? */ 10659 /* FIXME drm helper for size checks (especially planar formats)? */
10674 if (obj->base.size < aligned_height * mode_cmd->pitches[0]) 10660 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10675 return -EINVAL; 10661 return -EINVAL;
@@ -11049,7 +11035,7 @@ void intel_modeset_init(struct drm_device *dev)
11049 11035
11050 for_each_pipe(i) { 11036 for_each_pipe(i) {
11051 intel_crtc_init(dev, i); 11037 intel_crtc_init(dev, i);
11052 for (j = 0; j < dev_priv->num_plane; j++) { 11038 for (j = 0; j < INTEL_INFO(dev)->num_sprites; j++) {
11053 ret = intel_plane_init(dev, i, j); 11039 ret = intel_plane_init(dev, i, j);
11054 if (ret) 11040 if (ret)
11055 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", 11041 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
@@ -11069,6 +11055,8 @@ void intel_modeset_init(struct drm_device *dev)
11069 11055
11070 /* Just in case the BIOS is doing something questionable. */ 11056 /* Just in case the BIOS is doing something questionable. */
11071 intel_disable_fbc(dev); 11057 intel_disable_fbc(dev);
11058
11059 intel_modeset_setup_hw_state(dev, false);
11072} 11060}
11073 11061
11074static void 11062static void
@@ -11375,8 +11363,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev,
11375 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 11363 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11376 base.head) { 11364 base.head) {
11377 if (crtc->active && i915.fastboot) { 11365 if (crtc->active && i915.fastboot) {
11378 intel_crtc_mode_from_pipe_config(crtc, &crtc->config); 11366 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
11379
11380 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", 11367 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11381 crtc->base.base.id); 11368 crtc->base.base.id);
11382 drm_mode_debug_printmodeline(&crtc->base.mode); 11369 drm_mode_debug_printmodeline(&crtc->base.mode);
@@ -11436,10 +11423,14 @@ void intel_modeset_gem_init(struct drm_device *dev)
11436 intel_modeset_init_hw(dev); 11423 intel_modeset_init_hw(dev);
11437 11424
11438 intel_setup_overlay(dev); 11425 intel_setup_overlay(dev);
11426}
11439 11427
11440 mutex_lock(&dev->mode_config.mutex); 11428void intel_connector_unregister(struct intel_connector *intel_connector)
11441 intel_modeset_setup_hw_state(dev, false); 11429{
11442 mutex_unlock(&dev->mode_config.mutex); 11430 struct drm_connector *connector = &intel_connector->base;
11431
11432 intel_panel_destroy_backlight(connector);
11433 drm_sysfs_connector_remove(connector);
11443} 11434}
11444 11435
11445void intel_modeset_cleanup(struct drm_device *dev) 11436void intel_modeset_cleanup(struct drm_device *dev)
@@ -11486,8 +11477,10 @@ void intel_modeset_cleanup(struct drm_device *dev)
11486 11477
11487 /* destroy the backlight and sysfs files before encoders/connectors */ 11478 /* destroy the backlight and sysfs files before encoders/connectors */
11488 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 11479 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11489 intel_panel_destroy_backlight(connector); 11480 struct intel_connector *intel_connector;
11490 drm_sysfs_connector_remove(connector); 11481
11482 intel_connector = to_intel_connector(connector);
11483 intel_connector->unregister(intel_connector);
11491 } 11484 }
11492 11485
11493 drm_mode_config_cleanup(dev); 11486 drm_mode_config_cleanup(dev);
@@ -11520,12 +11513,24 @@ int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11520 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; 11513 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
11521 u16 gmch_ctrl; 11514 u16 gmch_ctrl;
11522 11515
11523 pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl); 11516 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
11517 DRM_ERROR("failed to read control word\n");
11518 return -EIO;
11519 }
11520
11521 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
11522 return 0;
11523
11524 if (state) 11524 if (state)
11525 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 11525 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11526 else 11526 else
11527 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 11527 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11528 pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl); 11528
11529 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
11530 DRM_ERROR("failed to write control word\n");
11531 return -EIO;
11532 }
11533
11529 return 0; 11534 return 0;
11530} 11535}
11531 11536
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index bd1df502bc34..c512d78af271 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -784,6 +784,16 @@ out:
784 return ret; 784 return ret;
785} 785}
786 786
787static void
788intel_dp_connector_unregister(struct intel_connector *intel_connector)
789{
790 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
791
792 sysfs_remove_link(&intel_connector->base.kdev->kobj,
793 intel_dp->adapter.dev.kobj.name);
794 intel_connector_unregister(intel_connector);
795}
796
787static int 797static int
788intel_dp_i2c_init(struct intel_dp *intel_dp, 798intel_dp_i2c_init(struct intel_dp *intel_dp,
789 struct intel_connector *intel_connector, const char *name) 799 struct intel_connector *intel_connector, const char *name)
@@ -801,9 +811,19 @@ intel_dp_i2c_init(struct intel_dp *intel_dp,
801 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); 811 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
802 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; 812 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
803 intel_dp->adapter.algo_data = &intel_dp->algo; 813 intel_dp->adapter.algo_data = &intel_dp->algo;
804 intel_dp->adapter.dev.parent = intel_connector->base.kdev; 814 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
805 815
806 ret = i2c_dp_aux_add_bus(&intel_dp->adapter); 816 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
817 if (ret < 0)
818 return ret;
819
820 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
821 &intel_dp->adapter.dev.kobj,
822 intel_dp->adapter.dev.kobj.name);
823
824 if (ret < 0)
825 i2c_del_adapter(&intel_dp->adapter);
826
807 return ret; 827 return ret;
808} 828}
809 829
@@ -3739,7 +3759,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3739 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 3759 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3740 } 3760 }
3741 3761
3742 intel_panel_init(&intel_connector->panel, fixed_mode); 3762 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3743 intel_panel_setup_backlight(connector); 3763 intel_panel_setup_backlight(connector);
3744 3764
3745 return true; 3765 return true;
@@ -3808,6 +3828,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3808 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3828 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3809 else 3829 else
3810 intel_connector->get_hw_state = intel_connector_get_hw_state; 3830 intel_connector->get_hw_state = intel_connector_get_hw_state;
3831 intel_connector->unregister = intel_dp_connector_unregister;
3811 3832
3812 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; 3833 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3813 if (HAS_DDI(dev)) { 3834 if (HAS_DDI(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 44067bce5e04..a4ffc021c317 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -110,7 +110,7 @@ struct intel_framebuffer {
110 110
111struct intel_fbdev { 111struct intel_fbdev {
112 struct drm_fb_helper helper; 112 struct drm_fb_helper helper;
113 struct intel_framebuffer ifb; 113 struct intel_framebuffer *fb;
114 struct list_head fbdev_list; 114 struct list_head fbdev_list;
115 struct drm_display_mode *our_mode; 115 struct drm_display_mode *our_mode;
116}; 116};
@@ -187,6 +187,14 @@ struct intel_connector {
187 * and active (i.e. dpms ON state). */ 187 * and active (i.e. dpms ON state). */
188 bool (*get_hw_state)(struct intel_connector *); 188 bool (*get_hw_state)(struct intel_connector *);
189 189
190 /*
191 * Removes all interfaces through which the connector is accessible
192 * - like sysfs, debugfs entries -, so that no new operations can be
193 * started on the connector. Also makes sure all currently pending
194 * operations finish before returing.
195 */
196 void (*unregister)(struct intel_connector *);
197
190 /* Panel info for eDP and LVDS */ 198 /* Panel info for eDP and LVDS */
191 struct intel_panel panel; 199 struct intel_panel panel;
192 200
@@ -681,11 +689,10 @@ int intel_pin_and_fence_fb_obj(struct drm_device *dev,
681 struct drm_i915_gem_object *obj, 689 struct drm_i915_gem_object *obj,
682 struct intel_ring_buffer *pipelined); 690 struct intel_ring_buffer *pipelined);
683void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 691void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
684int intel_framebuffer_init(struct drm_device *dev, 692struct drm_framebuffer *
685 struct intel_framebuffer *ifb, 693__intel_framebuffer_create(struct drm_device *dev,
686 struct drm_mode_fb_cmd2 *mode_cmd, 694 struct drm_mode_fb_cmd2 *mode_cmd,
687 struct drm_i915_gem_object *obj); 695 struct drm_i915_gem_object *obj);
688void intel_framebuffer_fini(struct intel_framebuffer *fb);
689void intel_prepare_page_flip(struct drm_device *dev, int plane); 696void intel_prepare_page_flip(struct drm_device *dev, int plane);
690void intel_finish_page_flip(struct drm_device *dev, int pipe); 697void intel_finish_page_flip(struct drm_device *dev, int pipe);
691void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 698void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
@@ -727,6 +734,8 @@ void hsw_enable_ips(struct intel_crtc *crtc);
727void hsw_disable_ips(struct intel_crtc *crtc); 734void hsw_disable_ips(struct intel_crtc *crtc);
728void intel_display_set_init_power(struct drm_device *dev, bool enable); 735void intel_display_set_init_power(struct drm_device *dev, bool enable);
729int valleyview_get_vco(struct drm_i915_private *dev_priv); 736int valleyview_get_vco(struct drm_i915_private *dev_priv);
737void intel_mode_from_pipe_config(struct drm_display_mode *mode,
738 struct intel_crtc_config *pipe_config);
730 739
731/* intel_dp.c */ 740/* intel_dp.c */
732void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 741void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
@@ -824,7 +833,8 @@ int intel_overlay_attrs(struct drm_device *dev, void *data,
824 833
825/* intel_panel.c */ 834/* intel_panel.c */
826int intel_panel_init(struct intel_panel *panel, 835int intel_panel_init(struct intel_panel *panel,
827 struct drm_display_mode *fixed_mode); 836 struct drm_display_mode *fixed_mode,
837 struct drm_display_mode *downclock_mode);
828void intel_panel_fini(struct intel_panel *panel); 838void intel_panel_fini(struct intel_panel *panel);
829void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, 839void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
830 struct drm_display_mode *adjusted_mode); 840 struct drm_display_mode *adjusted_mode);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index fabbf0d895cf..3ee1db1407b0 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -586,6 +586,7 @@ bool intel_dsi_init(struct drm_device *dev)
586 intel_encoder->get_config = intel_dsi_get_config; 586 intel_encoder->get_config = intel_dsi_get_config;
587 587
588 intel_connector->get_hw_state = intel_connector_get_hw_state; 588 intel_connector->get_hw_state = intel_connector_get_hw_state;
589 intel_connector->unregister = intel_connector_unregister;
589 590
590 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { 591 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
591 dsi = &intel_dsi_devices[i]; 592 dsi = &intel_dsi_devices[i];
@@ -624,7 +625,7 @@ bool intel_dsi_init(struct drm_device *dev)
624 } 625 }
625 626
626 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 627 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
627 intel_panel_init(&intel_connector->panel, fixed_mode); 628 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
628 629
629 return true; 630 return true;
630 631
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index eeff998e52ef..86eeb8b7d435 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -477,6 +477,7 @@ void intel_dvo_init(struct drm_device *dev)
477 intel_encoder->compute_config = intel_dvo_compute_config; 477 intel_encoder->compute_config = intel_dvo_compute_config;
478 intel_encoder->mode_set = intel_dvo_mode_set; 478 intel_encoder->mode_set = intel_dvo_mode_set;
479 intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; 479 intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
480 intel_connector->unregister = intel_connector_unregister;
480 481
481 /* Now, try to find a controller */ 482 /* Now, try to find a controller */
482 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) { 483 for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index d6a8a716018d..19be4bfbcc59 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -62,6 +62,7 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
62{ 62{
63 struct intel_fbdev *ifbdev = 63 struct intel_fbdev *ifbdev =
64 container_of(helper, struct intel_fbdev, helper); 64 container_of(helper, struct intel_fbdev, helper);
65 struct drm_framebuffer *fb;
65 struct drm_device *dev = helper->dev; 66 struct drm_device *dev = helper->dev;
66 struct drm_mode_fb_cmd2 mode_cmd = {}; 67 struct drm_mode_fb_cmd2 mode_cmd = {};
67 struct drm_i915_gem_object *obj; 68 struct drm_i915_gem_object *obj;
@@ -93,13 +94,17 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
93 /* Flush everything out, we'll be doing GTT only from now on */ 94 /* Flush everything out, we'll be doing GTT only from now on */
94 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 95 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
95 if (ret) { 96 if (ret) {
96 DRM_ERROR("failed to pin fb: %d\n", ret); 97 DRM_ERROR("failed to pin obj: %d\n", ret);
97 goto out_unref; 98 goto out_unref;
98 } 99 }
99 100
100 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj); 101 fb = __intel_framebuffer_create(dev, &mode_cmd, obj);
101 if (ret) 102 if (IS_ERR(fb)) {
103 ret = PTR_ERR(fb);
102 goto out_unpin; 104 goto out_unpin;
105 }
106
107 ifbdev->fb = to_intel_framebuffer(fb);
103 108
104 return 0; 109 return 0;
105 110
@@ -116,7 +121,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
116{ 121{
117 struct intel_fbdev *ifbdev = 122 struct intel_fbdev *ifbdev =
118 container_of(helper, struct intel_fbdev, helper); 123 container_of(helper, struct intel_fbdev, helper);
119 struct intel_framebuffer *intel_fb = &ifbdev->ifb; 124 struct intel_framebuffer *intel_fb = ifbdev->fb;
120 struct drm_device *dev = helper->dev; 125 struct drm_device *dev = helper->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private; 126 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct fb_info *info; 127 struct fb_info *info;
@@ -126,11 +131,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
126 131
127 mutex_lock(&dev->struct_mutex); 132 mutex_lock(&dev->struct_mutex);
128 133
129 if (!intel_fb->obj) { 134 if (!intel_fb || WARN_ON(!intel_fb->obj)) {
130 DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n"); 135 DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
131 ret = intelfb_alloc(helper, sizes); 136 ret = intelfb_alloc(helper, sizes);
132 if (ret) 137 if (ret)
133 goto out_unlock; 138 goto out_unlock;
139 intel_fb = ifbdev->fb;
134 } else { 140 } else {
135 DRM_DEBUG_KMS("re-using BIOS fb\n"); 141 DRM_DEBUG_KMS("re-using BIOS fb\n");
136 sizes->fb_width = intel_fb->base.width; 142 sizes->fb_width = intel_fb->base.width;
@@ -148,7 +154,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
148 154
149 info->par = helper; 155 info->par = helper;
150 156
151 fb = &ifbdev->ifb.base; 157 fb = &ifbdev->fb->base;
152 158
153 ifbdev->helper.fb = fb; 159 ifbdev->helper.fb = fb;
154 ifbdev->helper.fbdev = info; 160 ifbdev->helper.fbdev = info;
@@ -194,7 +200,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
194 * If the object is stolen however, it will be full of whatever 200 * If the object is stolen however, it will be full of whatever
195 * garbage was left in there. 201 * garbage was left in there.
196 */ 202 */
197 if (ifbdev->ifb.obj->stolen) 203 if (ifbdev->fb->obj->stolen)
198 memset_io(info->screen_base, 0, info->screen_size); 204 memset_io(info->screen_base, 0, info->screen_size);
199 205
200 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ 206 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
@@ -236,7 +242,152 @@ static void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
236 *blue = intel_crtc->lut_b[regno] << 8; 242 *blue = intel_crtc->lut_b[regno] << 8;
237} 243}
238 244
245static struct drm_fb_helper_crtc *
246intel_fb_helper_crtc(struct drm_fb_helper *fb_helper, struct drm_crtc *crtc)
247{
248 int i;
249
250 for (i = 0; i < fb_helper->crtc_count; i++)
251 if (fb_helper->crtc_info[i].mode_set.crtc == crtc)
252 return &fb_helper->crtc_info[i];
253
254 return NULL;
255}
256
257/*
258 * Try to read the BIOS display configuration and use it for the initial
259 * fb configuration.
260 *
261 * The BIOS or boot loader will generally create an initial display
262 * configuration for us that includes some set of active pipes and displays.
263 * This routine tries to figure out which pipes and connectors are active
264 * and stuffs them into the crtcs and modes array given to us by the
265 * drm_fb_helper code.
266 *
267 * The overall sequence is:
268 * intel_fbdev_init - from driver load
269 * intel_fbdev_init_bios - initialize the intel_fbdev using BIOS data
270 * drm_fb_helper_init - build fb helper structs
271 * drm_fb_helper_single_add_all_connectors - more fb helper structs
272 * intel_fbdev_initial_config - apply the config
273 * drm_fb_helper_initial_config - call ->probe then register_framebuffer()
274 * drm_setup_crtcs - build crtc config for fbdev
275 * intel_fb_initial_config - find active connectors etc
276 * drm_fb_helper_single_fb_probe - set up fbdev
277 * intelfb_create - re-use or alloc fb, build out fbdev structs
278 *
279 * Note that we don't make special consideration whether we could actually
280 * switch to the selected modes without a full modeset. E.g. when the display
281 * is in VGA mode we need to recalculate watermarks and set a new high-res
282 * framebuffer anyway.
283 */
284static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper,
285 struct drm_fb_helper_crtc **crtcs,
286 struct drm_display_mode **modes,
287 bool *enabled, int width, int height)
288{
289 struct drm_device *dev = fb_helper->dev;
290 int i, j;
291 bool *save_enabled;
292 bool any_enabled = false;
293
294 save_enabled = kcalloc(dev->mode_config.num_connector, sizeof(bool),
295 GFP_KERNEL);
296 if (!save_enabled)
297 return false;
298
299 memcpy(save_enabled, enabled, dev->mode_config.num_connector);
300
301 for (i = 0; i < fb_helper->connector_count; i++) {
302 struct drm_fb_helper_connector *fb_conn;
303 struct drm_connector *connector;
304 struct drm_encoder *encoder;
305 struct drm_fb_helper_crtc *new_crtc;
306
307 fb_conn = fb_helper->connector_info[i];
308 connector = fb_conn->connector;
309 if (!enabled[i]) {
310 DRM_DEBUG_KMS("connector %d not enabled, skipping\n",
311 connector->base.id);
312 continue;
313 }
314
315 encoder = connector->encoder;
316 if (!encoder || WARN_ON(!encoder->crtc)) {
317 DRM_DEBUG_KMS("connector %d has no encoder or crtc, skipping\n",
318 connector->base.id);
319 enabled[i] = false;
320 continue;
321 }
322
323 new_crtc = intel_fb_helper_crtc(fb_helper, encoder->crtc);
324
325 /*
326 * Make sure we're not trying to drive multiple connectors
327 * with a single CRTC, since our cloning support may not
328 * match the BIOS.
329 */
330 for (j = 0; j < fb_helper->connector_count; j++) {
331 if (crtcs[j] == new_crtc) {
332 any_enabled = false;
333 goto out;
334 }
335 }
336
337 DRM_DEBUG_KMS("looking for cmdline mode on connector %d\n",
338 fb_conn->connector->base.id);
339
340 /* go for command line mode first */
341 modes[i] = drm_pick_cmdline_mode(fb_conn, width, height);
342
343 /* try for preferred next */
344 if (!modes[i]) {
345 DRM_DEBUG_KMS("looking for preferred mode on connector %d\n",
346 fb_conn->connector->base.id);
347 modes[i] = drm_has_preferred_mode(fb_conn, width,
348 height);
349 }
350
351 /* last resort: use current mode */
352 if (!modes[i]) {
353 /*
354 * IMPORTANT: We want to use the adjusted mode (i.e.
355 * after the panel fitter upscaling) as the initial
356 * config, not the input mode, which is what crtc->mode
357 * usually contains. But since our current fastboot
358 * code puts a mode derived from the post-pfit timings
359 * into crtc->mode this works out correctly. We don't
360 * use hwmode anywhere right now, so use it for this
361 * since the fb helper layer wants a pointer to
362 * something we own.
363 */
364 intel_mode_from_pipe_config(&encoder->crtc->hwmode,
365 &to_intel_crtc(encoder->crtc)->config);
366 modes[i] = &encoder->crtc->hwmode;
367 }
368 crtcs[i] = new_crtc;
369
370 DRM_DEBUG_KMS("connector %s on crtc %d: %s\n",
371 drm_get_connector_name(connector),
372 encoder->crtc->base.id,
373 modes[i]->name);
374
375 any_enabled = true;
376 }
377
378out:
379 if (!any_enabled) {
380 memcpy(enabled, save_enabled, dev->mode_config.num_connector);
381 kfree(save_enabled);
382 return false;
383 }
384
385 kfree(save_enabled);
386 return true;
387}
388
239static struct drm_fb_helper_funcs intel_fb_helper_funcs = { 389static struct drm_fb_helper_funcs intel_fb_helper_funcs = {
390 .initial_config = intel_fb_initial_config,
240 .gamma_set = intel_crtc_fb_gamma_set, 391 .gamma_set = intel_crtc_fb_gamma_set,
241 .gamma_get = intel_crtc_fb_gamma_get, 392 .gamma_get = intel_crtc_fb_gamma_get,
242 .fb_probe = intelfb_create, 393 .fb_probe = intelfb_create,
@@ -258,8 +409,8 @@ static void intel_fbdev_destroy(struct drm_device *dev,
258 409
259 drm_fb_helper_fini(&ifbdev->helper); 410 drm_fb_helper_fini(&ifbdev->helper);
260 411
261 drm_framebuffer_unregister_private(&ifbdev->ifb.base); 412 drm_framebuffer_unregister_private(&ifbdev->fb->base);
262 intel_framebuffer_fini(&ifbdev->ifb); 413 drm_framebuffer_remove(&ifbdev->fb->base);
263} 414}
264 415
265int intel_fbdev_init(struct drm_device *dev) 416int intel_fbdev_init(struct drm_device *dev)
@@ -322,7 +473,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state)
322 * been restored from swap. If the object is stolen however, it will be 473 * been restored from swap. If the object is stolen however, it will be
323 * full of whatever garbage was left in there. 474 * full of whatever garbage was left in there.
324 */ 475 */
325 if (state == FBINFO_STATE_RUNNING && ifbdev->ifb.obj->stolen) 476 if (state == FBINFO_STATE_RUNNING && ifbdev->fb->obj->stolen)
326 memset_io(info->screen_base, 0, info->screen_size); 477 memset_io(info->screen_base, 0, info->screen_size);
327 478
328 fb_set_suspend(info, state); 479 fb_set_suspend(info, state);
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 43872f00822a..98d68ab04de4 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -425,7 +425,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 425 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
426 u32 reg = VIDEO_DIP_CTL; 426 u32 reg = VIDEO_DIP_CTL;
427 u32 val = I915_READ(reg); 427 u32 val = I915_READ(reg);
428 u32 port; 428 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
429 429
430 assert_hdmi_port_disabled(intel_hdmi); 430 assert_hdmi_port_disabled(intel_hdmi);
431 431
@@ -449,18 +449,6 @@ static void g4x_set_infoframes(struct drm_encoder *encoder,
449 return; 449 return;
450 } 450 }
451 451
452 switch (intel_dig_port->port) {
453 case PORT_B:
454 port = VIDEO_DIP_PORT_B;
455 break;
456 case PORT_C:
457 port = VIDEO_DIP_PORT_C;
458 break;
459 default:
460 BUG();
461 return;
462 }
463
464 if (port != (val & VIDEO_DIP_PORT_MASK)) { 452 if (port != (val & VIDEO_DIP_PORT_MASK)) {
465 if (val & VIDEO_DIP_ENABLE) { 453 if (val & VIDEO_DIP_ENABLE) {
466 val &= ~VIDEO_DIP_ENABLE; 454 val &= ~VIDEO_DIP_ENABLE;
@@ -491,7 +479,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
491 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; 479 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
492 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 480 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
493 u32 val = I915_READ(reg); 481 u32 val = I915_READ(reg);
494 u32 port; 482 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
495 483
496 assert_hdmi_port_disabled(intel_hdmi); 484 assert_hdmi_port_disabled(intel_hdmi);
497 485
@@ -507,21 +495,6 @@ static void ibx_set_infoframes(struct drm_encoder *encoder,
507 return; 495 return;
508 } 496 }
509 497
510 switch (intel_dig_port->port) {
511 case PORT_B:
512 port = VIDEO_DIP_PORT_B;
513 break;
514 case PORT_C:
515 port = VIDEO_DIP_PORT_C;
516 break;
517 case PORT_D:
518 port = VIDEO_DIP_PORT_D;
519 break;
520 default:
521 BUG();
522 return;
523 }
524
525 if (port != (val & VIDEO_DIP_PORT_MASK)) { 498 if (port != (val & VIDEO_DIP_PORT_MASK)) {
526 if (val & VIDEO_DIP_ENABLE) { 499 if (val & VIDEO_DIP_ENABLE) {
527 val &= ~VIDEO_DIP_ENABLE; 500 val &= ~VIDEO_DIP_ENABLE;
@@ -1263,6 +1236,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1263 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 1236 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1264 else 1237 else
1265 intel_connector->get_hw_state = intel_connector_get_hw_state; 1238 intel_connector->get_hw_state = intel_connector_get_hw_state;
1239 intel_connector->unregister = intel_connector_unregister;
1266 1240
1267 intel_hdmi_add_properties(intel_hdmi, connector); 1241 intel_hdmi_add_properties(intel_hdmi, connector);
1268 1242
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 3f3043b4ff26..fecff3c2b9e1 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -899,6 +899,7 @@ void intel_lvds_init(struct drm_device *dev)
899 struct drm_encoder *encoder; 899 struct drm_encoder *encoder;
900 struct drm_display_mode *scan; /* *modes, *bios_mode; */ 900 struct drm_display_mode *scan; /* *modes, *bios_mode; */
901 struct drm_display_mode *fixed_mode = NULL; 901 struct drm_display_mode *fixed_mode = NULL;
902 struct drm_display_mode *downclock_mode = NULL;
902 struct edid *edid; 903 struct edid *edid;
903 struct drm_crtc *crtc; 904 struct drm_crtc *crtc;
904 u32 lvds; 905 u32 lvds;
@@ -957,6 +958,7 @@ void intel_lvds_init(struct drm_device *dev)
957 intel_encoder->get_hw_state = intel_lvds_get_hw_state; 958 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
958 intel_encoder->get_config = intel_lvds_get_config; 959 intel_encoder->get_config = intel_lvds_get_config;
959 intel_connector->get_hw_state = intel_connector_get_hw_state; 960 intel_connector->get_hw_state = intel_connector_get_hw_state;
961 intel_connector->unregister = intel_connector_unregister;
960 962
961 intel_connector_attach_encoder(intel_connector, intel_encoder); 963 intel_connector_attach_encoder(intel_connector, intel_encoder);
962 intel_encoder->type = INTEL_OUTPUT_LVDS; 964 intel_encoder->type = INTEL_OUTPUT_LVDS;
@@ -1032,15 +1034,14 @@ void intel_lvds_init(struct drm_device *dev)
1032 1034
1033 fixed_mode = drm_mode_duplicate(dev, scan); 1035 fixed_mode = drm_mode_duplicate(dev, scan);
1034 if (fixed_mode) { 1036 if (fixed_mode) {
1035 intel_connector->panel.downclock_mode = 1037 downclock_mode =
1036 intel_find_panel_downclock(dev, 1038 intel_find_panel_downclock(dev,
1037 fixed_mode, connector); 1039 fixed_mode, connector);
1038 if (intel_connector->panel.downclock_mode != 1040 if (downclock_mode != NULL &&
1039 NULL && i915.lvds_downclock) { 1041 i915.lvds_downclock) {
1040 /* We found the downclock for LVDS. */ 1042 /* We found the downclock for LVDS. */
1041 dev_priv->lvds_downclock_avail = true; 1043 dev_priv->lvds_downclock_avail = true;
1042 dev_priv->lvds_downclock = 1044 dev_priv->lvds_downclock =
1043 intel_connector->panel.
1044 downclock_mode->clock; 1045 downclock_mode->clock;
1045 DRM_DEBUG_KMS("LVDS downclock is found" 1046 DRM_DEBUG_KMS("LVDS downclock is found"
1046 " in EDID. Normal clock %dKhz, " 1047 " in EDID. Normal clock %dKhz, "
@@ -1116,7 +1117,7 @@ out:
1116 } 1117 }
1117 drm_sysfs_connector_add(connector); 1118 drm_sysfs_connector_add(connector);
1118 1119
1119 intel_panel_init(&intel_connector->panel, fixed_mode); 1120 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1120 intel_panel_setup_backlight(connector); 1121 intel_panel_setup_backlight(connector);
1121 1122
1122 return; 1123 return;
@@ -1125,8 +1126,6 @@ failed:
1125 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); 1126 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1126 drm_connector_cleanup(connector); 1127 drm_connector_cleanup(connector);
1127 drm_encoder_cleanup(encoder); 1128 drm_encoder_cleanup(encoder);
1128 if (fixed_mode)
1129 drm_mode_destroy(dev, fixed_mode);
1130 kfree(lvds_encoder); 1129 kfree(lvds_encoder);
1131 kfree(lvds_connector); 1130 kfree(lvds_connector);
1132 return; 1131 return;
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 424f0946d8c4..ac519cb46f22 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1349,7 +1349,7 @@ void intel_setup_overlay(struct drm_device *dev)
1349 } 1349 }
1350 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr; 1350 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1351 } else { 1351 } else {
1352 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, true, false); 1352 ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE);
1353 if (ret) { 1353 if (ret) {
1354 DRM_ERROR("failed to pin overlay register bo\n"); 1354 DRM_ERROR("failed to pin overlay register bo\n");
1355 goto out_free_bo; 1355 goto out_free_bo;
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index f1ee2c4d282e..5bc3f6ea1014 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1190,9 +1190,11 @@ void intel_panel_init_backlight_funcs(struct drm_device *dev)
1190} 1190}
1191 1191
1192int intel_panel_init(struct intel_panel *panel, 1192int intel_panel_init(struct intel_panel *panel,
1193 struct drm_display_mode *fixed_mode) 1193 struct drm_display_mode *fixed_mode,
1194 struct drm_display_mode *downclock_mode)
1194{ 1195{
1195 panel->fixed_mode = fixed_mode; 1196 panel->fixed_mode = fixed_mode;
1197 panel->downclock_mode = downclock_mode;
1196 1198
1197 return 0; 1199 return 0;
1198} 1200}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f74d7f506aa9..a6b877a4a916 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2741,7 +2741,7 @@ intel_alloc_context_page(struct drm_device *dev)
2741 return NULL; 2741 return NULL;
2742 } 2742 }
2743 2743
2744 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false); 2744 ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2745 if (ret) { 2745 if (ret) {
2746 DRM_ERROR("failed to pin power context: %d\n", ret); 2746 DRM_ERROR("failed to pin power context: %d\n", ret);
2747 goto err_unref; 2747 goto err_unref;
@@ -3196,16 +3196,10 @@ static void valleyview_disable_rps(struct drm_device *dev)
3196 3196
3197static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 3197static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3198{ 3198{
3199 if (IS_GEN6(dev))
3200 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3201
3202 if (IS_HASWELL(dev))
3203 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3204
3205 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 3199 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3206 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 3200 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3207 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 3201 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3208 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 3202 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3209} 3203}
3210 3204
3211int intel_enable_rc6(const struct drm_device *dev) 3205int intel_enable_rc6(const struct drm_device *dev)
@@ -3222,14 +3216,10 @@ int intel_enable_rc6(const struct drm_device *dev)
3222 if (INTEL_INFO(dev)->gen == 5) 3216 if (INTEL_INFO(dev)->gen == 5)
3223 return 0; 3217 return 0;
3224 3218
3225 if (IS_HASWELL(dev)) 3219 if (IS_IVYBRIDGE(dev))
3226 return INTEL_RC6_ENABLE; 3220 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3227
3228 /* snb/ivb have more than one rc6 state. */
3229 if (INTEL_INFO(dev)->gen == 6)
3230 return INTEL_RC6_ENABLE;
3231 3221
3232 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 3222 return INTEL_RC6_ENABLE;
3233} 3223}
3234 3224
3235static void gen6_enable_rps_interrupts(struct drm_device *dev) 3225static void gen6_enable_rps_interrupts(struct drm_device *dev)
@@ -3286,10 +3276,10 @@ static void gen8_enable_rps(struct drm_device *dev)
3286 /* 3: Enable RC6 */ 3276 /* 3: Enable RC6 */
3287 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 3277 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3288 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 3278 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3289 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 3279 intel_print_rc6_info(dev, rc6_mask);
3290 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 3280 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3291 GEN6_RC_CTL_EI_MODE(1) | 3281 GEN6_RC_CTL_EI_MODE(1) |
3292 rc6_mask); 3282 rc6_mask);
3293 3283
3294 /* 4 Program defaults and thresholds for RPS*/ 3284 /* 4 Program defaults and thresholds for RPS*/
3295 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ 3285 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */
@@ -3903,9 +3893,10 @@ static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3903 3893
3904unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 3894unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3905{ 3895{
3896 struct drm_device *dev = dev_priv->dev;
3906 unsigned long val; 3897 unsigned long val;
3907 3898
3908 if (dev_priv->info->gen != 5) 3899 if (INTEL_INFO(dev)->gen != 5)
3909 return 0; 3900 return 0;
3910 3901
3911 spin_lock_irq(&mchdev_lock); 3902 spin_lock_irq(&mchdev_lock);
@@ -3934,6 +3925,7 @@ unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3934 3925
3935static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 3926static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3936{ 3927{
3928 struct drm_device *dev = dev_priv->dev;
3937 static const struct v_table { 3929 static const struct v_table {
3938 u16 vd; /* in .1 mil */ 3930 u16 vd; /* in .1 mil */
3939 u16 vm; /* in .1 mil */ 3931 u16 vm; /* in .1 mil */
@@ -4067,7 +4059,7 @@ static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4067 { 16000, 14875, }, 4059 { 16000, 14875, },
4068 { 16125, 15000, }, 4060 { 16125, 15000, },
4069 }; 4061 };
4070 if (dev_priv->info->is_mobile) 4062 if (INTEL_INFO(dev)->is_mobile)
4071 return v_table[pxvid].vm; 4063 return v_table[pxvid].vm;
4072 else 4064 else
4073 return v_table[pxvid].vd; 4065 return v_table[pxvid].vd;
@@ -4110,7 +4102,9 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4110 4102
4111void i915_update_gfx_val(struct drm_i915_private *dev_priv) 4103void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4112{ 4104{
4113 if (dev_priv->info->gen != 5) 4105 struct drm_device *dev = dev_priv->dev;
4106
4107 if (INTEL_INFO(dev)->gen != 5)
4114 return; 4108 return;
4115 4109
4116 spin_lock_irq(&mchdev_lock); 4110 spin_lock_irq(&mchdev_lock);
@@ -4159,9 +4153,10 @@ static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4159 4153
4160unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 4154unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4161{ 4155{
4156 struct drm_device *dev = dev_priv->dev;
4162 unsigned long val; 4157 unsigned long val;
4163 4158
4164 if (dev_priv->info->gen != 5) 4159 if (INTEL_INFO(dev)->gen != 5)
4165 return 0; 4160 return 0;
4166 4161
4167 spin_lock_irq(&mchdev_lock); 4162 spin_lock_irq(&mchdev_lock);
@@ -4698,6 +4693,14 @@ static void gen6_init_clock_gating(struct drm_device *dev)
4698 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 4693 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4699 4694
4700 /* 4695 /*
4696 * Bspec says:
4697 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
4698 * 3DSTATE_SF number of SF output attributes is more than 16."
4699 */
4700 I915_WRITE(_3D_CHICKEN3,
4701 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
4702
4703 /*
4701 * According to the spec the following bits should be 4704 * According to the spec the following bits should be
4702 * set in order to enable memory self-refresh and fbc: 4705 * set in order to enable memory self-refresh and fbc:
4703 * The bit21 and bit22 of 0x42000 4706 * The bit21 and bit22 of 0x42000
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8c1c0bc3e630..b340c7587629 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -531,9 +531,11 @@ init_pipe_control(struct intel_ring_buffer *ring)
531 goto err; 531 goto err;
532 } 532 }
533 533
534 i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); 534 ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
535 if (ret)
536 goto err_unref;
535 537
536 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false); 538 ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0);
537 if (ret) 539 if (ret)
538 goto err_unref; 540 goto err_unref;
539 541
@@ -1271,12 +1273,13 @@ static int init_status_page(struct intel_ring_buffer *ring)
1271 goto err; 1273 goto err;
1272 } 1274 }
1273 1275
1274 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 1276 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1277 if (ret)
1278 goto err_unref;
1275 1279
1276 ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false); 1280 ret = i915_gem_obj_ggtt_pin(obj, 4096, 0);
1277 if (ret != 0) { 1281 if (ret)
1278 goto err_unref; 1282 goto err_unref;
1279 }
1280 1283
1281 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); 1284 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1282 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); 1285 ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
@@ -1356,7 +1359,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
1356 1359
1357 ring->obj = obj; 1360 ring->obj = obj;
1358 1361
1359 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false); 1362 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
1360 if (ret) 1363 if (ret)
1361 goto err_unref; 1364 goto err_unref;
1362 1365
@@ -1513,7 +1516,8 @@ static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1513 return 0; 1516 return 0;
1514 } 1517 }
1515 1518
1516 if (dev->primary->master) { 1519 if (!drm_core_check_feature(dev, DRIVER_MODESET) &&
1520 dev->primary->master) {
1517 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1521 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1518 if (master_priv->sarea_priv) 1522 if (master_priv->sarea_priv)
1519 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1523 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
@@ -1939,7 +1943,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
1939 return -ENOMEM; 1943 return -ENOMEM;
1940 } 1944 }
1941 1945
1942 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); 1946 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
1943 if (ret != 0) { 1947 if (ret != 0) {
1944 drm_gem_object_unreference(&obj->base); 1948 drm_gem_object_unreference(&obj->base);
1945 DRM_ERROR("Failed to ping batch bo\n"); 1949 DRM_ERROR("Failed to ping batch bo\n");
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 95bdfb3c431c..825853d82a4d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2382,24 +2382,62 @@ intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
2382} 2382}
2383 2383
2384static void 2384static void
2385intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
2386{
2387 struct drm_connector *drm_connector;
2388 struct intel_sdvo *sdvo_encoder;
2389
2390 drm_connector = &intel_connector->base;
2391 sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
2392
2393 sysfs_remove_link(&drm_connector->kdev->kobj,
2394 sdvo_encoder->ddc.dev.kobj.name);
2395 intel_connector_unregister(intel_connector);
2396}
2397
2398static int
2385intel_sdvo_connector_init(struct intel_sdvo_connector *connector, 2399intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2386 struct intel_sdvo *encoder) 2400 struct intel_sdvo *encoder)
2387{ 2401{
2388 drm_connector_init(encoder->base.base.dev, 2402 struct drm_connector *drm_connector;
2389 &connector->base.base, 2403 int ret;
2404
2405 drm_connector = &connector->base.base;
2406 ret = drm_connector_init(encoder->base.base.dev,
2407 drm_connector,
2390 &intel_sdvo_connector_funcs, 2408 &intel_sdvo_connector_funcs,
2391 connector->base.base.connector_type); 2409 connector->base.base.connector_type);
2410 if (ret < 0)
2411 return ret;
2392 2412
2393 drm_connector_helper_add(&connector->base.base, 2413 drm_connector_helper_add(drm_connector,
2394 &intel_sdvo_connector_helper_funcs); 2414 &intel_sdvo_connector_helper_funcs);
2395 2415
2396 connector->base.base.interlace_allowed = 1; 2416 connector->base.base.interlace_allowed = 1;
2397 connector->base.base.doublescan_allowed = 0; 2417 connector->base.base.doublescan_allowed = 0;
2398 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; 2418 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2399 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; 2419 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2420 connector->base.unregister = intel_sdvo_connector_unregister;
2400 2421
2401 intel_connector_attach_encoder(&connector->base, &encoder->base); 2422 intel_connector_attach_encoder(&connector->base, &encoder->base);
2402 drm_sysfs_connector_add(&connector->base.base); 2423 ret = drm_sysfs_connector_add(drm_connector);
2424 if (ret < 0)
2425 goto err1;
2426
2427 ret = sysfs_create_link(&encoder->ddc.dev.kobj,
2428 &drm_connector->kdev->kobj,
2429 encoder->ddc.dev.kobj.name);
2430 if (ret < 0)
2431 goto err2;
2432
2433 return 0;
2434
2435err2:
2436 drm_sysfs_connector_remove(drm_connector);
2437err1:
2438 drm_connector_cleanup(drm_connector);
2439
2440 return ret;
2403} 2441}
2404 2442
2405static void 2443static void
@@ -2459,7 +2497,11 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2459 intel_sdvo->is_hdmi = true; 2497 intel_sdvo->is_hdmi = true;
2460 } 2498 }
2461 2499
2462 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2500 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2501 kfree(intel_sdvo_connector);
2502 return false;
2503 }
2504
2463 if (intel_sdvo->is_hdmi) 2505 if (intel_sdvo->is_hdmi)
2464 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); 2506 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2465 2507
@@ -2490,7 +2532,10 @@ intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2490 2532
2491 intel_sdvo->is_tv = true; 2533 intel_sdvo->is_tv = true;
2492 2534
2493 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2535 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2536 kfree(intel_sdvo_connector);
2537 return false;
2538 }
2494 2539
2495 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) 2540 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2496 goto err; 2541 goto err;
@@ -2534,8 +2579,11 @@ intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2534 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; 2579 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2535 } 2580 }
2536 2581
2537 intel_sdvo_connector_init(intel_sdvo_connector, 2582 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2538 intel_sdvo); 2583 kfree(intel_sdvo_connector);
2584 return false;
2585 }
2586
2539 return true; 2587 return true;
2540} 2588}
2541 2589
@@ -2566,7 +2614,11 @@ intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2566 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; 2614 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2567 } 2615 }
2568 2616
2569 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); 2617 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2618 kfree(intel_sdvo_connector);
2619 return false;
2620 }
2621
2570 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) 2622 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2571 goto err; 2623 goto err;
2572 2624
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 22cf0f4ba248..b64fc1c6ff3f 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1189,8 +1189,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
1189 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1189 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1190 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1190 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1191 i915_disable_pipestat(dev_priv, 0, 1191 i915_disable_pipestat(dev_priv, 0,
1192 PIPE_HOTPLUG_INTERRUPT_ENABLE | 1192 PIPE_HOTPLUG_INTERRUPT_STATUS |
1193 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1193 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1194 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1194 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1195 } 1195 }
1196 1196
@@ -1266,8 +1266,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv,
1266 if (connector->polled & DRM_CONNECTOR_POLL_HPD) { 1266 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1267 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); 1267 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1268 i915_enable_pipestat(dev_priv, 0, 1268 i915_enable_pipestat(dev_priv, 0,
1269 PIPE_HOTPLUG_INTERRUPT_ENABLE | 1269 PIPE_HOTPLUG_INTERRUPT_STATUS |
1270 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE); 1270 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
1271 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); 1271 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1272 } 1272 }
1273 1273
@@ -1634,6 +1634,7 @@ intel_tv_init(struct drm_device *dev)
1634 intel_encoder->disable = intel_disable_tv; 1634 intel_encoder->disable = intel_disable_tv;
1635 intel_encoder->get_hw_state = intel_tv_get_hw_state; 1635 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1636 intel_connector->get_hw_state = intel_connector_get_hw_state; 1636 intel_connector->get_hw_state = intel_connector_get_hw_state;
1637 intel_connector->unregister = intel_connector_unregister;
1637 1638
1638 intel_connector_attach_encoder(intel_connector, intel_encoder); 1639 intel_connector_attach_encoder(intel_connector, intel_encoder);
1639 intel_encoder->type = INTEL_OUTPUT_TVOUT; 1640 intel_encoder->type = INTEL_OUTPUT_TVOUT;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 23:59:49 -0500