diff options
author | Thierry Reding <treding@nvidia.com> | 2015-01-28 10:14:26 -0500 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2015-04-02 12:49:22 -0400 |
commit | 375e118437716acdccda224abb3d464ecfe92884 (patch) | |
tree | 8460c95274239e289bb5d7f678b86fbc61c0c9d9 /drivers/gpu/drm | |
parent | 9d910b6068be9b6670d0ebba2ddc3e7816dd8881 (diff) |
drm/tegra: hdmi: Resets are synchronous
Resets on Tegra are synchronous, so keep the clock enabled while
asserting the reset.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/tegra/hdmi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c index 7eaaee74a039..05213b2ec2bd 100644 --- a/drivers/gpu/drm/tegra/hdmi.c +++ b/drivers/gpu/drm/tegra/hdmi.c | |||
@@ -1394,8 +1394,8 @@ static int tegra_hdmi_exit(struct host1x_client *client) | |||
1394 | 1394 | ||
1395 | tegra_output_exit(&hdmi->output); | 1395 | tegra_output_exit(&hdmi->output); |
1396 | 1396 | ||
1397 | clk_disable_unprepare(hdmi->clk); | ||
1398 | reset_control_assert(hdmi->rst); | 1397 | reset_control_assert(hdmi->rst); |
1398 | clk_disable_unprepare(hdmi->clk); | ||
1399 | 1399 | ||
1400 | regulator_disable(hdmi->vdd); | 1400 | regulator_disable(hdmi->vdd); |
1401 | regulator_disable(hdmi->pll); | 1401 | regulator_disable(hdmi->pll); |