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authorBen Widawsky <benjamin.widawsky@intel.com>2013-11-03 00:07:04 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-11-08 12:09:37 -0500
commit31a5336e1c8e7cffb5ce3f6530aded7c05edb664 (patch)
tree34f0d0969d8ed6b71fb1a8f209742b7ee7f0b0af /drivers/gpu/drm
parent5ab31333ac94f808e2249a0955a2a79b2b1c32a1 (diff)
drm/i915/bdw: Swizzling support
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c2
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5be1a154f09e..12bbd5eac70d 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4362,6 +4362,8 @@ void i915_gem_init_swizzling(struct drm_device *dev)
4362 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); 4362 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4363 else if (IS_GEN7(dev)) 4363 else if (IS_GEN7(dev))
4364 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); 4364 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4365 else if (IS_GEN8(dev))
4366 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4365 else 4367 else
4366 BUG(); 4368 BUG();
4367} 4369}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f303ba995c5..0c5cb3cea9c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -655,6 +655,8 @@
655#define ARB_MODE 0x04030 655#define ARB_MODE 0x04030
656#define ARB_MODE_SWIZZLE_SNB (1<<4) 656#define ARB_MODE_SWIZZLE_SNB (1<<4)
657#define ARB_MODE_SWIZZLE_IVB (1<<5) 657#define ARB_MODE_SWIZZLE_IVB (1<<5)
658#define GAMTARBMODE 0x04a08
659#define ARB_MODE_SWIZZLE_BDW (1<<1)
658#define RENDER_HWS_PGA_GEN7 (0x04080) 660#define RENDER_HWS_PGA_GEN7 (0x04080)
659#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id) 661#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
660#define RING_FAULT_GTTSEL_MASK (1<<11) 662#define RING_FAULT_GTTSEL_MASK (1<<11)