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authorJerome Glisse <jglisse@redhat.com>2011-11-20 15:45:34 -0500
committerDave Airlie <airlied@redhat.com>2011-12-20 14:51:19 -0500
commit30eb77f4e6ba20f797af4ff79807fae7cb67429e (patch)
tree0143bb70c00f3080d70cf8e2a966cf8d7f137dfc /drivers/gpu/drm
parentaf9720f4907e0a4a4341a015efe08026b3d3eb2e (diff)
drm/radeon: precompute fence cpu/gpu addr once v3
Add a start fence driver helper function which will be call once for each ring and will compute cpu/gpu addr for fence depending on wether to use wb buffer or scratch reg. This patch replace initialize fence driver separately which was broken in regard of GPU lockup. The fence list for created, emited, signaled must be initialize once and only from the asic init callback not from the startup call back which is call from the gpu reset. v2: With this in place we no longer need to know the number of rings in fence_driver_init, also writing to the scratch reg before knowing its offset is a bad idea. v3: rebase on top of change to previous patch in the serie Signed-off-by: Christian König <deathsimple@vodafone.de> Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c8
-rw-r--r--drivers/gpu/drm/radeon/ni.c20
-rw-r--r--drivers/gpu/drm/radeon/r100.c8
-rw-r--r--drivers/gpu/drm/radeon/r300.c8
-rw-r--r--drivers/gpu/drm/radeon/r420.c8
-rw-r--r--drivers/gpu/drm/radeon/r520.c8
-rw-r--r--drivers/gpu/drm/radeon/r600.c11
-rw-r--r--drivers/gpu/drm/radeon/radeon.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c89
-rw-r--r--drivers/gpu/drm/radeon/rs400.c8
-rw-r--r--drivers/gpu/drm/radeon/rs600.c8
-rw-r--r--drivers/gpu/drm/radeon/rs690.c8
-rw-r--r--drivers/gpu/drm/radeon/rv515.c8
-rw-r--r--drivers/gpu/drm/radeon/rv770.c8
14 files changed, 152 insertions, 53 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index b19ace86121e..ba19b9a697b0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3111,6 +3111,12 @@ static int evergreen_startup(struct radeon_device *rdev)
3111 if (r) 3111 if (r)
3112 return r; 3112 return r;
3113 3113
3114 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3115 if (r) {
3116 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3117 return r;
3118 }
3119
3114 /* Enable IRQ */ 3120 /* Enable IRQ */
3115 r = r600_irq_init(rdev); 3121 r = r600_irq_init(rdev);
3116 if (r) { 3122 if (r) {
@@ -3229,7 +3235,7 @@ int evergreen_init(struct radeon_device *rdev)
3229 /* Initialize clocks */ 3235 /* Initialize clocks */
3230 radeon_get_clock_info(rdev->ddev); 3236 radeon_get_clock_info(rdev->ddev);
3231 /* Fence driver */ 3237 /* Fence driver */
3232 r = radeon_fence_driver_init(rdev, 1); 3238 r = radeon_fence_driver_init(rdev);
3233 if (r) 3239 if (r)
3234 return r; 3240 return r;
3235 /* initialize AGP */ 3241 /* initialize AGP */
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 022a606c783b..a9b0e615804f 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1384,6 +1384,24 @@ static int cayman_startup(struct radeon_device *rdev)
1384 if (r) 1384 if (r)
1385 return r; 1385 return r;
1386 1386
1387 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1388 if (r) {
1389 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1390 return r;
1391 }
1392
1393 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1394 if (r) {
1395 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1396 return r;
1397 }
1398
1399 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1400 if (r) {
1401 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1402 return r;
1403 }
1404
1387 /* Enable IRQ */ 1405 /* Enable IRQ */
1388 r = r600_irq_init(rdev); 1406 r = r600_irq_init(rdev);
1389 if (r) { 1407 if (r) {
@@ -1492,7 +1510,7 @@ int cayman_init(struct radeon_device *rdev)
1492 /* Initialize clocks */ 1510 /* Initialize clocks */
1493 radeon_get_clock_info(rdev->ddev); 1511 radeon_get_clock_info(rdev->ddev);
1494 /* Fence driver */ 1512 /* Fence driver */
1495 r = radeon_fence_driver_init(rdev, 3); 1513 r = radeon_fence_driver_init(rdev);
1496 if (r) 1514 if (r)
1497 return r; 1515 return r;
1498 /* initialize memory controller */ 1516 /* initialize memory controller */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index a40e893a7b69..bed56c7b690b 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3916,6 +3916,12 @@ static int r100_startup(struct radeon_device *rdev)
3916 if (r) 3916 if (r)
3917 return r; 3917 return r;
3918 3918
3919 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3920 if (r) {
3921 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3922 return r;
3923 }
3924
3919 /* Enable IRQ */ 3925 /* Enable IRQ */
3920 r100_irq_set(rdev); 3926 r100_irq_set(rdev);
3921 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 3927 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -4059,7 +4065,7 @@ int r100_init(struct radeon_device *rdev)
4059 /* initialize VRAM */ 4065 /* initialize VRAM */
4060 r100_mc_init(rdev); 4066 r100_mc_init(rdev);
4061 /* Fence driver */ 4067 /* Fence driver */
4062 r = radeon_fence_driver_init(rdev, 1); 4068 r = radeon_fence_driver_init(rdev);
4063 if (r) 4069 if (r)
4064 return r; 4070 return r;
4065 r = radeon_irq_kms_init(rdev); 4071 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 6a96b31b558f..e2dfae4b40e6 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1399,6 +1399,12 @@ static int r300_startup(struct radeon_device *rdev)
1399 if (r) 1399 if (r)
1400 return r; 1400 return r;
1401 1401
1402 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1403 if (r) {
1404 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1405 return r;
1406 }
1407
1402 /* Enable IRQ */ 1408 /* Enable IRQ */
1403 r100_irq_set(rdev); 1409 r100_irq_set(rdev);
1404 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 1410 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -1521,7 +1527,7 @@ int r300_init(struct radeon_device *rdev)
1521 /* initialize memory controller */ 1527 /* initialize memory controller */
1522 r300_mc_init(rdev); 1528 r300_mc_init(rdev);
1523 /* Fence driver */ 1529 /* Fence driver */
1524 r = radeon_fence_driver_init(rdev, 1); 1530 r = radeon_fence_driver_init(rdev);
1525 if (r) 1531 if (r)
1526 return r; 1532 return r;
1527 r = radeon_irq_kms_init(rdev); 1533 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 1d3231f3a090..17ecff1000e7 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -258,6 +258,12 @@ static int r420_startup(struct radeon_device *rdev)
258 if (r) 258 if (r)
259 return r; 259 return r;
260 260
261 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
262 if (r) {
263 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
264 return r;
265 }
266
261 /* Enable IRQ */ 267 /* Enable IRQ */
262 r100_irq_set(rdev); 268 r100_irq_set(rdev);
263 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 269 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -391,7 +397,7 @@ int r420_init(struct radeon_device *rdev)
391 r300_mc_init(rdev); 397 r300_mc_init(rdev);
392 r420_debugfs(rdev); 398 r420_debugfs(rdev);
393 /* Fence driver */ 399 /* Fence driver */
394 r = radeon_fence_driver_init(rdev, 1); 400 r = radeon_fence_driver_init(rdev);
395 if (r) { 401 if (r) {
396 return r; 402 return r;
397 } 403 }
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index cb96a51f7f7c..39b31544c6e7 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -187,6 +187,12 @@ static int r520_startup(struct radeon_device *rdev)
187 if (r) 187 if (r)
188 return r; 188 return r;
189 189
190 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
191 if (r) {
192 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
193 return r;
194 }
195
190 /* Enable IRQ */ 196 /* Enable IRQ */
191 rs600_irq_set(rdev); 197 rs600_irq_set(rdev);
192 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 198 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -278,7 +284,7 @@ int r520_init(struct radeon_device *rdev)
278 r520_mc_init(rdev); 284 r520_mc_init(rdev);
279 rv515_debugfs(rdev); 285 rv515_debugfs(rdev);
280 /* Fence driver */ 286 /* Fence driver */
281 r = radeon_fence_driver_init(rdev, 1); 287 r = radeon_fence_driver_init(rdev);
282 if (r) 288 if (r)
283 return r; 289 return r;
284 r = radeon_irq_kms_init(rdev); 290 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 17538926cc47..f2deadfcd88f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2313,8 +2313,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
2313 struct radeon_ring *ring = &rdev->ring[fence->ring]; 2313 struct radeon_ring *ring = &rdev->ring[fence->ring];
2314 2314
2315 if (rdev->wb.use_event) { 2315 if (rdev->wb.use_event) {
2316 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + 2316 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2317 (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
2318 /* flush read cache over gart */ 2317 /* flush read cache over gart */
2319 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2318 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2320 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | 2319 radeon_ring_write(ring, PACKET3_TC_ACTION_ENA |
@@ -2459,6 +2458,12 @@ int r600_startup(struct radeon_device *rdev)
2459 if (r) 2458 if (r)
2460 return r; 2459 return r;
2461 2460
2461 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2462 if (r) {
2463 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2464 return r;
2465 }
2466
2462 /* Enable IRQ */ 2467 /* Enable IRQ */
2463 r = r600_irq_init(rdev); 2468 r = r600_irq_init(rdev);
2464 if (r) { 2469 if (r) {
@@ -2589,7 +2594,7 @@ int r600_init(struct radeon_device *rdev)
2589 /* Initialize clocks */ 2594 /* Initialize clocks */
2590 radeon_get_clock_info(rdev->ddev); 2595 radeon_get_clock_info(rdev->ddev);
2591 /* Fence driver */ 2596 /* Fence driver */
2592 r = radeon_fence_driver_init(rdev, 1); 2597 r = radeon_fence_driver_init(rdev);
2593 if (r) 2598 if (r)
2594 return r; 2599 return r;
2595 if (rdev->flags & RADEON_IS_AGP) { 2600 if (rdev->flags & RADEON_IS_AGP) {
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 014065af60dc..5777afb361de 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -192,6 +192,8 @@ extern int sumo_get_temp(struct radeon_device *rdev);
192 */ 192 */
193struct radeon_fence_driver { 193struct radeon_fence_driver {
194 uint32_t scratch_reg; 194 uint32_t scratch_reg;
195 uint64_t gpu_addr;
196 volatile uint32_t *cpu_addr;
195 atomic_t seq; 197 atomic_t seq;
196 uint32_t last_seq; 198 uint32_t last_seq;
197 unsigned long last_jiffies; 199 unsigned long last_jiffies;
@@ -215,7 +217,8 @@ struct radeon_fence {
215 int ring; 217 int ring;
216}; 218};
217 219
218int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings); 220int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
221int radeon_fence_driver_init(struct radeon_device *rdev);
219void radeon_fence_driver_fini(struct radeon_device *rdev); 222void radeon_fence_driver_fini(struct radeon_device *rdev);
220int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring); 223int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
221int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); 224int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 809e66e8a86e..8d626baaa064 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -42,35 +42,22 @@
42 42
43static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring) 43static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
44{ 44{
45 u32 scratch_index;
46
47 if (rdev->wb.enabled) { 45 if (rdev->wb.enabled) {
48 if (rdev->wb.use_event) 46 *rdev->fence_drv[ring].cpu_addr = cpu_to_le32(seq);
49 scratch_index = R600_WB_EVENT_OFFSET + 47 } else {
50 rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
51 else
52 scratch_index = RADEON_WB_SCRATCH_OFFSET +
53 rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
54 rdev->wb.wb[scratch_index/4] = cpu_to_le32(seq);
55 } else
56 WREG32(rdev->fence_drv[ring].scratch_reg, seq); 48 WREG32(rdev->fence_drv[ring].scratch_reg, seq);
49 }
57} 50}
58 51
59static u32 radeon_fence_read(struct radeon_device *rdev, int ring) 52static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
60{ 53{
61 u32 seq = 0; 54 u32 seq = 0;
62 u32 scratch_index;
63 55
64 if (rdev->wb.enabled) { 56 if (rdev->wb.enabled) {
65 if (rdev->wb.use_event) 57 seq = le32_to_cpu(*rdev->fence_drv[ring].cpu_addr);
66 scratch_index = R600_WB_EVENT_OFFSET + 58 } else {
67 rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
68 else
69 scratch_index = RADEON_WB_SCRATCH_OFFSET +
70 rdev->fence_drv[ring].scratch_reg - rdev->scratch.reg_base;
71 seq = le32_to_cpu(rdev->wb.wb[scratch_index/4]);
72 } else
73 seq = RREG32(rdev->fence_drv[ring].scratch_reg); 59 seq = RREG32(rdev->fence_drv[ring].scratch_reg);
60 }
74 return seq; 61 return seq;
75} 62}
76 63
@@ -389,36 +376,61 @@ int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
389 return not_processed; 376 return not_processed;
390} 377}
391 378
392int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings) 379int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
393{ 380{
394 unsigned long irq_flags; 381 unsigned long irq_flags;
395 int r, ring; 382 uint64_t index;
383 int r;
396 384
397 for (ring = 0; ring < num_rings; ring++) { 385 write_lock_irqsave(&rdev->fence_lock, irq_flags);
398 write_lock_irqsave(&rdev->fence_lock, irq_flags); 386 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
387 if (rdev->wb.use_event) {
388 rdev->fence_drv[ring].scratch_reg = 0;
389 index = R600_WB_EVENT_OFFSET + ring * 4;
390 } else {
399 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg); 391 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
400 if (r) { 392 if (r) {
401 dev_err(rdev->dev, "fence failed to get scratch register\n"); 393 dev_err(rdev->dev, "fence failed to get scratch register\n");
402 write_unlock_irqrestore(&rdev->fence_lock, irq_flags); 394 write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
403 return r; 395 return r;
404 } 396 }
405 radeon_fence_write(rdev, 0, ring); 397 index = RADEON_WB_SCRATCH_OFFSET +
406 atomic_set(&rdev->fence_drv[ring].seq, 0); 398 rdev->fence_drv[ring].scratch_reg -
407 INIT_LIST_HEAD(&rdev->fence_drv[ring].created); 399 rdev->scratch.reg_base;
408 INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
409 INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
410 init_waitqueue_head(&rdev->fence_drv[ring].queue);
411 rdev->fence_drv[ring].initialized = true;
412 write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
413 } 400 }
414 for (ring = num_rings; ring < RADEON_NUM_RINGS; ring++) { 401 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
415 write_lock_irqsave(&rdev->fence_lock, irq_flags); 402 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
416 INIT_LIST_HEAD(&rdev->fence_drv[ring].created); 403 radeon_fence_write(rdev, atomic_read(&rdev->fence_drv[ring].seq), ring);
417 INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted); 404 rdev->fence_drv[ring].initialized = true;
418 INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled); 405 DRM_INFO("fence driver on ring %d use gpu addr 0x%08Lx and cpu addr 0x%p\n",
419 rdev->fence_drv[ring].initialized = false; 406 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
420 write_unlock_irqrestore(&rdev->fence_lock, irq_flags); 407 write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
408 return 0;
409}
410
411static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
412{
413 rdev->fence_drv[ring].scratch_reg = -1;
414 rdev->fence_drv[ring].cpu_addr = NULL;
415 rdev->fence_drv[ring].gpu_addr = 0;
416 atomic_set(&rdev->fence_drv[ring].seq, 0);
417 INIT_LIST_HEAD(&rdev->fence_drv[ring].created);
418 INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
419 INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
420 init_waitqueue_head(&rdev->fence_drv[ring].queue);
421 rdev->fence_drv[ring].initialized = false;
422}
423
424int radeon_fence_driver_init(struct radeon_device *rdev)
425{
426 unsigned long irq_flags;
427 int ring;
428
429 write_lock_irqsave(&rdev->fence_lock, irq_flags);
430 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
431 radeon_fence_driver_init_ring(rdev, ring);
421 } 432 }
433 write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
422 if (radeon_debugfs_fence_init(rdev)) { 434 if (radeon_debugfs_fence_init(rdev)) {
423 dev_err(rdev->dev, "fence debugfs file creation failed\n"); 435 dev_err(rdev->dev, "fence debugfs file creation failed\n");
424 } 436 }
@@ -433,6 +445,7 @@ void radeon_fence_driver_fini(struct radeon_device *rdev)
433 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { 445 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
434 if (!rdev->fence_drv[ring].initialized) 446 if (!rdev->fence_drv[ring].initialized)
435 continue; 447 continue;
448 radeon_fence_wait_last(rdev, ring);
436 wake_up_all(&rdev->fence_drv[ring].queue); 449 wake_up_all(&rdev->fence_drv[ring].queue);
437 write_lock_irqsave(&rdev->fence_lock, irq_flags); 450 write_lock_irqsave(&rdev->fence_lock, irq_flags);
438 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); 451 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index c71fa16106ca..5c86d5161fdb 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -410,6 +410,12 @@ static int rs400_startup(struct radeon_device *rdev)
410 if (r) 410 if (r)
411 return r; 411 return r;
412 412
413 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
414 if (r) {
415 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
416 return r;
417 }
418
413 /* Enable IRQ */ 419 /* Enable IRQ */
414 r100_irq_set(rdev); 420 r100_irq_set(rdev);
415 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 421 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -516,7 +522,7 @@ int rs400_init(struct radeon_device *rdev)
516 /* initialize memory controller */ 522 /* initialize memory controller */
517 rs400_mc_init(rdev); 523 rs400_mc_init(rdev);
518 /* Fence driver */ 524 /* Fence driver */
519 r = radeon_fence_driver_init(rdev, 1); 525 r = radeon_fence_driver_init(rdev);
520 if (r) 526 if (r)
521 return r; 527 return r;
522 r = radeon_irq_kms_init(rdev); 528 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 1c9ab9409531..3fe384741fc0 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -849,6 +849,12 @@ static int rs600_startup(struct radeon_device *rdev)
849 if (r) 849 if (r)
850 return r; 850 return r;
851 851
852 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
853 if (r) {
854 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
855 return r;
856 }
857
852 /* Enable IRQ */ 858 /* Enable IRQ */
853 rs600_irq_set(rdev); 859 rs600_irq_set(rdev);
854 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 860 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -962,7 +968,7 @@ int rs600_init(struct radeon_device *rdev)
962 rs600_mc_init(rdev); 968 rs600_mc_init(rdev);
963 rs600_debugfs(rdev); 969 rs600_debugfs(rdev);
964 /* Fence driver */ 970 /* Fence driver */
965 r = radeon_fence_driver_init(rdev, 1); 971 r = radeon_fence_driver_init(rdev);
966 if (r) 972 if (r)
967 return r; 973 return r;
968 r = radeon_irq_kms_init(rdev); 974 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 8aa5e7ef2efc..ae941d196d3f 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -621,6 +621,12 @@ static int rs690_startup(struct radeon_device *rdev)
621 if (r) 621 if (r)
622 return r; 622 return r;
623 623
624 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
625 if (r) {
626 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
627 return r;
628 }
629
624 /* Enable IRQ */ 630 /* Enable IRQ */
625 rs600_irq_set(rdev); 631 rs600_irq_set(rdev);
626 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 632 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -735,7 +741,7 @@ int rs690_init(struct radeon_device *rdev)
735 rs690_mc_init(rdev); 741 rs690_mc_init(rdev);
736 rv515_debugfs(rdev); 742 rv515_debugfs(rdev);
737 /* Fence driver */ 743 /* Fence driver */
738 r = radeon_fence_driver_init(rdev, 1); 744 r = radeon_fence_driver_init(rdev);
739 if (r) 745 if (r)
740 return r; 746 return r;
741 r = radeon_irq_kms_init(rdev); 747 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index beed57c7df96..21d90d9fe11c 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -393,6 +393,12 @@ static int rv515_startup(struct radeon_device *rdev)
393 if (r) 393 if (r)
394 return r; 394 return r;
395 395
396 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
397 if (r) {
398 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
399 return r;
400 }
401
396 /* Enable IRQ */ 402 /* Enable IRQ */
397 rs600_irq_set(rdev); 403 rs600_irq_set(rdev);
398 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); 404 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
@@ -511,7 +517,7 @@ int rv515_init(struct radeon_device *rdev)
511 rv515_mc_init(rdev); 517 rv515_mc_init(rdev);
512 rv515_debugfs(rdev); 518 rv515_debugfs(rdev);
513 /* Fence driver */ 519 /* Fence driver */
514 r = radeon_fence_driver_init(rdev, 1); 520 r = radeon_fence_driver_init(rdev);
515 if (r) 521 if (r)
516 return r; 522 return r;
517 r = radeon_irq_kms_init(rdev); 523 r = radeon_irq_kms_init(rdev);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index f01603d522bb..0a1283d24027 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -1083,6 +1083,12 @@ static int rv770_startup(struct radeon_device *rdev)
1083 if (r) 1083 if (r)
1084 return r; 1084 return r;
1085 1085
1086 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1087 if (r) {
1088 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1089 return r;
1090 }
1091
1086 /* Enable IRQ */ 1092 /* Enable IRQ */
1087 r = r600_irq_init(rdev); 1093 r = r600_irq_init(rdev);
1088 if (r) { 1094 if (r) {
@@ -1196,7 +1202,7 @@ int rv770_init(struct radeon_device *rdev)
1196 /* Initialize clocks */ 1202 /* Initialize clocks */
1197 radeon_get_clock_info(rdev->ddev); 1203 radeon_get_clock_info(rdev->ddev);
1198 /* Fence driver */ 1204 /* Fence driver */
1199 r = radeon_fence_driver_init(rdev, 1); 1205 r = radeon_fence_driver_init(rdev);
1200 if (r) 1206 if (r)
1201 return r; 1207 return r;
1202 /* initialize AGP */ 1208 /* initialize AGP */