Merge remote branch 'airlied/drm-fixes' into drm-intel-fixes

33 files changed, 445 insertions, 296 deletions

diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index dcbeb98f195a..f7af91cb273d 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -276,7 +276,7 @@ static bool drm_encoder_crtc_ok(struct drm_encoder *encoder,
         struct drm_crtc *tmp;
         int crtc_mask = 1;
 
-        WARN(!crtc, "checking null crtc?");
+        WARN(!crtc, "checking null crtc?\n");
 
         dev = crtc->dev;
 
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index c1a26217a530..a245d17165ae 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -240,7 +240,7 @@ drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
                         .addr   = DDC_ADDR,
                         .flags  = I2C_M_RD,
                         .len    = len,
-                        .buf    = buf + start,
+                        .buf    = buf,
                 }
         };
 
@@ -253,7 +253,7 @@ drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf,
 static u8 *
 drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 {
-        int i, j = 0;
+        int i, j = 0, valid_extensions = 0;
         u8 *block, *new;
 
         if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
@@ -280,14 +280,28 @@ drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
 
         for (j = 1; j <= block[0x7e]; j++) {
                 for (i = 0; i < 4; i++) {
-                        if (drm_do_probe_ddc_edid(adapter, block, j,
-                                                  EDID_LENGTH))
+                        if (drm_do_probe_ddc_edid(adapter,
+                                  block + (valid_extensions + 1) * EDID_LENGTH,
+                                  j, EDID_LENGTH))
                                 goto out;
-                        if (drm_edid_block_valid(block + j * EDID_LENGTH))
+                        if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH)) {
+                                valid_extensions++;
                                 break;
+                        }
                 }
                 if (i == 4)
-                        goto carp;
+                        dev_warn(connector->dev->dev,
+                         "%s: Ignoring invalid EDID block %d.\n",
+                         drm_get_connector_name(connector), j);
+        }
+
+        if (valid_extensions != block[0x7e]) {
+                block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
+                block[0x7e] = valid_extensions;
+                new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
+                if (!new)
+                        goto out;
+                block = new;
         }
 
         return block;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 951e3d463113..781c26c37b38 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4079,8 +4079,7 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
                         alignment = i915_gem_get_gtt_alignment(obj);
                 if (obj_priv->gtt_offset & (alignment - 1)) {
                         WARN(obj_priv->pin_count,
-                             "bo is already pinned with incorrect alignment:"
-                             " offset=%x, req.alignment=%x\n",
+                             "bo is already pinned with incorrect alignment: offset=%x, req.alignment=%x\n",
                              obj_priv->gtt_offset, alignment);
                         ret = i915_gem_object_unbind(obj);
                         if (ret)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f12a5b3ec050..488c36c8f5e6 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2033,7 +2033,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
         u32 grbm_int_cntl = 0;
 
         if (!rdev->irq.installed) {
-                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                 return -EINVAL;
         }
         /* don't enable anything if the ih is disabled */
@@ -2295,6 +2295,7 @@ restart_ih:
                         case 0: /* D1 vblank */
                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 0);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D1 vblank\n");
@@ -2316,6 +2317,7 @@ restart_ih:
                         case 0: /* D2 vblank */
                                 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 1);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D2 vblank\n");
@@ -2337,6 +2339,7 @@ restart_ih:
                         case 0: /* D3 vblank */
                                 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 2);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D3 vblank\n");
@@ -2358,6 +2361,7 @@ restart_ih:
                         case 0: /* D4 vblank */
                                 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 3);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D4 vblank\n");
@@ -2379,6 +2383,7 @@ restart_ih:
                         case 0: /* D5 vblank */
                                 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 4);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D5 vblank\n");
@@ -2400,6 +2405,7 @@ restart_ih:
                         case 0: /* D6 vblank */
                                 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
                                         drm_handle_vblank(rdev->ddev, 5);
+                                        rdev->pm.vblank_sync = true;
                                         wake_up(&rdev->irq.vblank_queue);
                                         disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
                                         DRM_DEBUG("IH: D6 vblank\n");
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 086b9b0416c4..ac3b6dde23db 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -495,6 +495,7 @@ done:
                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
                 return r;
         }
+        rdev->mc.active_vram_size = rdev->mc.real_vram_size;
         return 0;
 }
 
@@ -502,6 +503,7 @@ void evergreen_blit_fini(struct radeon_device *rdev)
 {
         int r;
 
+        rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
         if (rdev->r600_blit.shader_obj == NULL)
                 return;
         /* If we can't reserve the bo, unref should be enough to destroy
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 6d1540c0bfed..8e10aa9f74b0 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -442,7 +442,7 @@ int r100_pci_gart_init(struct radeon_device *rdev)
         int r;
 
         if (rdev->gart.table.ram.ptr) {
-                WARN(1, "R100 PCI GART already initialized.\n");
+                WARN(1, "R100 PCI GART already initialized\n");
                 return 0;
         }
         /* Initialize common gart structure */
@@ -516,7 +516,7 @@ int r100_irq_set(struct radeon_device *rdev)
         uint32_t tmp = 0;
 
         if (!rdev->irq.installed) {
-                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                 WREG32(R_000040_GEN_INT_CNTL, 0);
                 return -EINVAL;
         }
@@ -3180,6 +3180,8 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
         for (u = 0; u < track->num_texture; u++) {
                 if (!track->textures[u].enabled)
                         continue;
+                if (track->textures[u].lookup_disable)
+                        continue;
                 robj = track->textures[u].robj;
                 if (robj == NULL) {
                         DRM_ERROR("No texture bound to unit %u\n", u);
@@ -3414,6 +3416,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
                 track->textures[i].robj = NULL;
                 /* CS IB emission code makes sure texture unit are disabled */
                 track->textures[i].enabled = false;
+                track->textures[i].lookup_disable = false;
                 track->textures[i].roundup_w = true;
                 track->textures[i].roundup_h = true;
                 if (track->separate_cube)
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index f47cdca1c004..af65600e6564 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -46,6 +46,7 @@ struct r100_cs_track_texture {
         unsigned                height_11;
         bool                    use_pitch;
         bool                    enabled;
+        bool                    lookup_disable;
         bool                    roundup_w;
         bool                    roundup_h;
         unsigned                compress_format;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 0266d72e0a4c..d2408c395619 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -447,6 +447,8 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
                 }
+                if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
+                        track->textures[i].lookup_disable = true;
                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
                 case R200_TXFORMAT_I8:
                 case R200_TXFORMAT_RGB332:
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 34527e600fe9..cde1d3480d93 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -91,7 +91,7 @@ int rv370_pcie_gart_init(struct radeon_device *rdev)
         int r;
 
         if (rdev->gart.table.vram.robj) {
-                WARN(1, "RV370 PCIE GART already initialized.\n");
+                WARN(1, "RV370 PCIE GART already initialized\n");
                 return 0;
         }
         /* Initialize common gart structure */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 33952a12f0a3..0f806cc7dc75 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -97,14 +97,8 @@ u32 rv6xx_get_temp(struct radeon_device *rdev)
 {
         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
                 ASIC_T_SHIFT;
-        u32 actual_temp = 0;
 
-        if ((temp >> 7) & 1)
-                actual_temp = 0;
-        else
-                actual_temp = (temp >> 1) & 0xff;
-
-        return actual_temp * 1000;
+        return temp * 1000;
 }
 
 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
@@ -919,7 +913,7 @@ int r600_pcie_gart_init(struct radeon_device *rdev)
         int r;
 
         if (rdev->gart.table.vram.robj) {
-                WARN(1, "R600 PCIE GART already initialized.\n");
+                WARN(1, "R600 PCIE GART already initialized\n");
                 return 0;
         }
         /* Initialize common gart structure */
@@ -2995,7 +2989,7 @@ int r600_irq_set(struct radeon_device *rdev)
         u32 hdmi1, hdmi2;
 
         if (!rdev->irq.installed) {
-                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                 return -EINVAL;
         }
         /* don't enable anything if the ih is disabled */
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 7b294c127c5f..0f90fc3482ce 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -50,6 +50,7 @@ struct r600_cs_track {
         u32                     nsamples;
         u32                     cb_color_base_last[8];
         struct radeon_bo        *cb_color_bo[8];
+        u64                     cb_color_bo_mc[8];
         u32                     cb_color_bo_offset[8];
         struct radeon_bo        *cb_color_frag_bo[8];
         struct radeon_bo        *cb_color_tile_bo[8];
@@ -67,6 +68,7 @@ struct r600_cs_track {
         u32                     db_depth_size;
         u32                     db_offset;
         struct radeon_bo        *db_bo;
+        u64                     db_bo_mc;
 };
 
 static inline int r600_bpe_from_format(u32 *bpe, u32 format)
@@ -140,6 +142,68 @@ static inline int r600_bpe_from_format(u32 *bpe, u32 format)
         return 0;
 }
 
+struct array_mode_checker {
+        int array_mode;
+        u32 group_size;
+        u32 nbanks;
+        u32 npipes;
+        u32 nsamples;
+        u32 bpe;
+};
+
+/* returns alignment in pixels for pitch/height/depth and bytes for base */
+static inline int r600_get_array_mode_alignment(struct array_mode_checker *values,
+                                                u32 *pitch_align,
+                                                u32 *height_align,
+                                                u32 *depth_align,
+                                                u64 *base_align)
+{
+        u32 tile_width = 8;
+        u32 tile_height = 8;
+        u32 macro_tile_width = values->nbanks;
+        u32 macro_tile_height = values->npipes;
+        u32 tile_bytes = tile_width * tile_height * values->bpe * values->nsamples;
+        u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
+
+        switch (values->array_mode) {
+        case ARRAY_LINEAR_GENERAL:
+                /* technically tile_width/_height for pitch/height */
+                *pitch_align = 1; /* tile_width */
+                *height_align = 1; /* tile_height */
+                *depth_align = 1;
+                *base_align = 1;
+                break;
+        case ARRAY_LINEAR_ALIGNED:
+                *pitch_align = max((u32)64, (u32)(values->group_size / values->bpe));
+                *height_align = tile_height;
+                *depth_align = 1;
+                *base_align = values->group_size;
+                break;
+        case ARRAY_1D_TILED_THIN1:
+                *pitch_align = max((u32)tile_width,
+                                   (u32)(values->group_size /
+                                         (tile_height * values->bpe * values->nsamples)));
+                *height_align = tile_height;
+                *depth_align = 1;
+                *base_align = values->group_size;
+                break;
+        case ARRAY_2D_TILED_THIN1:
+                *pitch_align = max((u32)macro_tile_width,
+                                  (u32)(((values->group_size / tile_height) /
+                                         (values->bpe * values->nsamples)) *
+                                        values->nbanks)) * tile_width;
+                *height_align = macro_tile_height * tile_height;
+                *depth_align = 1;
+                *base_align = max(macro_tile_bytes,
+                                  (*pitch_align) * values->bpe * (*height_align) * values->nsamples);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static void r600_cs_track_init(struct r600_cs_track *track)
 {
         int i;
@@ -153,10 +217,12 @@ static void r600_cs_track_init(struct r600_cs_track *track)
                 track->cb_color_info[i] = 0;
                 track->cb_color_bo[i] = NULL;
                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
+                track->cb_color_bo_mc[i] = 0xFFFFFFFF;
         }
         track->cb_target_mask = 0xFFFFFFFF;
         track->cb_shader_mask = 0xFFFFFFFF;
         track->db_bo = NULL;
+        track->db_bo_mc = 0xFFFFFFFF;
         /* assume the biggest format and that htile is enabled */
         track->db_depth_info = 7 | (1 << 25);
         track->db_depth_view = 0xFFFFC000;
@@ -168,7 +234,10 @@ static void r600_cs_track_init(struct r600_cs_track *track)
 static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 {
         struct r600_cs_track *track = p->track;
-        u32 bpe = 0, pitch, slice_tile_max, size, tmp, height, pitch_align;
+        u32 bpe = 0, slice_tile_max, size, tmp;
+        u32 height, height_align, pitch, pitch_align, depth_align;
+        u64 base_offset, base_align;
+        struct array_mode_checker array_check;
         volatile u32 *ib = p->ib->ptr;
         unsigned array_mode;
 
@@ -183,60 +252,40 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
                         i, track->cb_color_info[i]);
                 return -EINVAL;
         }
-        /* pitch is the number of 8x8 tiles per row */
-        pitch = G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1;
+        /* pitch in pixels */
+        pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
         slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
         slice_tile_max *= 64;
-        height = slice_tile_max / (pitch * 8);
+        height = slice_tile_max / pitch;
         if (height > 8192)
                 height = 8192;
         array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
+
+        base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
+        array_check.array_mode = array_mode;
+        array_check.group_size = track->group_size;
+        array_check.nbanks = track->nbanks;
+        array_check.npipes = track->npipes;
+        array_check.nsamples = track->nsamples;
+        array_check.bpe = bpe;
+        if (r600_get_array_mode_alignment(&array_check,
+                                          &pitch_align, &height_align, &depth_align, &base_align)) {
+                dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
+                         G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
+                         track->cb_color_info[i]);
+                return -EINVAL;
+        }
         switch (array_mode) {
         case V_0280A0_ARRAY_LINEAR_GENERAL:
-                /* technically height & 0x7 */
                 break;
         case V_0280A0_ARRAY_LINEAR_ALIGNED:
-                pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-                                 __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
-                if (!IS_ALIGNED(height, 8)) {
-                        dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
-                                 __func__, __LINE__, height);
-                        return -EINVAL;
-                }
                 break;
         case V_0280A0_ARRAY_1D_TILED_THIN1:
-                pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe * track->nsamples))) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-                                 __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
                 /* avoid breaking userspace */
                 if (height > 7)
                         height &= ~0x7;
-                if (!IS_ALIGNED(height, 8)) {
-                        dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
-                                 __func__, __LINE__, height);
-                        return -EINVAL;
-                }
                 break;
         case V_0280A0_ARRAY_2D_TILED_THIN1:
-                pitch_align = max((u32)track->nbanks,
-                                  (u32)(((track->group_size / 8) / (bpe * track->nsamples)) * track->nbanks)) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
-                                __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
-                if (!IS_ALIGNED((height / 8), track->npipes)) {
-                        dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
-                                 __func__, __LINE__, height);
-                        return -EINVAL;
-                }
                 break;
         default:
                 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
@@ -244,8 +293,24 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
                         track->cb_color_info[i]);
                 return -EINVAL;
         }
+
+        if (!IS_ALIGNED(pitch, pitch_align)) {
+                dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n",
+                         __func__, __LINE__, pitch);
+                return -EINVAL;
+        }
+        if (!IS_ALIGNED(height, height_align)) {
+                dev_warn(p->dev, "%s:%d cb height (%d) invalid\n",
+                         __func__, __LINE__, height);
+                return -EINVAL;
+        }
+        if (!IS_ALIGNED(base_offset, base_align)) {
+                dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
+                return -EINVAL;
+        }
+
         /* check offset */
-        tmp = height * pitch * 8 * bpe;
+        tmp = height * pitch * bpe;
         if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
                 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
                         /* the initial DDX does bad things with the CB size occasionally */
@@ -260,15 +325,11 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
                         return -EINVAL;
                 }
         }
-        if (!IS_ALIGNED(track->cb_color_bo_offset[i], track->group_size)) {
-                dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->cb_color_bo_offset[i]);
-                return -EINVAL;
-        }
         /* limit max tile */
-        tmp = (height * pitch * 8) >> 6;
+        tmp = (height * pitch) >> 6;
         if (tmp < slice_tile_max)
                 slice_tile_max = tmp;
-        tmp = S_028060_PITCH_TILE_MAX(pitch - 1) |
+        tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
                 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
         ib[track->cb_color_size_idx[i]] = tmp;
         return 0;
@@ -310,7 +371,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
         /* Check depth buffer */
         if (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
                 G_028800_Z_ENABLE(track->db_depth_control)) {
-                u32 nviews, bpe, ntiles, pitch, pitch_align, height, size;
+                u32 nviews, bpe, ntiles, size, slice_tile_max;
+                u32 height, height_align, pitch, pitch_align, depth_align;
+                u64 base_offset, base_align;
+                struct array_mode_checker array_check;
+                int array_mode;
+
                 if (track->db_bo == NULL) {
                         dev_warn(p->dev, "z/stencil with no depth buffer\n");
                         return -EINVAL;
@@ -353,39 +419,34 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
                         ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
                 } else {
                         size = radeon_bo_size(track->db_bo);
-                        pitch = G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1;
-                        height = size / (pitch * 8 * bpe);
-                        height &= ~0x7;
-                        if (!height)
-                                height = 8;
-
-                        switch (G_028010_ARRAY_MODE(track->db_depth_info)) {
+                        /* pitch in pixels */
+                        pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
+                        slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
+                        slice_tile_max *= 64;
+                        height = slice_tile_max / pitch;
+                        if (height > 8192)
+                                height = 8192;
+                        base_offset = track->db_bo_mc + track->db_offset;
+                        array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
+                        array_check.array_mode = array_mode;
+                        array_check.group_size = track->group_size;
+                        array_check.nbanks = track->nbanks;
+                        array_check.npipes = track->npipes;
+                        array_check.nsamples = track->nsamples;
+                        array_check.bpe = bpe;
+                        if (r600_get_array_mode_alignment(&array_check,
+                                                          &pitch_align, &height_align, &depth_align, &base_align)) {
+                                dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
+                                         G_028010_ARRAY_MODE(track->db_depth_info),
+                                         track->db_depth_info);
+                                return -EINVAL;
+                        }
+                        switch (array_mode) {
                         case V_028010_ARRAY_1D_TILED_THIN1:
-                                pitch_align = (max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8);
-                                if (!IS_ALIGNED(pitch, pitch_align)) {
-                                        dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
-                                                 __func__, __LINE__, pitch);
-                                        return -EINVAL;
-                                }
-                                if (!IS_ALIGNED(height, 8)) {
-                                        dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
-                                                 __func__, __LINE__, height);
-                                        return -EINVAL;
-                                }
+                                /* don't break userspace */
+                                height &= ~0x7;
                                 break;
                         case V_028010_ARRAY_2D_TILED_THIN1:
-                                pitch_align = max((u32)track->nbanks,
-                                                  (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
-                                if (!IS_ALIGNED(pitch, pitch_align)) {
-                                        dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
-                                                 __func__, __LINE__, pitch);
-                                        return -EINVAL;
-                                }
-                                if (!IS_ALIGNED((height / 8), track->npipes)) {
-                                        dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
-                                                 __func__, __LINE__, height);
-                                        return -EINVAL;
-                                }
                                 break;
                         default:
                                 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
@@ -393,15 +454,27 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
                                          track->db_depth_info);
                                 return -EINVAL;
                         }
-                        if (!IS_ALIGNED(track->db_offset, track->group_size)) {
-                                dev_warn(p->dev, "%s offset[%d] %d not aligned\n", __func__, i, track->db_offset);
+
+                        if (!IS_ALIGNED(pitch, pitch_align)) {
+                                dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n",
+                                         __func__, __LINE__, pitch);
+                                return -EINVAL;
+                        }
+                        if (!IS_ALIGNED(height, height_align)) {
+                                dev_warn(p->dev, "%s:%d db height (%d) invalid\n",
+                                         __func__, __LINE__, height);
                                 return -EINVAL;
                         }
+                        if (!IS_ALIGNED(base_offset, base_align)) {
+                                dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset);
+                                return -EINVAL;
+                        }
+
                         ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
                         nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
                         tmp = ntiles * bpe * 64 * nviews;
                         if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
-                                dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %d have %ld)\n",
+                                dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n",
                                                 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
                                                 radeon_bo_size(track->db_bo));
                                 return -EINVAL;
@@ -952,6 +1025,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                 track->cb_color_base_last[tmp] = ib[idx];
                 track->cb_color_bo[tmp] = reloc->robj;
+                track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
                 break;
         case DB_DEPTH_BASE:
                 r = r600_cs_packet_next_reloc(p, &reloc);
@@ -963,6 +1037,7 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                 track->db_offset = radeon_get_ib_value(p, idx) << 8;
                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                 track->db_bo = reloc->robj;
+                track->db_bo_mc = reloc->lobj.gpu_offset;
                 break;
         case DB_HTILE_DATA_BASE:
         case SQ_PGM_START_FS:
@@ -1084,16 +1159,25 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels
 static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 idx,
                                               struct radeon_bo *texture,
                                               struct radeon_bo *mipmap,
+                                              u64 base_offset,
+                                              u64 mip_offset,
                                               u32 tiling_flags)
 {
         struct r600_cs_track *track = p->track;
         u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0;
-        u32 word0, word1, l0_size, mipmap_size, pitch, pitch_align;
+        u32 word0, word1, l0_size, mipmap_size;
+        u32 height_align, pitch, pitch_align, depth_align;
+        u64 base_align;
+        struct array_mode_checker array_check;
 
         /* on legacy kernel we don't perform advanced check */
         if (p->rdev == NULL)
                 return 0;
 
+        /* convert to bytes */
+        base_offset <<= 8;
+        mip_offset <<= 8;
+
         word0 = radeon_get_ib_value(p, idx + 0);
         if (tiling_flags & RADEON_TILING_MACRO)
                 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
@@ -1126,46 +1210,38 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p,  u32 i
                 return -EINVAL;
         }
 
-        pitch = G_038000_PITCH(word0) + 1;
-        switch (G_038000_TILE_MODE(word0)) {
-        case V_038000_ARRAY_LINEAR_GENERAL:
-                pitch_align = 1;
-                /* XXX check height align */
-                break;
-        case V_038000_ARRAY_LINEAR_ALIGNED:
-                pitch_align = max((u32)64, (u32)(track->group_size / bpe)) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
-                                 __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
-                /* XXX check height align */
-                break;
-        case V_038000_ARRAY_1D_TILED_THIN1:
-                pitch_align = max((u32)8, (u32)(track->group_size / (8 * bpe))) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
-                                 __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
-                /* XXX check height align */
-                break;
-        case V_038000_ARRAY_2D_TILED_THIN1:
-                pitch_align = max((u32)track->nbanks,
-                                  (u32)(((track->group_size / 8) / bpe) * track->nbanks)) / 8;
-                if (!IS_ALIGNED(pitch, pitch_align)) {
-                        dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
-                                __func__, __LINE__, pitch);
-                        return -EINVAL;
-                }
-                /* XXX check height align */
-                break;
-        default:
-                dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
-                         G_038000_TILE_MODE(word0), word0);
+        /* pitch in texels */
+        pitch = (G_038000_PITCH(word0) + 1) * 8;
+        array_check.array_mode = G_038000_TILE_MODE(word0);
+        array_check.group_size = track->group_size;
+        array_check.nbanks = track->nbanks;
+        array_check.npipes = track->npipes;
+        array_check.nsamples = 1;
+        array_check.bpe = bpe;
+        if (r600_get_array_mode_alignment(&array_check,
+                                          &pitch_align, &height_align, &depth_align, &base_align)) {
+                dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
+                         __func__, __LINE__, G_038000_TILE_MODE(word0));
+                return -EINVAL;
+        }
+
+        /* XXX check height as well... */
+
+        if (!IS_ALIGNED(pitch, pitch_align)) {
+                dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n",
+                         __func__, __LINE__, pitch);
+                return -EINVAL;
+        }
+        if (!IS_ALIGNED(base_offset, base_align)) {
+                dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n",
+                         __func__, __LINE__, base_offset);
+                return -EINVAL;
+        }
+        if (!IS_ALIGNED(mip_offset, base_align)) {
+                dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n",
+                         __func__, __LINE__, mip_offset);
                 return -EINVAL;
         }
-        /* XXX check offset align */
 
         word0 = radeon_get_ib_value(p, idx + 4);
         word1 = radeon_get_ib_value(p, idx + 5);
@@ -1400,7 +1476,10 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                                 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
                                 mipmap = reloc->robj;
                                 r = r600_check_texture_resource(p,  idx+(i*7)+1,
-                                                                texture, mipmap, reloc->lobj.tiling_flags);
+                                                                texture, mipmap,
+                                                                base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
+                                                                mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
+                                                                reloc->lobj.tiling_flags);
                                 if (r)
                                         return r;
                                 ib[idx+1+(i*7)+2] += base_offset;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 966a793e225b..bff4dc4f410f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -51,6 +51,12 @@
 #define PTE_READABLE                            (1 << 5)
 #define PTE_WRITEABLE                           (1 << 6)
 
+/* tiling bits */
+#define     ARRAY_LINEAR_GENERAL              0x00000000
+#define     ARRAY_LINEAR_ALIGNED              0x00000001
+#define     ARRAY_1D_TILED_THIN1              0x00000002
+#define     ARRAY_2D_TILED_THIN1              0x00000004
+
 /* Registers */
 #define ARB_POP                                         0x2418
 #define         ENABLE_TC128                                    (1 << 30)
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 04cac7ec9039..87ead090c7d5 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -526,8 +526,6 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
         if (crev < 2)
                 return false;
 
-        router.valid = false;
-
         obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
         path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
             (ctx->bios + data_offset +
@@ -624,6 +622,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                         if (connector_type == DRM_MODE_CONNECTOR_Unknown)
                                 continue;
 
+                        router.ddc_valid = false;
+                        router.cd_valid = false;
                         for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
                                 uint8_t grph_obj_id, grph_obj_num, grph_obj_type;
 
@@ -647,9 +647,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                                                  usDeviceTag));
 
                                 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
-                                        router.valid = false;
                                         for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
-                                                u16 router_obj_id = le16_to_cpu(router_obj->asObjects[j].usObjectID);
+                                                u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
                                                 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
                                                         ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
                                                                 (ctx->bios + data_offset +
@@ -657,6 +656,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                                         ATOM_I2C_RECORD *i2c_record;
                                                         ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
                                                         ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
+                                                        ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
                                                         ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
                                                                 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
                                                                 (ctx->bios + data_offset +
@@ -690,10 +690,18 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
                                                                 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
                                                                         ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
                                                                                 record;
-                                                                        router.valid = true;
-                                                                        router.mux_type = ddc_path->ucMuxType;
-                                                                        router.mux_control_pin = ddc_path->ucMuxControlPin;
-                                                                        router.mux_state = ddc_path->ucMuxState[enum_id];
+                                                                        router.ddc_valid = true;
+                                                                        router.ddc_mux_type = ddc_path->ucMuxType;
+                                                                        router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
+                                                                        router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
+                                                                        break;
+                                                                case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
+                                                                        cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
+                                                                                record;
+                                                                        router.cd_valid = true;
+                                                                        router.cd_mux_type = cd_path->ucMuxType;
+                                                                        router.cd_mux_control_pin = cd_path->ucMuxControlPin;
+                                                                        router.cd_mux_state = cd_path->ucMuxState[enum_id];
                                                                         break;
                                                                 }
                                                                 record = (ATOM_COMMON_RECORD_HEADER *)
@@ -860,7 +868,8 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
         size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
         struct radeon_router router;
 
-        router.valid = false;
+        router.ddc_valid = false;
+        router.cd_valid = false;
 
         bios_connectors = kzalloc(bc_size, GFP_KERNEL);
         if (!bios_connectors)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 4dac4b0a02ee..fe6c74780f18 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -183,13 +183,13 @@ radeon_connector_analog_encoder_conflict_solve(struct drm_connector *connector,
                                         continue;
 
                                 if (priority == true) {
-                                        DRM_INFO("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
-                                        DRM_INFO("in favor of %s\n", drm_get_connector_name(connector));
+                                        DRM_DEBUG_KMS("1: conflicting encoders switching off %s\n", drm_get_connector_name(conflict));
+                                        DRM_DEBUG_KMS("in favor of %s\n", drm_get_connector_name(connector));
                                         conflict->status = connector_status_disconnected;
                                         radeon_connector_update_scratch_regs(conflict, connector_status_disconnected);
                                 } else {
-                                        DRM_INFO("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector));
-                                        DRM_INFO("in favor of %s\n", drm_get_connector_name(conflict));
+                                        DRM_DEBUG_KMS("2: conflicting encoders switching off %s\n", drm_get_connector_name(connector));
+                                        DRM_DEBUG_KMS("in favor of %s\n", drm_get_connector_name(conflict));
                                         current_status = connector_status_disconnected;
                                 }
                                 break;
@@ -432,13 +432,13 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
                             mode->vdisplay == native_mode->vdisplay) {
                                 *native_mode = *mode;
                                 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
-                                DRM_INFO("Determined LVDS native mode details from EDID\n");
+                                DRM_DEBUG_KMS("Determined LVDS native mode details from EDID\n");
                                 break;
                         }
                 }
         }
         if (!native_mode->clock) {
-                DRM_INFO("No LVDS native mode details, disabling RMX\n");
+                DRM_DEBUG_KMS("No LVDS native mode details, disabling RMX\n");
                 radeon_encoder->rmx_type = RMX_OFF;
         }
 }
@@ -1116,7 +1116,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                 radeon_connector->shared_ddc = true;
                                 shared_ddc = true;
                         }
-                        if (radeon_connector->router_bus && router->valid &&
+                        if (radeon_connector->router_bus && router->ddc_valid &&
                             (radeon_connector->router.router_id == router->router_id)) {
                                 radeon_connector->shared_ddc = false;
                                 shared_ddc = false;
@@ -1136,7 +1136,7 @@ radeon_add_atom_connector(struct drm_device *dev,
         radeon_connector->connector_object_id = connector_object_id;
         radeon_connector->hpd = *hpd;
         radeon_connector->router = *router;
-        if (router->valid) {
+        if (router->ddc_valid || router->cd_valid) {
                 radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
                 if (!radeon_connector->router_bus)
                         goto failed;
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 0383631da69c..1df4dc6c063c 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -315,10 +315,14 @@ static void radeon_print_display_setup(struct drm_device *dev)
                                  radeon_connector->ddc_bus->rec.en_data_reg,
                                  radeon_connector->ddc_bus->rec.y_clk_reg,
                                  radeon_connector->ddc_bus->rec.y_data_reg);
-                        if (radeon_connector->router_bus)
+                        if (radeon_connector->router.ddc_valid)
                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
-                                         radeon_connector->router.mux_control_pin,
-                                         radeon_connector->router.mux_state);
+                                         radeon_connector->router.ddc_mux_control_pin,
+                                         radeon_connector->router.ddc_mux_state);
+                        if (radeon_connector->router.cd_valid)
+                                DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
+                                         radeon_connector->router.cd_mux_control_pin,
+                                         radeon_connector->router.cd_mux_state);
                 } else {
                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
@@ -398,8 +402,8 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
         int ret = 0;
 
         /* on hw with routers, select right port */
-        if (radeon_connector->router.valid)
-                radeon_router_select_port(radeon_connector);
+        if (radeon_connector->router.ddc_valid)
+                radeon_router_select_ddc_port(radeon_connector);
 
         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
@@ -432,8 +436,8 @@ static int radeon_ddc_dump(struct drm_connector *connector)
         int ret = 0;
 
         /* on hw with routers, select right port */
-        if (radeon_connector->router.valid)
-                radeon_router_select_port(radeon_connector);
+        if (radeon_connector->router.ddc_valid)
+                radeon_router_select_ddc_port(radeon_connector);
 
         if (!radeon_connector->ddc_bus)
                 return -1;
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index ae58b6849a2e..f678257c42e6 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1520,6 +1520,7 @@ radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connec
 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 {
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 
         if (radeon_encoder->active_device &
             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
@@ -1531,6 +1532,13 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
         radeon_atom_output_lock(encoder, true);
         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 
+        /* select the clock/data port if it uses a router */
+        if (connector) {
+                struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+                if (radeon_connector->router.cd_valid)
+                        radeon_router_select_cd_port(radeon_connector);
+        }
+
         /* this is needed for the pll/ss setup to work correctly in some cases */
         atombios_set_encoder_crtc_source(encoder);
 }
@@ -1547,6 +1555,23 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct radeon_encoder_atom_dig *dig;
+
+        /* check for pre-DCE3 cards with shared encoders;
+         * can't really use the links individually, so don't disable
+         * the encoder if it's in use by another connector
+         */
+        if (!ASIC_IS_DCE3(rdev)) {
+                struct drm_encoder *other_encoder;
+                struct radeon_encoder *other_radeon_encoder;
+
+                list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
+                        other_radeon_encoder = to_radeon_encoder(other_encoder);
+                        if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
+                            drm_helper_encoder_in_use(other_encoder))
+                                goto disable_done;
+                }
+        }
+
         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 
         switch (radeon_encoder->encoder_id) {
@@ -1586,6 +1611,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
                 break;
         }
 
+disable_done:
         if (radeon_encoder_is_digital(encoder)) {
                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
                         r600_hdmi_disable(encoder);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 216392d0353b..daacb281dfaf 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -240,7 +240,8 @@ retry:
                  */
                 if (seq == rdev->fence_drv.last_seq && radeon_gpu_is_lockup(rdev)) {
                         /* good news we believe it's a lockup */
-                        WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", fence->seq, seq);
+                        WARN(1, "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
+                             fence->seq, seq);
                         /* FIXME: what should we do ? marking everyone
                          * as signaled for now
                          */
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 6a13ee38a5b9..0cfbba02c4d0 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -53,8 +53,8 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector)
         };
 
         /* on hw with routers, select right port */
-        if (radeon_connector->router.valid)
-                radeon_router_select_port(radeon_connector);
+        if (radeon_connector->router.ddc_valid)
+                radeon_router_select_ddc_port(radeon_connector);
 
         ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2);
         if (ret == 2)
@@ -1084,26 +1084,51 @@ void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
                           addr, val);
 }
 
-/* router switching */
-void radeon_router_select_port(struct radeon_connector *radeon_connector)
+/* ddc router switching */
+void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
 {
         u8 val;
 
-        if (!radeon_connector->router.valid)
+        if (!radeon_connector->router.ddc_valid)
                 return;
 
         radeon_i2c_get_byte(radeon_connector->router_bus,
                             radeon_connector->router.i2c_addr,
                             0x3, &val);
-        val &= radeon_connector->router.mux_control_pin;
+        val &= ~radeon_connector->router.ddc_mux_control_pin;
         radeon_i2c_put_byte(radeon_connector->router_bus,
                             radeon_connector->router.i2c_addr,
                             0x3, val);
         radeon_i2c_get_byte(radeon_connector->router_bus,
                             radeon_connector->router.i2c_addr,
                             0x1, &val);
-        val &= radeon_connector->router.mux_control_pin;
-        val |= radeon_connector->router.mux_state;
+        val &= ~radeon_connector->router.ddc_mux_control_pin;
+        val |= radeon_connector->router.ddc_mux_state;
+        radeon_i2c_put_byte(radeon_connector->router_bus,
+                            radeon_connector->router.i2c_addr,
+                            0x1, val);
+}
+
+/* clock/data router switching */
+void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
+{
+        u8 val;
+
+        if (!radeon_connector->router.cd_valid)
+                return;
+
+        radeon_i2c_get_byte(radeon_connector->router_bus,
+                            radeon_connector->router.i2c_addr,
+                            0x3, &val);
+        val &= ~radeon_connector->router.cd_mux_control_pin;
+        radeon_i2c_put_byte(radeon_connector->router_bus,
+                            radeon_connector->router.i2c_addr,
+                            0x3, val);
+        radeon_i2c_get_byte(radeon_connector->router_bus,
+                            radeon_connector->router.i2c_addr,
+                            0x1, &val);
+        val &= ~radeon_connector->router.cd_mux_control_pin;
+        val |= radeon_connector->router.cd_mux_state;
         radeon_i2c_put_byte(radeon_connector->router_bus,
                             radeon_connector->router.i2c_addr,
                             0x1, val);
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index 2f349a300195..465746bd51b7 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -76,7 +76,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
                 default:
                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
                                   crtc);
-                        return EINVAL;
+                        return -EINVAL;
                 }
         } else {
                 switch (crtc) {
@@ -89,7 +89,7 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc)
                 default:
                         DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
                                   crtc);
-                        return EINVAL;
+                        return -EINVAL;
                 }
         }
 
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 92457163d070..680f57644e86 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -401,13 +401,19 @@ struct radeon_hpd {
 };
 
 struct radeon_router {
-        bool valid;
         u32 router_id;
         struct radeon_i2c_bus_rec i2c_info;
         u8 i2c_addr;
-        u8 mux_type;
-        u8 mux_control_pin;
-        u8 mux_state;
+        /* i2c mux */
+        bool ddc_valid;
+        u8 ddc_mux_type;
+        u8 ddc_mux_control_pin;
+        u8 ddc_mux_state;
+        /* clock/data mux */
+        bool cd_valid;
+        u8 cd_mux_type;
+        u8 cd_mux_control_pin;
+        u8 cd_mux_state;
 };
 
 struct radeon_connector {
@@ -488,7 +494,8 @@ extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
                                 u8 slave_addr,
                                 u8 addr,
                                 u8 val);
-extern void radeon_router_select_port(struct radeon_connector *radeon_connector);
+extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
+extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
 extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
 
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d7ab91416410..8eb183466015 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -102,6 +102,8 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
                 type = ttm_bo_type_device;
         }
         *bo_ptr = NULL;
+
+retry:
         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
         if (bo == NULL)
                 return -ENOMEM;
@@ -109,8 +111,6 @@ int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
         bo->gobj = gobj;
         bo->surface_reg = -1;
         INIT_LIST_HEAD(&bo->list);
-
-retry:
         radeon_ttm_placement_from_domain(bo, domain);
         /* Kernel allocation are uninterruptible */
         mutex_lock(&rdev->vram_mutex);
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index c332f46340d5..64928814de53 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -2836,6 +2836,7 @@
 #       define R200_TXFORMAT_ST_ROUTE_STQ5      (5 << 24)
 #       define R200_TXFORMAT_ST_ROUTE_MASK      (7 << 24)
 #       define R200_TXFORMAT_ST_ROUTE_SHIFT     24
+#       define R200_TXFORMAT_LOOKUP_DISABLE     (1 << 27)
 #       define R200_TXFORMAT_ALPHA_MASK_ENABLE  (1 << 28)
 #       define R200_TXFORMAT_CHROMA_KEY_ENABLE  (1 << 29)
 #       define R200_TXFORMAT_CUBIC_MAP_ENABLE           (1 << 30)
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index fe95bb35317e..01c2c736a1da 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -689,7 +689,8 @@ static int radeon_ttm_backend_bind(struct ttm_backend *backend,
         gtt = container_of(backend, struct radeon_ttm_backend, backend);
         gtt->offset = bo_mem->start << PAGE_SHIFT;
         if (!gtt->num_pages) {
-                WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", gtt->num_pages, bo_mem, backend);
+                WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
+                     gtt->num_pages, bo_mem, backend);
         }
         r = radeon_gart_bind(gtt->rdev, gtt->offset,
                              gtt->num_pages, gtt->pages);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index f683e51a2a06..5512e4e5e636 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -78,7 +78,7 @@ int rs400_gart_init(struct radeon_device *rdev)
         int r;
 
         if (rdev->gart.table.ram.ptr) {
-                WARN(1, "RS400 GART already initialized.\n");
+                WARN(1, "RS400 GART already initialized\n");
                 return 0;
         }
         /* Check gart size */
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index b091a1f6fa4e..f1c6e02c2e6b 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -375,7 +375,7 @@ int rs600_gart_init(struct radeon_device *rdev)
         int r;
 
         if (rdev->gart.table.vram.robj) {
-                WARN(1, "RS600 GART already initialized.\n");
+                WARN(1, "RS600 GART already initialized\n");
                 return 0;
         }
         /* Initialize common gart structure */
@@ -505,7 +505,7 @@ int rs600_irq_set(struct radeon_device *rdev)
                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
 
         if (!rdev->irq.installed) {
-                WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
+                WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                 WREG32(R_000040_GEN_INT_CNTL, 0);
                 return -EINVAL;
         }
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index a1cb783c7131..3ca77dc03915 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -27,14 +27,6 @@
 /*
  * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
  */
-/* Notes:
- *
- * We store bo pointer in drm_mm_node struct so we know which bo own a
- * specific node. There is no protection on the pointer, thus to make
- * sure things don't go berserk you have to access this pointer while
- * holding the global lru lock and make sure anytime you free a node you
- * reset the pointer to NULL.
- */
 
 #include "ttm/ttm_module.h"
 #include "ttm/ttm_bo_driver.h"
@@ -45,6 +37,7 @@
 #include <linux/mm.h>
 #include <linux/file.h>
 #include <linux/module.h>
+#include <asm/atomic.h>
 
 #define TTM_ASSERT_LOCKED(param)
 #define TTM_DEBUG(fmt, arg...)
@@ -452,6 +445,11 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo)
         ttm_bo_mem_put(bo, &bo->mem);
 
         atomic_set(&bo->reserved, 0);
+
+        /*
+         * Make processes trying to reserve really pick it up.
+         */
+        smp_mb__after_atomic_dec();
         wake_up_all(&bo->event_queue);
 }
 
@@ -460,7 +458,7 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo)
         struct ttm_bo_device *bdev = bo->bdev;
         struct ttm_bo_global *glob = bo->glob;
         struct ttm_bo_driver *driver;
-        void *sync_obj;
+        void *sync_obj = NULL;
         void *sync_obj_arg;
         int put_count;
         int ret;
@@ -495,17 +493,20 @@ static void ttm_bo_cleanup_refs_or_queue(struct ttm_buffer_object *bo)
                 spin_lock(&glob->lru_lock);
         }
 queue:
-        sync_obj = bo->sync_obj;
-        sync_obj_arg = bo->sync_obj_arg;
         driver = bdev->driver;
+        if (bo->sync_obj)
+                sync_obj = driver->sync_obj_ref(bo->sync_obj);
+        sync_obj_arg = bo->sync_obj_arg;
 
         kref_get(&bo->list_kref);
         list_add_tail(&bo->ddestroy, &bdev->ddestroy);
         spin_unlock(&glob->lru_lock);
         spin_unlock(&bo->lock);
 
-        if (sync_obj)
+        if (sync_obj) {
                 driver->sync_obj_flush(sync_obj, sync_obj_arg);
+                driver->sync_obj_unref(&sync_obj);
+        }
         schedule_delayed_work(&bdev->wq,
                               ((HZ / 100) < 1) ? 1 : HZ / 100);
 }
@@ -822,7 +823,6 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo,
                                         bool no_wait_gpu)
 {
         struct ttm_bo_device *bdev = bo->bdev;
-        struct ttm_bo_global *glob = bdev->glob;
         struct ttm_mem_type_manager *man = &bdev->man[mem_type];
         int ret;
 
@@ -832,12 +832,6 @@ static int ttm_bo_mem_force_space(struct ttm_buffer_object *bo,
                         return ret;
                 if (mem->mm_node)
                         break;
-                spin_lock(&glob->lru_lock);
-                if (list_empty(&man->lru)) {
-                        spin_unlock(&glob->lru_lock);
-                        break;
-                }
-                spin_unlock(&glob->lru_lock);
                 ret = ttm_mem_evict_first(bdev, mem_type, interruptible,
                                                 no_wait_reserve, no_wait_gpu);
                 if (unlikely(ret != 0))
@@ -1125,35 +1119,9 @@ EXPORT_SYMBOL(ttm_bo_validate);
 int ttm_bo_check_placement(struct ttm_buffer_object *bo,
                                 struct ttm_placement *placement)
 {
-        int i;
+        BUG_ON((placement->fpfn || placement->lpfn) &&
+               (bo->mem.num_pages > (placement->lpfn - placement->fpfn)));
 
-        if (placement->fpfn || placement->lpfn) {
-                if (bo->mem.num_pages > (placement->lpfn - placement->fpfn)) {
-                        printk(KERN_ERR TTM_PFX "Page number range to small "
-                                "Need %lu pages, range is [%u, %u]\n",
-                                bo->mem.num_pages, placement->fpfn,
-                                placement->lpfn);
-                        return -EINVAL;
-                }
-        }
-        for (i = 0; i < placement->num_placement; i++) {
-                if (!capable(CAP_SYS_ADMIN)) {
-                        if (placement->placement[i] & TTM_PL_FLAG_NO_EVICT) {
-                                printk(KERN_ERR TTM_PFX "Need to be root to "
-                                        "modify NO_EVICT status.\n");
-                                return -EINVAL;
-                        }
-                }
-        }
-        for (i = 0; i < placement->num_busy_placement; i++) {
-                if (!capable(CAP_SYS_ADMIN)) {
-                        if (placement->busy_placement[i] & TTM_PL_FLAG_NO_EVICT) {
-                                printk(KERN_ERR TTM_PFX "Need to be root to "
-                                        "modify NO_EVICT status.\n");
-                                return -EINVAL;
-                        }
-                }
-        }
         return 0;
 }
 
@@ -1176,6 +1144,10 @@ int ttm_bo_init(struct ttm_bo_device *bdev,
         num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
         if (num_pages == 0) {
                 printk(KERN_ERR TTM_PFX "Illegal buffer object size.\n");
+                if (destroy)
+                        (*destroy)(bo);
+                else
+                        kfree(bo);
                 return -EINVAL;
         }
         bo->destroy = destroy;
@@ -1369,18 +1341,9 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
         int ret = -EINVAL;
         struct ttm_mem_type_manager *man;
 
-        if (type >= TTM_NUM_MEM_TYPES) {
-                printk(KERN_ERR TTM_PFX "Illegal memory type %d\n", type);
-                return ret;
-        }
-
+        BUG_ON(type >= TTM_NUM_MEM_TYPES);
         man = &bdev->man[type];
-        if (man->has_type) {
-                printk(KERN_ERR TTM_PFX
-                       "Memory manager already initialized for type %d\n",
-                       type);
-                return ret;
-        }
+        BUG_ON(man->has_type);
 
         ret = bdev->driver->init_mem_type(bdev, type, man);
         if (ret)
@@ -1389,13 +1352,6 @@ int ttm_bo_init_mm(struct ttm_bo_device *bdev, unsigned type,
 
         ret = 0;
         if (type != TTM_PL_SYSTEM) {
-                if (!p_size) {
-                        printk(KERN_ERR TTM_PFX
-                               "Zero size memory manager type %d\n",
-                               type);
-                        return ret;
-                }
-
                 ret = (*man->func->init)(man, p_size);
                 if (ret)
                         return ret;
diff --git a/drivers/gpu/drm/ttm/ttm_bo_manager.c b/drivers/gpu/drm/ttm/ttm_bo_manager.c
index 7410c190c891..038e947d00f9 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_manager.c
@@ -1,6 +1,6 @@
 /**************************************************************************
  *
- * Copyright (c) 2007-2009 VMware, Inc., Palo Alto, CA., USA
+ * Copyright (c) 2007-2010 VMware, Inc., Palo Alto, CA., USA
  * All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -31,20 +31,29 @@
 #include "ttm/ttm_module.h"
 #include "ttm/ttm_bo_driver.h"
 #include "ttm/ttm_placement.h"
-#include <linux/jiffies.h>
+#include "drm_mm.h"
 #include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/file.h>
+#include <linux/spinlock.h>
 #include <linux/module.h>
 
+/**
+ * Currently we use a spinlock for the lock, but a mutex *may* be
+ * more appropriate to reduce scheduling latency if the range manager
+ * ends up with very fragmented allocation patterns.
+ */
+
+struct ttm_range_manager {
+        struct drm_mm mm;
+        spinlock_t lock;
+};
+
 static int ttm_bo_man_get_node(struct ttm_mem_type_manager *man,
                                struct ttm_buffer_object *bo,
                                struct ttm_placement *placement,
                                struct ttm_mem_reg *mem)
 {
-        struct ttm_bo_global *glob = man->bdev->glob;
-        struct drm_mm *mm = man->priv;
+        struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv;
+        struct drm_mm *mm = &rman->mm;
         struct drm_mm_node *node = NULL;
         unsigned long lpfn;
         int ret;
@@ -57,19 +66,19 @@ static int ttm_bo_man_get_node(struct ttm_mem_type_manager *man,
                 if (unlikely(ret))
                         return ret;
 
-                spin_lock(&glob->lru_lock);
+                spin_lock(&rman->lock);
                 node = drm_mm_search_free_in_range(mm,
                                         mem->num_pages, mem->page_alignment,
                                         placement->fpfn, lpfn, 1);
                 if (unlikely(node == NULL)) {
-                        spin_unlock(&glob->lru_lock);
+                        spin_unlock(&rman->lock);
                         return 0;
                 }
                 node = drm_mm_get_block_atomic_range(node, mem->num_pages,
-                                                        mem->page_alignment,
-                                                        placement->fpfn,
-                                                        lpfn);
-                spin_unlock(&glob->lru_lock);
+                                                     mem->page_alignment,
+                                                     placement->fpfn,
+                                                     lpfn);
+                spin_unlock(&rman->lock);
         } while (node == NULL);
 
         mem->mm_node = node;
@@ -80,12 +89,12 @@ static int ttm_bo_man_get_node(struct ttm_mem_type_manager *man,
 static void ttm_bo_man_put_node(struct ttm_mem_type_manager *man,
                                 struct ttm_mem_reg *mem)
 {
-        struct ttm_bo_global *glob = man->bdev->glob;
+        struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv;
 
         if (mem->mm_node) {
-                spin_lock(&glob->lru_lock);
+                spin_lock(&rman->lock);
                 drm_mm_put_block(mem->mm_node);
-                spin_unlock(&glob->lru_lock);
+                spin_unlock(&rman->lock);
                 mem->mm_node = NULL;
         }
 }
@@ -93,49 +102,49 @@ static void ttm_bo_man_put_node(struct ttm_mem_type_manager *man,
 static int ttm_bo_man_init(struct ttm_mem_type_manager *man,
                            unsigned long p_size)
 {
-        struct drm_mm *mm;
+        struct ttm_range_manager *rman;
         int ret;
 
-        mm = kzalloc(sizeof(*mm), GFP_KERNEL);
-        if (!mm)
+        rman = kzalloc(sizeof(*rman), GFP_KERNEL);
+        if (!rman)
                 return -ENOMEM;
 
-        ret = drm_mm_init(mm, 0, p_size);
+        ret = drm_mm_init(&rman->mm, 0, p_size);
         if (ret) {
-                kfree(mm);
+                kfree(rman);
                 return ret;
         }
 
-        man->priv = mm;
+        spin_lock_init(&rman->lock);
+        man->priv = rman;
         return 0;
 }
 
 static int ttm_bo_man_takedown(struct ttm_mem_type_manager *man)
 {
-        struct ttm_bo_global *glob = man->bdev->glob;
-        struct drm_mm *mm = man->priv;
-        int ret = 0;
+        struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv;
+        struct drm_mm *mm = &rman->mm;
 
-        spin_lock(&glob->lru_lock);
+        spin_lock(&rman->lock);
         if (drm_mm_clean(mm)) {
                 drm_mm_takedown(mm);
-                kfree(mm);
+                spin_unlock(&rman->lock);
+                kfree(rman);
                 man->priv = NULL;
-        } else
-                ret = -EBUSY;
-        spin_unlock(&glob->lru_lock);
-        return ret;
+                return 0;
+        }
+        spin_unlock(&rman->lock);
+        return -EBUSY;
 }
 
 static void ttm_bo_man_debug(struct ttm_mem_type_manager *man,
                              const char *prefix)
 {
-        struct ttm_bo_global *glob = man->bdev->glob;
-        struct drm_mm *mm = man->priv;
+        struct ttm_range_manager *rman = (struct ttm_range_manager *) man->priv;
 
-        spin_lock(&glob->lru_lock);
-        drm_mm_debug_table(mm, prefix);
-        spin_unlock(&glob->lru_lock);
+        spin_lock(&rman->lock);
+        drm_mm_debug_table(&rman->mm, prefix);
+        spin_unlock(&rman->lock);
 }
 
 const struct ttm_mem_type_manager_func ttm_bo_manager_func = {
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index a7bab87a548b..af789dc869b9 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -440,10 +440,8 @@ int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem)
                 return ret;
 
         ret = be->func->bind(be, bo_mem);
-        if (ret) {
-                printk(KERN_ERR TTM_PFX "Couldn't bind backend.\n");
+        if (unlikely(ret != 0))
                 return ret;
-        }
 
         ttm->state = tt_bound;
 
diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c
index 9b5b4d9dd62c..3e038a394c51 100644
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ b/drivers/gpu/drm/via/via_dmablit.c
@@ -235,9 +235,9 @@ via_lock_all_dma_pages(drm_via_sg_info_t *vsg,  drm_via_dmablit_t *xfer)
         vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride - 1)) -
                 first_pfn + 1;
 
-        if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages)))
+        vsg->pages = vzalloc(sizeof(struct page *) * vsg->num_pages);
+        if (NULL == vsg->pages)
                 return -ENOMEM;
-        memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
         down_read(&current->mm->mmap_sem);
         ret = get_user_pages(current, current->mm,
                              (unsigned long)xfer->mem_addr,
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 51d9f9f1d7f2..76954e3528c1 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -691,6 +691,7 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data,
 
         fence_rep.error = ret;
         fence_rep.fence_seq = (uint64_t) sequence;
+        fence_rep.pad64 = 0;
 
         user_fence_rep = (struct drm_vmw_fence_rep __user *)
             (unsigned long)arg->fence_rep;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index 87c6e6156d7d..cceeb42789b6 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -720,6 +720,8 @@ static int vmw_surface_dmabuf_pin(struct vmw_framebuffer *vfb)
                                &vmw_vram_ne_placement,
                                false, &vmw_dmabuf_bo_free);
         vmw_overlay_resume_all(dev_priv);
+        if (unlikely(ret != 0))
+                vfbs->buffer = NULL;
 
         return ret;
 }
@@ -730,6 +732,9 @@ static int vmw_surface_dmabuf_unpin(struct vmw_framebuffer *vfb)
         struct vmw_framebuffer_surface *vfbs =
                 vmw_framebuffer_to_vfbs(&vfb->base);
 
+        if (unlikely(vfbs->buffer == NULL))
+                return 0;
+
         bo = &vfbs->buffer->base;
         ttm_bo_unref(&bo);
         vfbs->buffer = NULL;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
index a01c47ddb5bc..29113c9b26a8 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c
@@ -557,7 +557,7 @@ int vmw_kms_init_legacy_display_system(struct vmw_private *dev_priv)
                 return -EINVAL;
         }
 
-        dev_priv->ldu_priv = kmalloc(GFP_KERNEL, sizeof(*dev_priv->ldu_priv));
+        dev_priv->ldu_priv = kmalloc(sizeof(*dev_priv->ldu_priv), GFP_KERNEL);
 
         if (!dev_priv->ldu_priv)
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
index df2036ed18d5..f1a52f9e7298 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_overlay.c
@@ -585,7 +585,7 @@ int vmw_overlay_init(struct vmw_private *dev_priv)
                 return -ENOSYS;
         }
 
-        overlay = kmalloc(GFP_KERNEL, sizeof(*overlay));
+        overlay = kmalloc(sizeof(*overlay), GFP_KERNEL);
         if (!overlay)
                 return -ENOMEM;