diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-11-28 10:29:57 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-12-12 09:58:09 -0500 |
commit | 159f98750e413f5d6e63d1131417c5310ea175fb (patch) | |
tree | dc518390d3aecfe930792430837fb2cda02011b7 /drivers/gpu/drm | |
parent | 42a430f51c7500be41ca4cbd5b3de930853bd5ee (diff) |
drm/i915: FBC_CONTROL2 is gen4 only
Gen2 and gen3 don't have the FBC_CONTROL2 register, so don't
touch it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 599d445f7ce9..d7cb6bf5712d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -98,7 +98,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
98 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | 98 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99 | int cfb_pitch; | 99 | int cfb_pitch; |
100 | int plane, i; | 100 | int plane, i; |
101 | u32 fbc_ctl, fbc_ctl2; | 101 | u32 fbc_ctl; |
102 | 102 | ||
103 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; | 103 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
104 | if (fb->pitches[0] < cfb_pitch) | 104 | if (fb->pitches[0] < cfb_pitch) |
@@ -115,11 +115,15 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |||
115 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | 115 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
116 | I915_WRITE(FBC_TAG + (i * 4), 0); | 116 | I915_WRITE(FBC_TAG + (i * 4), 0); |
117 | 117 | ||
118 | /* Set it up... */ | 118 | if (IS_GEN4(dev)) { |
119 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | 119 | u32 fbc_ctl2; |
120 | fbc_ctl2 |= plane; | 120 | |
121 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | 121 | /* Set it up... */ |
122 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | 122 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
123 | fbc_ctl2 |= plane; | ||
124 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | ||
125 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | ||
126 | } | ||
123 | 127 | ||
124 | /* enable it... */ | 128 | /* enable it... */ |
125 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | 129 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; |