diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-01-11 02:22:33 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-01-16 20:28:43 -0500 |
commit | 1380da4979728bdd6af0086a8c8e186da14ae673 (patch) | |
tree | f8d9b0e227c0d539f760ad5d8e353206c0bb0c9b /drivers/gpu/drm | |
parent | c693931d93facab671bafdcebf515520663c22fc (diff) |
drm/nv40: initialise 0x17xx on all chipsets that have it
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv40_mc.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_mc.c b/drivers/gpu/drm/nouveau/nv40_mc.c index e4e72c12ab6a..03c0d4c3f355 100644 --- a/drivers/gpu/drm/nouveau/nv40_mc.c +++ b/drivers/gpu/drm/nouveau/nv40_mc.c | |||
@@ -6,27 +6,17 @@ | |||
6 | int | 6 | int |
7 | nv40_mc_init(struct drm_device *dev) | 7 | nv40_mc_init(struct drm_device *dev) |
8 | { | 8 | { |
9 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
10 | uint32_t tmp; | ||
11 | |||
12 | /* Power up everything, resetting each individual unit will | 9 | /* Power up everything, resetting each individual unit will |
13 | * be done later if needed. | 10 | * be done later if needed. |
14 | */ | 11 | */ |
15 | nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); | 12 | nv_wr32(dev, NV03_PMC_ENABLE, 0xFFFFFFFF); |
16 | 13 | ||
17 | switch (dev_priv->chipset) { | 14 | if (nv44_graph_class(dev)) { |
18 | case 0x44: | 15 | u32 tmp = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
19 | case 0x46: /* G72 */ | ||
20 | case 0x4e: | ||
21 | case 0x4c: /* C51_G7X */ | ||
22 | tmp = nv_rd32(dev, NV04_PFB_FIFO_DATA); | ||
23 | nv_wr32(dev, NV40_PMC_1700, tmp); | 16 | nv_wr32(dev, NV40_PMC_1700, tmp); |
24 | nv_wr32(dev, NV40_PMC_1704, 0); | 17 | nv_wr32(dev, NV40_PMC_1704, 0); |
25 | nv_wr32(dev, NV40_PMC_1708, 0); | 18 | nv_wr32(dev, NV40_PMC_1708, 0); |
26 | nv_wr32(dev, NV40_PMC_170C, tmp); | 19 | nv_wr32(dev, NV40_PMC_170C, tmp); |
27 | break; | ||
28 | default: | ||
29 | break; | ||
30 | } | 20 | } |
31 | 21 | ||
32 | return 0; | 22 | return 0; |