drm/nvf0/gr: fix ddx shaders locking up on me

This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

3 files changed, 54 insertions, 3 deletions

diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
index 51fb2687b570..261a600c8ffb 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c
@@ -804,7 +804,7 @@ nve4_grctx_init_unk[] = {
         {}
 };
 
-void
+static void
 nve4_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
 {
         u32 magic[GPC_MAX][2];
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
index c41a6f07e958..c1bacc3d7374 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c
@@ -221,6 +221,58 @@ nvf0_grctx_init_unk[] = {
         {}
 };
 
+static void
+nvf0_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
+{
+        u32 magic[GPC_MAX][4];
+        u32 offset;
+        int gpc;
+
+        mmio_data(0x003000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x008000, 0x0100, NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS);
+        mmio_data(0x060000, 0x1000, NV_MEM_ACCESS_RW);
+        mmio_list(0x40800c, 0x00000000,  8, 1);
+        mmio_list(0x408010, 0x80000000,  0, 0);
+        mmio_list(0x419004, 0x00000000,  8, 1);
+        mmio_list(0x419008, 0x00000000,  0, 0);
+        mmio_list(0x4064cc, 0x80000000,  0, 0);
+        mmio_list(0x408004, 0x00000000,  8, 0);
+        mmio_list(0x408008, 0x80000030,  0, 0);
+        mmio_list(0x418808, 0x00000000,  8, 0);
+        mmio_list(0x41880c, 0x80000030,  0, 0);
+        mmio_list(0x4064c8, 0x01800600,  0, 0);
+        mmio_list(0x418810, 0x80000000, 12, 2);
+        mmio_list(0x419848, 0x10000000, 12, 2);
+
+        mmio_list(0x405830, 0x02180648,  0, 0);
+        mmio_list(0x4064c4, 0x0192ffff,  0, 0);
+
+        for (gpc = 0, offset = 0; gpc < priv->gpc_nr; gpc++) {
+                u16 magic0 = 0x0218 * (priv->tpc_nr[gpc] - 1);
+                u16 magic1 = 0x0648 * (priv->tpc_nr[gpc] - 1);
+                u16 magic2 = 0x0218;
+                u16 magic3 = 0x0648;
+                magic[gpc][0]  = 0x10000000 | (magic0 << 16) | offset;
+                magic[gpc][1]  = 0x00000000 | (magic1 << 16);
+                offset += 0x0324 * (priv->tpc_nr[gpc] - 1);;
+                magic[gpc][2]  = 0x10000000 | (magic2 << 16) | offset;
+                magic[gpc][3]  = 0x00000000 | (magic3 << 16);
+                offset += 0x0324;
+        }
+
+        for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+                mmio_list(GPC_UNIT(gpc, 0x30c0), magic[gpc][0], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x30e4), magic[gpc][1] | offset, 0, 0);
+                offset += 0x07ff * (priv->tpc_nr[gpc] - 1);
+                mmio_list(GPC_UNIT(gpc, 0x32c0), magic[gpc][2], 0, 0);
+                mmio_list(GPC_UNIT(gpc, 0x32e4), magic[gpc][3] | offset, 0, 0);
+                offset += 0x07ff;
+        }
+
+        mmio_list(0x17e91c, 0x06060609, 0, 0);
+        mmio_list(0x17e920, 0x00090a05, 0, 0);
+}
+
 static struct nvc0_graph_init *
 nvf0_grctx_init_hub[] = {
         nvc0_grctx_init_base,
@@ -267,7 +319,7 @@ nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
                 .wr32 = _nouveau_graph_context_wr32,
         },
         .main = nve4_grctx_generate_main,
-        .mods = nve4_grctx_generate_mods,
+        .mods = nvf0_grctx_generate_mods,
         .hub  = nvf0_grctx_init_hub,
         .gpc  = nvf0_grctx_init_gpc,
         .icmd = nvc0_grctx_init_icmd,
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
index 0180f05f40c3..dd06674336b4 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
@@ -254,7 +254,6 @@ extern struct nvc0_graph_init nvd9_grctx_init_rop[];
 extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
 
 void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
 extern struct nouveau_oclass *nve4_grctx_oclass;
 extern struct nvc0_graph_init nve4_grctx_init_unk46xx[];
 extern struct nvc0_graph_init nve4_grctx_init_unk47xx[];