diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-29 23:49:12 -0500 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-29 23:49:12 -0500 |
commit | 9b0cd304f26b9fca140de15deeac2bf357d1f388 (patch) | |
tree | 03a0d74614865a5b776b2a98a433232013b1d369 /drivers/gpu/drm/vmwgfx/svga_reg.h | |
parent | ca2a650f3dfdc30d71d21bcbb04d2d057779f3f9 (diff) | |
parent | ef64cf9d06049e4e9df661f3be60b217e476bee1 (diff) |
Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"Been a bit busy, first week of kids school, and waiting on other trees
to go in before I could send this, so its a bit later than I'd
normally like.
Highlights:
- core:
timestamp fixes, lots of misc cleanups
- new drivers:
bochs virtual vga
- vmwgfx:
major overhaul for their nextgen virt gpu.
- i915:
runtime D3 on HSW, watermark fixes, power well work, fbc fixes,
bdw is no longer prelim.
- nouveau:
gk110/208 acceleration, more pm groundwork, old overlay support
- radeon:
dpm rework and clockgating for CIK, pci config reset, big endian
fixes
- tegra:
panel support and DSI support, build as module, prime.
- armada, omap, gma500, rcar, exynos, mgag200, cirrus, ast:
fixes
- msm:
hdmi support for mdp5"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (595 commits)
drm/nouveau: resume display if any later suspend bits fail
drm/nouveau: fix lock unbalance in nouveau_crtc_page_flip
drm/nouveau: implement hooks for needed for drm vblank timestamping support
drm/nouveau/disp: add a method to fetch info needed by drm vblank timestamping
drm/nv50: fill in crtc mode struct members from crtc_mode_fixup
drm/radeon/dce8: workaround for atom BlankCrtc table
drm/radeon/DCE4+: clear bios scratch dpms bit (v2)
drm/radeon: set si_notify_smc_display_change properly
drm/radeon: fix DAC interrupt handling on DCE5+
drm/radeon: clean up active vram sizing
drm/radeon: skip async dma init on r6xx
drm/radeon/runpm: don't runtime suspend non-PX cards
drm/radeon: add ring to fence trace functions
drm/radeon: add missing trace point
drm/radeon: fix VMID use tracking
drm: ast,cirrus,mgag200: use drm_can_sleep
drm/gma500: Lock struct_mutex around cursor updates
drm/i915: Fix the offset issue for the stolen GEM objects
DRM: armada: fix missing DRM_KMS_FB_HELPER select
drm/i915: Decouple GPU error reporting from ring initialisation
...
Diffstat (limited to 'drivers/gpu/drm/vmwgfx/svga_reg.h')
-rw-r--r-- | drivers/gpu/drm/vmwgfx/svga_reg.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/vmwgfx/svga_reg.h b/drivers/gpu/drm/vmwgfx/svga_reg.h index 01f63cb49678..71defa4d2d75 100644 --- a/drivers/gpu/drm/vmwgfx/svga_reg.h +++ b/drivers/gpu/drm/vmwgfx/svga_reg.h | |||
@@ -169,7 +169,10 @@ enum { | |||
169 | SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ | 169 | SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */ |
170 | SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ | 170 | SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */ |
171 | SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ | 171 | SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */ |
172 | SVGA_REG_TOP = 48, /* Must be 1 more than the last register */ | 172 | SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50, /* Max primary memory */ |
173 | SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */ | ||
174 | SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */ | ||
175 | SVGA_REG_TOP = 53, /* Must be 1 more than the last register */ | ||
173 | 176 | ||
174 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ | 177 | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
175 | /* Next 768 (== 256*3) registers exist for colormap */ | 178 | /* Next 768 (== 256*3) registers exist for colormap */ |
@@ -431,7 +434,10 @@ struct SVGASignedPoint { | |||
431 | #define SVGA_CAP_TRACES 0x00200000 | 434 | #define SVGA_CAP_TRACES 0x00200000 |
432 | #define SVGA_CAP_GMR2 0x00400000 | 435 | #define SVGA_CAP_GMR2 0x00400000 |
433 | #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 | 436 | #define SVGA_CAP_SCREEN_OBJECT_2 0x00800000 |
434 | 437 | #define SVGA_CAP_COMMAND_BUFFERS 0x01000000 | |
438 | #define SVGA_CAP_DEAD1 0x02000000 | ||
439 | #define SVGA_CAP_CMD_BUFFERS_2 0x04000000 | ||
440 | #define SVGA_CAP_GBOBJECTS 0x08000000 | ||
435 | 441 | ||
436 | /* | 442 | /* |
437 | * FIFO register indices. | 443 | * FIFO register indices. |