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authorThierry Reding <treding@nvidia.com>2014-04-16 04:47:36 -0400
committerThierry Reding <treding@nvidia.com>2014-06-05 17:09:25 -0400
commit9cbfc73e1141460243c5b169a36fa41b1582bbbd (patch)
treedc289615fb7ce667094d203bde15b1c0196a8ed4 /drivers/gpu/drm/tegra
parent8c8282c04d6aef91db1729cd5a2ab314598d23ed (diff)
drm/tegra: hdmi - Disable LVDS mode
Disable LVDS mode according to register documentation. It seems like this has no effect on the operation of HDMI, but it's probably a good idea to do this anyway. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c6
-rw-r--r--drivers/gpu/drm/tegra/hdmi.h5
2 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 4116b08acabb..9cba9bf14079 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -846,9 +846,13 @@ static int tegra_output_hdmi_enable(struct tegra_output *output)
846 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0)); 846 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
847 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8)); 847 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
848 848
849 value = 0x1c800; 849 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
850 value &= ~SOR_CSTM_ROTCLK(~0); 850 value &= ~SOR_CSTM_ROTCLK(~0);
851 value |= SOR_CSTM_ROTCLK(2); 851 value |= SOR_CSTM_ROTCLK(2);
852 value |= SOR_CSTM_PLLDIV;
853 value &= ~SOR_CSTM_LVDS_ENABLE;
854 value &= ~SOR_CSTM_MODE_MASK;
855 value |= SOR_CSTM_MODE_TMDS;
852 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM); 856 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
853 857
854 /* start SOR */ 858 /* start SOR */
diff --git a/drivers/gpu/drm/tegra/hdmi.h b/drivers/gpu/drm/tegra/hdmi.h
index 0aebc485f7fa..919a19df4e1b 100644
--- a/drivers/gpu/drm/tegra/hdmi.h
+++ b/drivers/gpu/drm/tegra/hdmi.h
@@ -190,6 +190,11 @@
190 190
191#define HDMI_NV_PDISP_SOR_CSTM 0x5a 191#define HDMI_NV_PDISP_SOR_CSTM 0x5a
192#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24) 192#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
193#define SOR_CSTM_PLLDIV (1 << 21)
194#define SOR_CSTM_LVDS_ENABLE (1 << 16)
195#define SOR_CSTM_MODE_LVDS (0 << 12)
196#define SOR_CSTM_MODE_TMDS (1 << 12)
197#define SOR_CSTM_MODE_MASK (3 << 12)
193 198
194#define HDMI_NV_PDISP_SOR_LVDS 0x5b 199#define HDMI_NV_PDISP_SOR_LVDS 0x5b
195#define HDMI_NV_PDISP_SOR_CRCA 0x5c 200#define HDMI_NV_PDISP_SOR_CRCA 0x5c