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authorThierry Reding <treding@nvidia.com>2014-11-13 08:50:33 -0500
committerThierry Reding <treding@nvidia.com>2014-11-13 10:12:26 -0500
commit3f6b406f7d716310c7a63648bbe6b2a4a30c3077 (patch)
tree9b1b8de4025f7397f9dbaf970ebc4abba57940ce /drivers/gpu/drm/tegra
parent337b443d58e2d7d04d23ed07ff61b1243d5f9f2d (diff)
drm/tegra: dsi: Split out tegra_dsi_set_timeout()
In preparation for adding ganged-mode support, this commit splits out the tegra_dsi_set_timeout() function so that it can be reused for the slave DSI controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r--drivers/gpu/drm/tegra/dsi.c38
1 files changed, 23 insertions, 15 deletions
diff --git a/drivers/gpu/drm/tegra/dsi.c b/drivers/gpu/drm/tegra/dsi.c
index 50684a4aa4f0..46fcf62658cf 100644
--- a/drivers/gpu/drm/tegra/dsi.c
+++ b/drivers/gpu/drm/tegra/dsi.c
@@ -681,15 +681,35 @@ static int tegra_output_dsi_disable(struct tegra_output *output)
681 return 0; 681 return 0;
682} 682}
683 683
684static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
685 unsigned int vrefresh)
686{
687 unsigned int timeout;
688 u32 value;
689
690 /* one frame high-speed transmission timeout */
691 timeout = (bclk / vrefresh) / 512;
692 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
693 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
694
695 /* 2 ms peripheral timeout for panel */
696 timeout = 2 * bclk / 512 * 1000;
697 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
698 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
699
700 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
701 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
702}
703
684static int tegra_output_dsi_setup_clock(struct tegra_output *output, 704static int tegra_output_dsi_setup_clock(struct tegra_output *output,
685 struct clk *clk, unsigned long pclk, 705 struct clk *clk, unsigned long pclk,
686 unsigned int *divp) 706 unsigned int *divp)
687{ 707{
688 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc); 708 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
689 struct drm_display_mode *mode = &dc->base.mode; 709 struct drm_display_mode *mode = &dc->base.mode;
690 unsigned int timeout, mul, div, vrefresh;
691 struct tegra_dsi *dsi = to_dsi(output); 710 struct tegra_dsi *dsi = to_dsi(output);
692 unsigned long bclk, plld, value; 711 unsigned int mul, div, vrefresh;
712 unsigned long bclk, plld;
693 int err; 713 int err;
694 714
695 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); 715 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
@@ -744,19 +764,7 @@ static int tegra_output_dsi_setup_clock(struct tegra_output *output,
744 * XXX: Move the below somewhere else so that we don't need to have 764 * XXX: Move the below somewhere else so that we don't need to have
745 * access to the vrefresh in this function? 765 * access to the vrefresh in this function?
746 */ 766 */
747 767 tegra_dsi_set_timeout(dsi, bclk, vrefresh);
748 /* one frame high-speed transmission timeout */
749 timeout = (bclk / vrefresh) / 512;
750 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
751 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
752
753 /* 2 ms peripheral timeout for panel */
754 timeout = 2 * bclk / 512 * 1000;
755 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
756 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
757
758 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
759 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
760 768
761 return 0; 769 return 0;
762} 770}