diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2014-03-12 11:01:07 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2014-03-12 11:01:07 -0400 |
commit | ffb12cf002edbc5927079f51bebde428d601f723 (patch) | |
tree | 1f04d80df9db8883037d59c81f5836770eecfdc6 /drivers/gpu/drm/radeon | |
parent | 1a75b8e64571a85d5e648cfdf4c40e0d9923abc5 (diff) | |
parent | c1bacbae8192dd2a9ebadd22d793b68054f6c6e5 (diff) |
Merge branch 'irq/for-gpio' into irq/core
Merge the request/release callbacks which are in a separate branch for
consumption by the gpio folks.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'drivers/gpu/drm/radeon')
33 files changed, 133 insertions, 88 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index a9338c85630f..daa4dd375ab1 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -559,7 +559,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
559 | u32 adjusted_clock = mode->clock; | 559 | u32 adjusted_clock = mode->clock; |
560 | int encoder_mode = atombios_get_encoder_mode(encoder); | 560 | int encoder_mode = atombios_get_encoder_mode(encoder); |
561 | u32 dp_clock = mode->clock; | 561 | u32 dp_clock = mode->clock; |
562 | int bpc = radeon_get_monitor_bpc(connector); | 562 | int bpc = radeon_crtc->bpc; |
563 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); | 563 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
564 | 564 | ||
565 | /* reset the pll flags */ | 565 | /* reset the pll flags */ |
@@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1176 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); | 1176 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1177 | 1177 | ||
1178 | /* Set NUM_BANKS. */ | 1178 | /* Set NUM_BANKS. */ |
1179 | if (rdev->family >= CHIP_BONAIRE) { | 1179 | if (rdev->family >= CHIP_TAHITI) { |
1180 | unsigned tileb, index, num_banks, tile_split_bytes; | 1180 | unsigned tileb, index, num_banks, tile_split_bytes; |
1181 | 1181 | ||
1182 | /* Calculate the macrotile mode index. */ | 1182 | /* Calculate the macrotile mode index. */ |
@@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1194 | return -EINVAL; | 1194 | return -EINVAL; |
1195 | } | 1195 | } |
1196 | 1196 | ||
1197 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; | 1197 | if (rdev->family >= CHIP_BONAIRE) |
1198 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; | ||
1199 | else | ||
1200 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; | ||
1198 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); | 1201 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1199 | } else { | 1202 | } else { |
1200 | /* SI and older. */ | 1203 | /* NI and older. */ |
1201 | if (rdev->family >= CHIP_TAHITI) | 1204 | if (rdev->family >= CHIP_CAYMAN) |
1202 | tmp = rdev->config.si.tile_config; | ||
1203 | else if (rdev->family >= CHIP_CAYMAN) | ||
1204 | tmp = rdev->config.cayman.tile_config; | 1205 | tmp = rdev->config.cayman.tile_config; |
1205 | else | 1206 | else |
1206 | tmp = rdev->config.evergreen.tile_config; | 1207 | tmp = rdev->config.evergreen.tile_config; |
@@ -1773,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1773 | return ATOM_PPLL1; | 1774 | return ATOM_PPLL1; |
1774 | DRM_ERROR("unable to allocate a PPLL\n"); | 1775 | DRM_ERROR("unable to allocate a PPLL\n"); |
1775 | return ATOM_PPLL_INVALID; | 1776 | return ATOM_PPLL_INVALID; |
1777 | } else if (ASIC_IS_DCE41(rdev)) { | ||
1778 | /* Don't share PLLs on DCE4.1 chips */ | ||
1779 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | ||
1780 | if (rdev->clock.dp_extclk) | ||
1781 | /* skip PPLL programming if using ext clock */ | ||
1782 | return ATOM_PPLL_INVALID; | ||
1783 | } | ||
1784 | pll_in_use = radeon_get_pll_use_mask(crtc); | ||
1785 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | ||
1786 | return ATOM_PPLL1; | ||
1787 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | ||
1788 | return ATOM_PPLL2; | ||
1789 | DRM_ERROR("unable to allocate a PPLL\n"); | ||
1790 | return ATOM_PPLL_INVALID; | ||
1776 | } else if (ASIC_IS_DCE4(rdev)) { | 1791 | } else if (ASIC_IS_DCE4(rdev)) { |
1777 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, | 1792 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1778 | * depending on the asic: | 1793 | * depending on the asic: |
@@ -1800,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1800 | if (pll != ATOM_PPLL_INVALID) | 1815 | if (pll != ATOM_PPLL_INVALID) |
1801 | return pll; | 1816 | return pll; |
1802 | } | 1817 | } |
1803 | } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ | 1818 | } else { |
1804 | /* use the same PPLL for all monitors with the same clock */ | 1819 | /* use the same PPLL for all monitors with the same clock */ |
1805 | pll = radeon_get_shared_nondp_ppll(crtc); | 1820 | pll = radeon_get_shared_nondp_ppll(crtc); |
1806 | if (pll != ATOM_PPLL_INVALID) | 1821 | if (pll != ATOM_PPLL_INVALID) |
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index a42d61571f49..607dc14d195e 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c | |||
@@ -464,11 +464,12 @@ atombios_tv_setup(struct drm_encoder *encoder, int action) | |||
464 | 464 | ||
465 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) | 465 | static u8 radeon_atom_get_bpc(struct drm_encoder *encoder) |
466 | { | 466 | { |
467 | struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); | ||
468 | int bpc = 8; | 467 | int bpc = 8; |
469 | 468 | ||
470 | if (connector) | 469 | if (encoder->crtc) { |
471 | bpc = radeon_get_monitor_bpc(connector); | 470 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); |
471 | bpc = radeon_crtc->bpc; | ||
472 | } | ||
472 | 473 | ||
473 | switch (bpc) { | 474 | switch (bpc) { |
474 | case 0: | 475 | case 0: |
@@ -1313,7 +1314,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t | |||
1313 | } | 1314 | } |
1314 | if (is_dp) | 1315 | if (is_dp) |
1315 | args.v5.ucLaneNum = dp_lane_count; | 1316 | args.v5.ucLaneNum = dp_lane_count; |
1316 | else if (radeon_encoder->pixel_clock > 165000) | 1317 | else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) |
1317 | args.v5.ucLaneNum = 8; | 1318 | args.v5.ucLaneNum = 8; |
1318 | else | 1319 | else |
1319 | args.v5.ucLaneNum = 4; | 1320 | args.v5.ucLaneNum = 4; |
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index e6419ca7cd37..e22be8458d92 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -3046,7 +3046,7 @@ static u32 cik_create_bitmask(u32 bit_width) | |||
3046 | } | 3046 | } |
3047 | 3047 | ||
3048 | /** | 3048 | /** |
3049 | * cik_select_se_sh - select which SE, SH to address | 3049 | * cik_get_rb_disabled - computes the mask of disabled RBs |
3050 | * | 3050 | * |
3051 | * @rdev: radeon_device pointer | 3051 | * @rdev: radeon_device pointer |
3052 | * @max_rb_num: max RBs (render backends) for the asic | 3052 | * @max_rb_num: max RBs (render backends) for the asic |
@@ -7902,7 +7902,8 @@ int cik_resume(struct radeon_device *rdev) | |||
7902 | /* init golden registers */ | 7902 | /* init golden registers */ |
7903 | cik_init_golden_registers(rdev); | 7903 | cik_init_golden_registers(rdev); |
7904 | 7904 | ||
7905 | radeon_pm_resume(rdev); | 7905 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
7906 | radeon_pm_resume(rdev); | ||
7906 | 7907 | ||
7907 | rdev->accel_working = true; | 7908 | rdev->accel_working = true; |
7908 | r = cik_startup(rdev); | 7909 | r = cik_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c index 713a5d359901..94e858751994 100644 --- a/drivers/gpu/drm/radeon/dce6_afmt.c +++ b/drivers/gpu/drm/radeon/dce6_afmt.c | |||
@@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev) | |||
278 | return !ASIC_IS_NODCE(rdev); | 278 | return !ASIC_IS_NODCE(rdev); |
279 | } | 279 | } |
280 | 280 | ||
281 | static void dce6_audio_enable(struct radeon_device *rdev, | 281 | void dce6_audio_enable(struct radeon_device *rdev, |
282 | struct r600_audio_pin *pin, | 282 | struct r600_audio_pin *pin, |
283 | bool enable) | 283 | bool enable) |
284 | { | 284 | { |
285 | if (!pin) | ||
286 | return; | ||
287 | |||
285 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, | 288 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL, |
286 | AUDIO_ENABLED); | 289 | enable ? AUDIO_ENABLED : 0); |
287 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); | ||
288 | } | 290 | } |
289 | 291 | ||
290 | static const u32 pin_offsets[7] = | 292 | static const u32 pin_offsets[7] = |
@@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev) | |||
323 | rdev->audio.pin[i].connected = false; | 325 | rdev->audio.pin[i].connected = false; |
324 | rdev->audio.pin[i].offset = pin_offsets[i]; | 326 | rdev->audio.pin[i].offset = pin_offsets[i]; |
325 | rdev->audio.pin[i].id = i; | 327 | rdev->audio.pin[i].id = i; |
326 | dce6_audio_enable(rdev, &rdev->audio.pin[i], true); | 328 | /* disable audio. it will be set up later */ |
329 | dce6_audio_enable(rdev, &rdev->audio.pin[i], false); | ||
327 | } | 330 | } |
328 | 331 | ||
329 | return 0; | 332 | return 0; |
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index f2b9e21ce4da..27b0ff16082e 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1680,7 +1680,7 @@ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) | |||
1680 | case RADEON_HPD_6: | 1680 | case RADEON_HPD_6: |
1681 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) | 1681 | if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) |
1682 | connected = true; | 1682 | connected = true; |
1683 | break; | 1683 | break; |
1684 | default: | 1684 | default: |
1685 | break; | 1685 | break; |
1686 | } | 1686 | } |
@@ -5299,7 +5299,8 @@ int evergreen_resume(struct radeon_device *rdev) | |||
5299 | /* init golden registers */ | 5299 | /* init golden registers */ |
5300 | evergreen_init_golden_registers(rdev); | 5300 | evergreen_init_golden_registers(rdev); |
5301 | 5301 | ||
5302 | radeon_pm_resume(rdev); | 5302 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
5303 | radeon_pm_resume(rdev); | ||
5303 | 5304 | ||
5304 | rdev->accel_working = true; | 5305 | rdev->accel_working = true; |
5305 | r = evergreen_startup(rdev); | 5306 | r = evergreen_startup(rdev); |
@@ -5475,9 +5476,9 @@ void evergreen_fini(struct radeon_device *rdev) | |||
5475 | radeon_wb_fini(rdev); | 5476 | radeon_wb_fini(rdev); |
5476 | radeon_ib_pool_fini(rdev); | 5477 | radeon_ib_pool_fini(rdev); |
5477 | radeon_irq_kms_fini(rdev); | 5478 | radeon_irq_kms_fini(rdev); |
5478 | evergreen_pcie_gart_fini(rdev); | ||
5479 | uvd_v1_0_fini(rdev); | 5479 | uvd_v1_0_fini(rdev); |
5480 | radeon_uvd_fini(rdev); | 5480 | radeon_uvd_fini(rdev); |
5481 | evergreen_pcie_gart_fini(rdev); | ||
5481 | r600_vram_scratch_fini(rdev); | 5482 | r600_vram_scratch_fini(rdev); |
5482 | radeon_gem_fini(rdev); | 5483 | radeon_gem_fini(rdev); |
5483 | radeon_fence_driver_fini(rdev); | 5484 | radeon_fence_driver_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index 0c6d5cef4cf1..05b0c95813fd 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
@@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode | |||
306 | return; | 306 | return; |
307 | offset = dig->afmt->offset; | 307 | offset = dig->afmt->offset; |
308 | 308 | ||
309 | /* disable audio prior to setting up hw */ | ||
310 | if (ASIC_IS_DCE6(rdev)) { | ||
311 | dig->afmt->pin = dce6_audio_get_pin(rdev); | ||
312 | dce6_audio_enable(rdev, dig->afmt->pin, false); | ||
313 | } else { | ||
314 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
315 | r600_audio_enable(rdev, dig->afmt->pin, false); | ||
316 | } | ||
317 | |||
309 | evergreen_audio_set_dto(encoder, mode->clock); | 318 | evergreen_audio_set_dto(encoder, mode->clock); |
310 | 319 | ||
311 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, | 320 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, |
@@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode | |||
409 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); | 418 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
410 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); | 419 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
411 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); | 420 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
421 | |||
422 | /* enable audio after to setting up hw */ | ||
423 | if (ASIC_IS_DCE6(rdev)) | ||
424 | dce6_audio_enable(rdev, dig->afmt->pin, true); | ||
425 | else | ||
426 | r600_audio_enable(rdev, dig->afmt->pin, true); | ||
412 | } | 427 | } |
413 | 428 | ||
414 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | 429 | void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) |
415 | { | 430 | { |
416 | struct drm_device *dev = encoder->dev; | ||
417 | struct radeon_device *rdev = dev->dev_private; | ||
418 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); | 431 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
419 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 432 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
420 | 433 | ||
@@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
427 | if (!enable && !dig->afmt->enabled) | 440 | if (!enable && !dig->afmt->enabled) |
428 | return; | 441 | return; |
429 | 442 | ||
430 | if (enable) { | ||
431 | if (ASIC_IS_DCE6(rdev)) | ||
432 | dig->afmt->pin = dce6_audio_get_pin(rdev); | ||
433 | else | ||
434 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
435 | } else { | ||
436 | dig->afmt->pin = NULL; | ||
437 | } | ||
438 | |||
439 | dig->afmt->enabled = enable; | 443 | dig->afmt->enabled = enable; |
440 | 444 | ||
441 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", | 445 | DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", |
diff --git a/drivers/gpu/drm/radeon/evergreen_smc.h b/drivers/gpu/drm/radeon/evergreen_smc.h index 76ada8cfe902..3a03ba37d043 100644 --- a/drivers/gpu/drm/radeon/evergreen_smc.h +++ b/drivers/gpu/drm/radeon/evergreen_smc.h | |||
@@ -57,7 +57,7 @@ typedef struct SMC_Evergreen_MCRegisters SMC_Evergreen_MCRegisters; | |||
57 | 57 | ||
58 | #define EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION 0x100 | 58 | #define EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION 0x100 |
59 | 59 | ||
60 | #define EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters 0x0 | 60 | #define EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters 0x8 |
61 | #define EVERGREEN_SMC_FIRMWARE_HEADER_stateTable 0xC | 61 | #define EVERGREEN_SMC_FIRMWARE_HEADER_stateTable 0xC |
62 | #define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 | 62 | #define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20 |
63 | 63 | ||
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index ea932ac66fc6..bf6300cfd62d 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -2105,7 +2105,8 @@ int cayman_resume(struct radeon_device *rdev) | |||
2105 | /* init golden registers */ | 2105 | /* init golden registers */ |
2106 | ni_init_golden_registers(rdev); | 2106 | ni_init_golden_registers(rdev); |
2107 | 2107 | ||
2108 | radeon_pm_resume(rdev); | 2108 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
2109 | radeon_pm_resume(rdev); | ||
2109 | 2110 | ||
2110 | rdev->accel_working = true; | 2111 | rdev->accel_working = true; |
2111 | r = cayman_startup(rdev); | 2112 | r = cayman_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index 1217fbcbdcca..ca814276b075 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c | |||
@@ -2588,7 +2588,7 @@ static int ni_populate_sq_ramping_values(struct radeon_device *rdev, | |||
2588 | if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) | 2588 | if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) |
2589 | enable_sq_ramping = false; | 2589 | enable_sq_ramping = false; |
2590 | 2590 | ||
2591 | if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) | 2591 | if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) |
2592 | enable_sq_ramping = false; | 2592 | enable_sq_ramping = false; |
2593 | 2593 | ||
2594 | for (i = 0; i < state->performance_level_count; i++) { | 2594 | for (i = 0; i < state->performance_level_count; i++) { |
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c index ef024ce3f7cc..3cc78bb66042 100644 --- a/drivers/gpu/drm/radeon/r100.c +++ b/drivers/gpu/drm/radeon/r100.c | |||
@@ -3942,8 +3942,6 @@ int r100_resume(struct radeon_device *rdev) | |||
3942 | /* Initialize surface registers */ | 3942 | /* Initialize surface registers */ |
3943 | radeon_surface_init(rdev); | 3943 | radeon_surface_init(rdev); |
3944 | 3944 | ||
3945 | radeon_pm_resume(rdev); | ||
3946 | |||
3947 | rdev->accel_working = true; | 3945 | rdev->accel_working = true; |
3948 | r = r100_startup(rdev); | 3946 | r = r100_startup(rdev); |
3949 | if (r) { | 3947 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 7c63ef840e86..0b658b34b33a 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -1430,8 +1430,6 @@ int r300_resume(struct radeon_device *rdev) | |||
1430 | /* Initialize surface registers */ | 1430 | /* Initialize surface registers */ |
1431 | radeon_surface_init(rdev); | 1431 | radeon_surface_init(rdev); |
1432 | 1432 | ||
1433 | radeon_pm_resume(rdev); | ||
1434 | |||
1435 | rdev->accel_working = true; | 1433 | rdev->accel_working = true; |
1436 | r = r300_startup(rdev); | 1434 | r = r300_startup(rdev); |
1437 | if (r) { | 1435 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c index 3768aab2710b..802b19220a21 100644 --- a/drivers/gpu/drm/radeon/r420.c +++ b/drivers/gpu/drm/radeon/r420.c | |||
@@ -325,8 +325,6 @@ int r420_resume(struct radeon_device *rdev) | |||
325 | /* Initialize surface registers */ | 325 | /* Initialize surface registers */ |
326 | radeon_surface_init(rdev); | 326 | radeon_surface_init(rdev); |
327 | 327 | ||
328 | radeon_pm_resume(rdev); | ||
329 | |||
330 | rdev->accel_working = true; | 328 | rdev->accel_working = true; |
331 | r = r420_startup(rdev); | 329 | r = r420_startup(rdev); |
332 | if (r) { | 330 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c index e209eb75024f..98d6053c36c6 100644 --- a/drivers/gpu/drm/radeon/r520.c +++ b/drivers/gpu/drm/radeon/r520.c | |||
@@ -240,8 +240,6 @@ int r520_resume(struct radeon_device *rdev) | |||
240 | /* Initialize surface registers */ | 240 | /* Initialize surface registers */ |
241 | radeon_surface_init(rdev); | 241 | radeon_surface_init(rdev); |
242 | 242 | ||
243 | radeon_pm_resume(rdev); | ||
244 | |||
245 | rdev->accel_working = true; | 243 | rdev->accel_working = true; |
246 | r = r520_startup(rdev); | 244 | r = r520_startup(rdev); |
247 | if (r) { | 245 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index cdbc4171fe73..647ef4079217 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2968,7 +2968,8 @@ int r600_resume(struct radeon_device *rdev) | |||
2968 | /* post card */ | 2968 | /* post card */ |
2969 | atom_asic_init(rdev->mode_info.atom_context); | 2969 | atom_asic_init(rdev->mode_info.atom_context); |
2970 | 2970 | ||
2971 | radeon_pm_resume(rdev); | 2971 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
2972 | radeon_pm_resume(rdev); | ||
2972 | 2973 | ||
2973 | rdev->accel_working = true; | 2974 | rdev->accel_working = true; |
2974 | r = r600_startup(rdev); | 2975 | r = r600_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c index 47fc2b886979..bffac10c4296 100644 --- a/drivers/gpu/drm/radeon/r600_audio.c +++ b/drivers/gpu/drm/radeon/r600_audio.c | |||
@@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work) | |||
142 | } | 142 | } |
143 | 143 | ||
144 | /* enable the audio stream */ | 144 | /* enable the audio stream */ |
145 | static void r600_audio_enable(struct radeon_device *rdev, | 145 | void r600_audio_enable(struct radeon_device *rdev, |
146 | struct r600_audio_pin *pin, | 146 | struct r600_audio_pin *pin, |
147 | bool enable) | 147 | bool enable) |
148 | { | 148 | { |
149 | u32 value = 0; | 149 | u32 value = 0; |
150 | 150 | ||
151 | if (!pin) | ||
152 | return; | ||
153 | |||
151 | if (ASIC_IS_DCE4(rdev)) { | 154 | if (ASIC_IS_DCE4(rdev)) { |
152 | if (enable) { | 155 | if (enable) { |
153 | value |= 0x81000000; /* Required to enable audio */ | 156 | value |= 0x81000000; /* Required to enable audio */ |
@@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev, | |||
158 | WREG32_P(R600_AUDIO_ENABLE, | 161 | WREG32_P(R600_AUDIO_ENABLE, |
159 | enable ? 0x81000000 : 0x0, ~0x81000000); | 162 | enable ? 0x81000000 : 0x0, ~0x81000000); |
160 | } | 163 | } |
161 | DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id); | ||
162 | } | 164 | } |
163 | 165 | ||
164 | /* | 166 | /* |
@@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev) | |||
178 | rdev->audio.pin[0].status_bits = 0; | 180 | rdev->audio.pin[0].status_bits = 0; |
179 | rdev->audio.pin[0].category_code = 0; | 181 | rdev->audio.pin[0].category_code = 0; |
180 | rdev->audio.pin[0].id = 0; | 182 | rdev->audio.pin[0].id = 0; |
181 | 183 | /* disable audio. it will be set up later */ | |
182 | r600_audio_enable(rdev, &rdev->audio.pin[0], true); | 184 | r600_audio_enable(rdev, &rdev->audio.pin[0], false); |
183 | 185 | ||
184 | return 0; | 186 | return 0; |
185 | } | 187 | } |
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c index 3016fc14f502..85a2bb28aed2 100644 --- a/drivers/gpu/drm/radeon/r600_hdmi.c +++ b/drivers/gpu/drm/radeon/r600_hdmi.c | |||
@@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder) | |||
329 | u8 *sadb; | 329 | u8 *sadb; |
330 | int sad_count; | 330 | int sad_count; |
331 | 331 | ||
332 | /* XXX: setting this register causes hangs on some asics */ | ||
333 | return; | ||
334 | |||
335 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { | 332 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
336 | if (connector->encoder == encoder) { | 333 | if (connector->encoder == encoder) { |
337 | radeon_connector = to_radeon_connector(connector); | 334 | radeon_connector = to_radeon_connector(connector); |
@@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod | |||
460 | return; | 457 | return; |
461 | offset = dig->afmt->offset; | 458 | offset = dig->afmt->offset; |
462 | 459 | ||
460 | /* disable audio prior to setting up hw */ | ||
461 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
462 | r600_audio_enable(rdev, dig->afmt->pin, false); | ||
463 | |||
463 | r600_audio_set_dto(encoder, mode->clock); | 464 | r600_audio_set_dto(encoder, mode->clock); |
464 | 465 | ||
465 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, | 466 | WREG32(HDMI0_VBI_PACKET_CONTROL + offset, |
@@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod | |||
531 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); | 532 | WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001); |
532 | 533 | ||
533 | r600_hdmi_audio_workaround(encoder); | 534 | r600_hdmi_audio_workaround(encoder); |
535 | |||
536 | /* enable audio after to setting up hw */ | ||
537 | r600_audio_enable(rdev, dig->afmt->pin, true); | ||
534 | } | 538 | } |
535 | 539 | ||
536 | /* | 540 | /* |
@@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) | |||
651 | if (!enable && !dig->afmt->enabled) | 655 | if (!enable && !dig->afmt->enabled) |
652 | return; | 656 | return; |
653 | 657 | ||
654 | if (enable) | ||
655 | dig->afmt->pin = r600_audio_get_pin(rdev); | ||
656 | else | ||
657 | dig->afmt->pin = NULL; | ||
658 | |||
659 | /* Older chipsets require setting HDMI and routing manually */ | 658 | /* Older chipsets require setting HDMI and routing manually */ |
660 | if (!ASIC_IS_DCE3(rdev)) { | 659 | if (!ASIC_IS_DCE3(rdev)) { |
661 | if (enable) | 660 | if (enable) |
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 4a8ac1cd6b4c..e887d027b6d0 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -135,6 +135,9 @@ extern int radeon_hard_reset; | |||
135 | /* R600+ */ | 135 | /* R600+ */ |
136 | #define R600_RING_TYPE_UVD_INDEX 5 | 136 | #define R600_RING_TYPE_UVD_INDEX 5 |
137 | 137 | ||
138 | /* number of hw syncs before falling back on blocking */ | ||
139 | #define RADEON_NUM_SYNCS 4 | ||
140 | |||
138 | /* hardcode those limit for now */ | 141 | /* hardcode those limit for now */ |
139 | #define RADEON_VA_IB_OFFSET (1 << 20) | 142 | #define RADEON_VA_IB_OFFSET (1 << 20) |
140 | #define RADEON_VA_RESERVED_SIZE (8 << 20) | 143 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
@@ -554,7 +557,6 @@ int radeon_mode_dumb_mmap(struct drm_file *filp, | |||
554 | /* | 557 | /* |
555 | * Semaphores. | 558 | * Semaphores. |
556 | */ | 559 | */ |
557 | /* everything here is constant */ | ||
558 | struct radeon_semaphore { | 560 | struct radeon_semaphore { |
559 | struct radeon_sa_bo *sa_bo; | 561 | struct radeon_sa_bo *sa_bo; |
560 | signed waiters; | 562 | signed waiters; |
@@ -2745,6 +2747,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev, | |||
2745 | void r600_audio_update_hdmi(struct work_struct *work); | 2747 | void r600_audio_update_hdmi(struct work_struct *work); |
2746 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); | 2748 | struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev); |
2747 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); | 2749 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev); |
2750 | void r600_audio_enable(struct radeon_device *rdev, | ||
2751 | struct r600_audio_pin *pin, | ||
2752 | bool enable); | ||
2753 | void dce6_audio_enable(struct radeon_device *rdev, | ||
2754 | struct r600_audio_pin *pin, | ||
2755 | bool enable); | ||
2748 | 2756 | ||
2749 | /* | 2757 | /* |
2750 | * R600 vram scratch functions | 2758 | * R600 vram scratch functions |
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index 485848f889f5..fa9a9c02751e 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c | |||
@@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx) | |||
219 | memcpy(&output, info->buffer.pointer, size); | 219 | memcpy(&output, info->buffer.pointer, size); |
220 | 220 | ||
221 | /* TODO: check version? */ | 221 | /* TODO: check version? */ |
222 | printk("ATPX version %u\n", output.version); | 222 | printk("ATPX version %u, functions 0x%08x\n", |
223 | output.version, output.function_bits); | ||
223 | 224 | ||
224 | radeon_atpx_parse_functions(&atpx->functions, output.function_bits); | 225 | radeon_atpx_parse_functions(&atpx->functions, output.function_bits); |
225 | 226 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index b012cbbc3ed5..044bc98fb459 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
@@ -1521,13 +1521,16 @@ int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) | |||
1521 | if (r) | 1521 | if (r) |
1522 | DRM_ERROR("ib ring test failed (%d).\n", r); | 1522 | DRM_ERROR("ib ring test failed (%d).\n", r); |
1523 | 1523 | ||
1524 | if (rdev->pm.dpm_enabled) { | 1524 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
1525 | /* do dpm late init */ | 1525 | /* do dpm late init */ |
1526 | r = radeon_pm_late_init(rdev); | 1526 | r = radeon_pm_late_init(rdev); |
1527 | if (r) { | 1527 | if (r) { |
1528 | rdev->pm.dpm_enabled = false; | 1528 | rdev->pm.dpm_enabled = false; |
1529 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); | 1529 | DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); |
1530 | } | 1530 | } |
1531 | } else { | ||
1532 | /* resume old pm late */ | ||
1533 | radeon_pm_resume(rdev); | ||
1531 | } | 1534 | } |
1532 | 1535 | ||
1533 | radeon_restore_bios_scratch_regs(rdev); | 1536 | radeon_restore_bios_scratch_regs(rdev); |
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index d680608f6f5b..fbd8b930f2be 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c | |||
@@ -571,6 +571,8 @@ static void radeon_crtc_init(struct drm_device *dev, int index) | |||
571 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; | 571 | radeon_crtc->max_cursor_width = CURSOR_WIDTH; |
572 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; | 572 | radeon_crtc->max_cursor_height = CURSOR_HEIGHT; |
573 | } | 573 | } |
574 | dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; | ||
575 | dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; | ||
574 | 576 | ||
575 | #if 0 | 577 | #if 0 |
576 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; | 578 | radeon_crtc->mode_set.crtc = &radeon_crtc->base; |
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index 114d1672d616..2aecd6dc2610 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c | |||
@@ -537,6 +537,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |||
537 | 537 | ||
538 | radeon_vm_init(rdev, &fpriv->vm); | 538 | radeon_vm_init(rdev, &fpriv->vm); |
539 | 539 | ||
540 | r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false); | ||
541 | if (r) | ||
542 | return r; | ||
543 | |||
540 | /* map the ib pool buffer read only into | 544 | /* map the ib pool buffer read only into |
541 | * virtual address space */ | 545 | * virtual address space */ |
542 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, | 546 | bo_va = radeon_vm_bo_add(rdev, &fpriv->vm, |
@@ -544,6 +548,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) | |||
544 | r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, | 548 | r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET, |
545 | RADEON_VM_PAGE_READABLE | | 549 | RADEON_VM_PAGE_READABLE | |
546 | RADEON_VM_PAGE_SNOOPED); | 550 | RADEON_VM_PAGE_SNOOPED); |
551 | |||
552 | radeon_bo_unreserve(rdev->ring_tmp_bo.bo); | ||
547 | if (r) { | 553 | if (r) { |
548 | radeon_vm_fini(rdev, &fpriv->vm); | 554 | radeon_vm_fini(rdev, &fpriv->vm); |
549 | kfree(fpriv); | 555 | kfree(fpriv); |
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c index 1b783f0e6d3a..15e44a7281ab 100644 --- a/drivers/gpu/drm/radeon/radeon_ring.c +++ b/drivers/gpu/drm/radeon/radeon_ring.c | |||
@@ -139,7 +139,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, | |||
139 | } | 139 | } |
140 | 140 | ||
141 | /* 64 dwords should be enough for fence too */ | 141 | /* 64 dwords should be enough for fence too */ |
142 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_RINGS * 8); | 142 | r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8); |
143 | if (r) { | 143 | if (r) { |
144 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); | 144 | dev_err(rdev->dev, "scheduling IB failed (%d).\n", r); |
145 | return r; | 145 | return r; |
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c index 2b42aa1914f2..9006b32d5eed 100644 --- a/drivers/gpu/drm/radeon/radeon_semaphore.c +++ b/drivers/gpu/drm/radeon/radeon_semaphore.c | |||
@@ -34,14 +34,15 @@ | |||
34 | int radeon_semaphore_create(struct radeon_device *rdev, | 34 | int radeon_semaphore_create(struct radeon_device *rdev, |
35 | struct radeon_semaphore **semaphore) | 35 | struct radeon_semaphore **semaphore) |
36 | { | 36 | { |
37 | uint32_t *cpu_addr; | ||
37 | int i, r; | 38 | int i, r; |
38 | 39 | ||
39 | *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL); | 40 | *semaphore = kmalloc(sizeof(struct radeon_semaphore), GFP_KERNEL); |
40 | if (*semaphore == NULL) { | 41 | if (*semaphore == NULL) { |
41 | return -ENOMEM; | 42 | return -ENOMEM; |
42 | } | 43 | } |
43 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, | 44 | r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &(*semaphore)->sa_bo, |
44 | &(*semaphore)->sa_bo, 8, 8, true); | 45 | 8 * RADEON_NUM_SYNCS, 8, true); |
45 | if (r) { | 46 | if (r) { |
46 | kfree(*semaphore); | 47 | kfree(*semaphore); |
47 | *semaphore = NULL; | 48 | *semaphore = NULL; |
@@ -49,7 +50,10 @@ int radeon_semaphore_create(struct radeon_device *rdev, | |||
49 | } | 50 | } |
50 | (*semaphore)->waiters = 0; | 51 | (*semaphore)->waiters = 0; |
51 | (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); | 52 | (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); |
52 | *((uint64_t*)radeon_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0; | 53 | |
54 | cpu_addr = radeon_sa_bo_cpu_addr((*semaphore)->sa_bo); | ||
55 | for (i = 0; i < RADEON_NUM_SYNCS; ++i) | ||
56 | cpu_addr[i] = 0; | ||
53 | 57 | ||
54 | for (i = 0; i < RADEON_NUM_RINGS; ++i) | 58 | for (i = 0; i < RADEON_NUM_RINGS; ++i) |
55 | (*semaphore)->sync_to[i] = NULL; | 59 | (*semaphore)->sync_to[i] = NULL; |
@@ -125,6 +129,7 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev, | |||
125 | struct radeon_semaphore *semaphore, | 129 | struct radeon_semaphore *semaphore, |
126 | int ring) | 130 | int ring) |
127 | { | 131 | { |
132 | unsigned count = 0; | ||
128 | int i, r; | 133 | int i, r; |
129 | 134 | ||
130 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { | 135 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
@@ -140,6 +145,12 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev, | |||
140 | return -EINVAL; | 145 | return -EINVAL; |
141 | } | 146 | } |
142 | 147 | ||
148 | if (++count > RADEON_NUM_SYNCS) { | ||
149 | /* not enough room, wait manually */ | ||
150 | radeon_fence_wait_locked(fence); | ||
151 | continue; | ||
152 | } | ||
153 | |||
143 | /* allocate enough space for sync command */ | 154 | /* allocate enough space for sync command */ |
144 | r = radeon_ring_alloc(rdev, &rdev->ring[i], 16); | 155 | r = radeon_ring_alloc(rdev, &rdev->ring[i], 16); |
145 | if (r) { | 156 | if (r) { |
@@ -164,6 +175,8 @@ int radeon_semaphore_sync_rings(struct radeon_device *rdev, | |||
164 | 175 | ||
165 | radeon_ring_commit(rdev, &rdev->ring[i]); | 176 | radeon_ring_commit(rdev, &rdev->ring[i]); |
166 | radeon_fence_note_sync(fence, ring); | 177 | radeon_fence_note_sync(fence, ring); |
178 | |||
179 | semaphore->gpu_addr += 8; | ||
167 | } | 180 | } |
168 | 181 | ||
169 | return 0; | 182 | return 0; |
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 77f5b0c3edb8..040a2a10ea17 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c | |||
@@ -714,6 +714,9 @@ int radeon_ttm_init(struct radeon_device *rdev) | |||
714 | DRM_ERROR("Failed initializing VRAM heap.\n"); | 714 | DRM_ERROR("Failed initializing VRAM heap.\n"); |
715 | return r; | 715 | return r; |
716 | } | 716 | } |
717 | /* Change the size here instead of the init above so only lpfn is affected */ | ||
718 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); | ||
719 | |||
717 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, | 720 | r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, |
718 | RADEON_GEM_DOMAIN_VRAM, | 721 | RADEON_GEM_DOMAIN_VRAM, |
719 | NULL, &rdev->stollen_vga_memory); | 722 | NULL, &rdev->stollen_vga_memory); |
@@ -935,7 +938,7 @@ static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, | |||
935 | while (size) { | 938 | while (size) { |
936 | loff_t p = *pos / PAGE_SIZE; | 939 | loff_t p = *pos / PAGE_SIZE; |
937 | unsigned off = *pos & ~PAGE_MASK; | 940 | unsigned off = *pos & ~PAGE_MASK; |
938 | ssize_t cur_size = min(size, PAGE_SIZE - off); | 941 | size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); |
939 | struct page *page; | 942 | struct page *page; |
940 | void *ptr; | 943 | void *ptr; |
941 | 944 | ||
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index 6781fee1eaad..3e6804b2b2ef 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
@@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev) | |||
171 | 171 | ||
172 | radeon_bo_unref(&rdev->uvd.vcpu_bo); | 172 | radeon_bo_unref(&rdev->uvd.vcpu_bo); |
173 | 173 | ||
174 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); | ||
175 | |||
174 | release_firmware(rdev->uvd_fw); | 176 | release_firmware(rdev->uvd_fw); |
175 | } | 177 | } |
176 | 178 | ||
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c index b5c2369cda2f..130d5cc50d43 100644 --- a/drivers/gpu/drm/radeon/rs400.c +++ b/drivers/gpu/drm/radeon/rs400.c | |||
@@ -474,8 +474,6 @@ int rs400_resume(struct radeon_device *rdev) | |||
474 | /* Initialize surface registers */ | 474 | /* Initialize surface registers */ |
475 | radeon_surface_init(rdev); | 475 | radeon_surface_init(rdev); |
476 | 476 | ||
477 | radeon_pm_resume(rdev); | ||
478 | |||
479 | rdev->accel_working = true; | 477 | rdev->accel_working = true; |
480 | r = rs400_startup(rdev); | 478 | r = rs400_startup(rdev); |
481 | if (r) { | 479 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index fdcde7693032..72d3616de08e 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c | |||
@@ -1048,8 +1048,6 @@ int rs600_resume(struct radeon_device *rdev) | |||
1048 | /* Initialize surface registers */ | 1048 | /* Initialize surface registers */ |
1049 | radeon_surface_init(rdev); | 1049 | radeon_surface_init(rdev); |
1050 | 1050 | ||
1051 | radeon_pm_resume(rdev); | ||
1052 | |||
1053 | rdev->accel_working = true; | 1051 | rdev->accel_working = true; |
1054 | r = rs600_startup(rdev); | 1052 | r = rs600_startup(rdev); |
1055 | if (r) { | 1053 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c index 35950738bd5e..3462b64369bf 100644 --- a/drivers/gpu/drm/radeon/rs690.c +++ b/drivers/gpu/drm/radeon/rs690.c | |||
@@ -756,8 +756,6 @@ int rs690_resume(struct radeon_device *rdev) | |||
756 | /* Initialize surface registers */ | 756 | /* Initialize surface registers */ |
757 | radeon_surface_init(rdev); | 757 | radeon_surface_init(rdev); |
758 | 758 | ||
759 | radeon_pm_resume(rdev); | ||
760 | |||
761 | rdev->accel_working = true; | 759 | rdev->accel_working = true; |
762 | r = rs690_startup(rdev); | 760 | r = rs690_startup(rdev); |
763 | if (r) { | 761 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 98e8138ff779..237dd29d9f1c 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c | |||
@@ -586,8 +586,6 @@ int rv515_resume(struct radeon_device *rdev) | |||
586 | /* Initialize surface registers */ | 586 | /* Initialize surface registers */ |
587 | radeon_surface_init(rdev); | 587 | radeon_surface_init(rdev); |
588 | 588 | ||
589 | radeon_pm_resume(rdev); | ||
590 | |||
591 | rdev->accel_working = true; | 589 | rdev->accel_working = true; |
592 | r = rv515_startup(rdev); | 590 | r = rv515_startup(rdev); |
593 | if (r) { | 591 | if (r) { |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 6c772e58c784..fef310773aad 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -1811,7 +1811,8 @@ int rv770_resume(struct radeon_device *rdev) | |||
1811 | /* init golden registers */ | 1811 | /* init golden registers */ |
1812 | rv770_init_golden_registers(rdev); | 1812 | rv770_init_golden_registers(rdev); |
1813 | 1813 | ||
1814 | radeon_pm_resume(rdev); | 1814 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
1815 | radeon_pm_resume(rdev); | ||
1815 | 1816 | ||
1816 | rdev->accel_working = true; | 1817 | rdev->accel_working = true; |
1817 | r = rv770_startup(rdev); | 1818 | r = rv770_startup(rdev); |
@@ -1955,9 +1956,9 @@ void rv770_fini(struct radeon_device *rdev) | |||
1955 | radeon_wb_fini(rdev); | 1956 | radeon_wb_fini(rdev); |
1956 | radeon_ib_pool_fini(rdev); | 1957 | radeon_ib_pool_fini(rdev); |
1957 | radeon_irq_kms_fini(rdev); | 1958 | radeon_irq_kms_fini(rdev); |
1958 | rv770_pcie_gart_fini(rdev); | ||
1959 | uvd_v1_0_fini(rdev); | 1959 | uvd_v1_0_fini(rdev); |
1960 | radeon_uvd_fini(rdev); | 1960 | radeon_uvd_fini(rdev); |
1961 | rv770_pcie_gart_fini(rdev); | ||
1961 | r600_vram_scratch_fini(rdev); | 1962 | r600_vram_scratch_fini(rdev); |
1962 | radeon_gem_fini(rdev); | 1963 | radeon_gem_fini(rdev); |
1963 | radeon_fence_driver_fini(rdev); | 1964 | radeon_fence_driver_fini(rdev); |
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c index 5b2ea8ac0731..b5f63f5e22a3 100644 --- a/drivers/gpu/drm/radeon/rv770_dpm.c +++ b/drivers/gpu/drm/radeon/rv770_dpm.c | |||
@@ -2526,14 +2526,7 @@ u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low) | |||
2526 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev) | 2526 | bool rv770_dpm_vblank_too_short(struct radeon_device *rdev) |
2527 | { | 2527 | { |
2528 | u32 vblank_time = r600_dpm_get_vblank_time(rdev); | 2528 | u32 vblank_time = r600_dpm_get_vblank_time(rdev); |
2529 | u32 switch_limit = 300; | 2529 | u32 switch_limit = 200; /* 300 */ |
2530 | |||
2531 | /* quirks */ | ||
2532 | /* ASUS K70AF */ | ||
2533 | if ((rdev->pdev->device == 0x9553) && | ||
2534 | (rdev->pdev->subsystem_vendor == 0x1043) && | ||
2535 | (rdev->pdev->subsystem_device == 0x1c42)) | ||
2536 | switch_limit = 200; | ||
2537 | 2530 | ||
2538 | /* RV770 */ | 2531 | /* RV770 */ |
2539 | /* mclk switching doesn't seem to work reliably on desktop RV770s */ | 2532 | /* mclk switching doesn't seem to work reliably on desktop RV770s */ |
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 83578324e5d1..9a124d0608b3 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c | |||
@@ -6618,7 +6618,8 @@ int si_resume(struct radeon_device *rdev) | |||
6618 | /* init golden registers */ | 6618 | /* init golden registers */ |
6619 | si_init_golden_registers(rdev); | 6619 | si_init_golden_registers(rdev); |
6620 | 6620 | ||
6621 | radeon_pm_resume(rdev); | 6621 | if (rdev->pm.pm_method == PM_METHOD_DPM) |
6622 | radeon_pm_resume(rdev); | ||
6622 | 6623 | ||
6623 | rdev->accel_working = true; | 6624 | rdev->accel_working = true; |
6624 | r = si_startup(rdev); | 6625 | r = si_startup(rdev); |
diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index eafb0e6bc67e..0a2f5b4bca43 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c | |||
@@ -2395,7 +2395,7 @@ static int si_populate_sq_ramping_values(struct radeon_device *rdev, | |||
2395 | if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) | 2395 | if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) |
2396 | enable_sq_ramping = false; | 2396 | enable_sq_ramping = false; |
2397 | 2397 | ||
2398 | if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) | 2398 | if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) |
2399 | enable_sq_ramping = false; | 2399 | enable_sq_ramping = false; |
2400 | 2400 | ||
2401 | for (i = 0; i < state->performance_level_count; i++) { | 2401 | for (i = 0; i < state->performance_level_count; i++) { |