aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon
diff options
context:
space:
mode:
authorRafał Miłecki <zajec5@gmail.com>2011-12-04 05:23:51 -0500
committerDave Airlie <airlied@redhat.com>2011-12-19 13:40:17 -0500
commitebcb796fa63a67ea2b7e8c023257ec6fe2813dc2 (patch)
treeaad176008e3b5afc7d729692618124606216116d /drivers/gpu/drm/radeon
parentf92e70cae880e3540d0c1dddc64825b70f963703 (diff)
drm/radeon/kms: minor HDMI audio cleanups
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c39
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c14
2 files changed, 33 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 846fae576399..fa3bb537893f 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -36,7 +36,7 @@
36 */ 36 */
37static int r600_audio_chipset_supported(struct radeon_device *rdev) 37static int r600_audio_chipset_supported(struct radeon_device *rdev)
38{ 38{
39 return (rdev->family >= CHIP_R600 && rdev->family < CHIP_CEDAR) 39 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE4(rdev))
40 || rdev->family == CHIP_RS600 40 || rdev->family == CHIP_RS600
41 || rdev->family == CHIP_RS690 41 || rdev->family == CHIP_RS690
42 || rdev->family == CHIP_RS740; 42 || rdev->family == CHIP_RS740;
@@ -248,22 +248,27 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
248 return; 248 return;
249 } 249 }
250 250
251 switch (dig->dig_encoder) { 251 if (ASIC_IS_DCE4(rdev)) {
252 case 0: 252 /* TODO */
253 WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50); 253 } else {
254 WREG32(R600_AUDIO_PLL1_DIV, clock * 100); 254 switch (dig->dig_encoder) {
255 WREG32(R600_AUDIO_CLK_SRCSEL, 0); 255 case 0:
256 break; 256 WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
257 257 WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
258 case 1: 258 WREG32(R600_AUDIO_CLK_SRCSEL, 0);
259 WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50); 259 break;
260 WREG32(R600_AUDIO_PLL2_DIV, clock * 100); 260
261 WREG32(R600_AUDIO_CLK_SRCSEL, 1); 261 case 1:
262 break; 262 WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
263 default: 263 WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
264 dev_err(rdev->dev, "Unsupported DIG on encoder 0x%02X\n", 264 WREG32(R600_AUDIO_CLK_SRCSEL, 1);
265 radeon_encoder->encoder_id); 265 break;
266 return; 266 default:
267 dev_err(rdev->dev,
268 "Unsupported DIG on encoder 0x%02X\n",
269 radeon_encoder->encoder_id);
270 return;
271 }
267 } 272 }
268} 273}
269 274
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index f5ac7e788d81..5021372a95be 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -460,7 +460,9 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder)
460 return; 460 return;
461 } 461 }
462 462
463 if (ASIC_IS_DCE4(rdev)) { 463 if (ASIC_IS_DCE5(rdev)) {
464 /* TODO */
465 } else if (ASIC_IS_DCE4(rdev)) {
464 /* TODO */ 466 /* TODO */
465 } else if (ASIC_IS_DCE3(rdev)) { 467 } else if (ASIC_IS_DCE3(rdev)) {
466 radeon_encoder->hdmi_offset = dig->dig_encoder ? 468 radeon_encoder->hdmi_offset = dig->dig_encoder ?
@@ -497,9 +499,15 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
497 } 499 }
498 500
499 offset = radeon_encoder->hdmi_offset; 501 offset = radeon_encoder->hdmi_offset;
500 if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) { 502 if (ASIC_IS_DCE5(rdev)) {
503 /* TODO */
504 } else if (ASIC_IS_DCE4(rdev)) {
505 /* TODO */
506 } else if (ASIC_IS_DCE32(rdev)) {
501 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1); 507 WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
502 } else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 508 } else if (ASIC_IS_DCE3(rdev)) {
509 /* TODO */
510 } else if (rdev->family >= CHIP_R600) {
503 switch (radeon_encoder->encoder_id) { 511 switch (radeon_encoder->encoder_id) {
504 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 512 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
505 WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4); 513 WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);