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authorAlex Deucher <alexander.deucher@amd.com>2014-06-18 11:46:35 -0400
committerAlex Deucher <alexander.deucher@amd.com>2014-07-01 11:16:08 -0400
commit9368931db826d57b6b88b3145a00276626b48df0 (patch)
tree3449ae1508c24fa7648d75a4aab9d943054af9ab /drivers/gpu/drm/radeon
parent0fcb70c30131aac40f62ba13f89963d5c13b48a7 (diff)
drm/radeon: adjust default dispclk on DCE6 (v2)
Set the default to 600Mhz if it's not set in the bios, and bump the default to 600Mhz if it's lower than that. This fixes display issues with certain 4k DP monitors when using 5.4 Ghz DP clocks. v2: fix typo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 30844814c25a..173f378428a9 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1227,11 +1227,19 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
1227 rdev->clock.default_dispclk = 1227 rdev->clock.default_dispclk =
1228 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 1228 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1229 if (rdev->clock.default_dispclk == 0) { 1229 if (rdev->clock.default_dispclk == 0) {
1230 if (ASIC_IS_DCE5(rdev)) 1230 if (ASIC_IS_DCE6(rdev))
1231 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1232 else if (ASIC_IS_DCE5(rdev))
1231 rdev->clock.default_dispclk = 54000; /* 540 Mhz */ 1233 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1232 else 1234 else
1233 rdev->clock.default_dispclk = 60000; /* 600 Mhz */ 1235 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1234 } 1236 }
1237 /* set a reasonable default for DP */
1238 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1239 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1240 rdev->clock.default_dispclk / 100);
1241 rdev->clock.default_dispclk = 60000;
1242 }
1235 rdev->clock.dp_extclk = 1243 rdev->clock.dp_extclk =
1236 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 1244 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1237 rdev->clock.current_dispclk = rdev->clock.default_dispclk; 1245 rdev->clock.current_dispclk = rdev->clock.default_dispclk;