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authorDavid S. Miller <davem@davemloft.net>2011-10-07 13:38:43 -0400
committerDavid S. Miller <davem@davemloft.net>2011-10-07 13:38:43 -0400
commit88c5100c28b02c4b2b2c6f6fafbbd76d90f698b9 (patch)
tree08c4399e0341f7eb0ccb24e15f2cab687275c2a4 /drivers/gpu/drm/radeon
parent8083f0fc969d9b5353061a7a6f963405057e26b1 (diff)
parent3ee72ca99288f1de95ec9c570e43f531c8799f06 (diff)
Merge branch 'master' of github.com:davem330/net
Conflicts: net/batman-adv/soft-interface.c
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c16
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c44
-rw-r--r--drivers/gpu/drm/radeon/ni.c32
-rw-r--r--drivers/gpu/drm/radeon/r100.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c40
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c9
-rw-r--r--drivers/gpu/drm/radeon/rv770.c51
8 files changed, 43 insertions, 161 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7ad43c6b1db7..4da23889fea6 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
115 u8 msg[20]; 115 u8 msg[20];
116 int msg_bytes = send_bytes + 4; 116 int msg_bytes = send_bytes + 4;
117 u8 ack; 117 u8 ack;
118 unsigned retry;
118 119
119 if (send_bytes > 16) 120 if (send_bytes > 16)
120 return -1; 121 return -1;
@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
125 msg[3] = (msg_bytes << 4) | (send_bytes - 1); 126 msg[3] = (msg_bytes << 4) | (send_bytes - 1);
126 memcpy(&msg[4], send, send_bytes); 127 memcpy(&msg[4], send, send_bytes);
127 128
128 while (1) { 129 for (retry = 0; retry < 4; retry++) {
129 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 130 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
130 msg, msg_bytes, NULL, 0, delay, &ack); 131 msg, msg_bytes, NULL, 0, delay, &ack);
131 if (ret < 0) 132 if (ret < 0)
132 return ret; 133 return ret;
133 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 134 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
134 break; 135 return send_bytes;
135 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 136 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
136 udelay(400); 137 udelay(400);
137 else 138 else
138 return -EIO; 139 return -EIO;
139 } 140 }
140 141
141 return send_bytes; 142 return -EIO;
142} 143}
143 144
144static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, 145static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
@@ -149,26 +150,29 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
149 int msg_bytes = 4; 150 int msg_bytes = 4;
150 u8 ack; 151 u8 ack;
151 int ret; 152 int ret;
153 unsigned retry;
152 154
153 msg[0] = address; 155 msg[0] = address;
154 msg[1] = address >> 8; 156 msg[1] = address >> 8;
155 msg[2] = AUX_NATIVE_READ << 4; 157 msg[2] = AUX_NATIVE_READ << 4;
156 msg[3] = (msg_bytes << 4) | (recv_bytes - 1); 158 msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
157 159
158 while (1) { 160 for (retry = 0; retry < 4; retry++) {
159 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, 161 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
160 msg, msg_bytes, recv, recv_bytes, delay, &ack); 162 msg, msg_bytes, recv, recv_bytes, delay, &ack);
161 if (ret == 0)
162 return -EPROTO;
163 if (ret < 0) 163 if (ret < 0)
164 return ret; 164 return ret;
165 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 165 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
166 return ret; 166 return ret;
167 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 167 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
168 udelay(400); 168 udelay(400);
169 else if (ret == 0)
170 return -EPROTO;
169 else 171 else
170 return -EIO; 172 return -EIO;
171 } 173 }
174
175 return -EIO;
172} 176}
173 177
174static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, 178static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e8a746712b5b..c4ffa14fb2f4 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1590,48 +1590,6 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1590 return backend_map; 1590 return backend_map;
1591} 1591}
1592 1592
1593static void evergreen_program_channel_remap(struct radeon_device *rdev)
1594{
1595 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1596
1597 tmp = RREG32(MC_SHARED_CHMAP);
1598 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1599 case 0:
1600 case 1:
1601 case 2:
1602 case 3:
1603 default:
1604 /* default mapping */
1605 mc_shared_chremap = 0x00fac688;
1606 break;
1607 }
1608
1609 switch (rdev->family) {
1610 case CHIP_HEMLOCK:
1611 case CHIP_CYPRESS:
1612 case CHIP_BARTS:
1613 tcp_chan_steer_lo = 0x54763210;
1614 tcp_chan_steer_hi = 0x0000ba98;
1615 break;
1616 case CHIP_JUNIPER:
1617 case CHIP_REDWOOD:
1618 case CHIP_CEDAR:
1619 case CHIP_PALM:
1620 case CHIP_SUMO:
1621 case CHIP_SUMO2:
1622 case CHIP_TURKS:
1623 case CHIP_CAICOS:
1624 default:
1625 tcp_chan_steer_lo = 0x76543210;
1626 tcp_chan_steer_hi = 0x0000ba98;
1627 break;
1628 }
1629
1630 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1631 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1632 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1633}
1634
1635static void evergreen_gpu_init(struct radeon_device *rdev) 1593static void evergreen_gpu_init(struct radeon_device *rdev)
1636{ 1594{
1637 u32 cc_rb_backend_disable = 0; 1595 u32 cc_rb_backend_disable = 0;
@@ -2078,8 +2036,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2078 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 2036 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2079 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 2037 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2080 2038
2081 evergreen_program_channel_remap(rdev);
2082
2083 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 2039 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2084 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 2040 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2085 2041
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 99fbd793c08c..8c79ca97753d 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
569 return backend_map; 569 return backend_map;
570} 570}
571 571
572static void cayman_program_channel_remap(struct radeon_device *rdev)
573{
574 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
575
576 tmp = RREG32(MC_SHARED_CHMAP);
577 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
578 case 0:
579 case 1:
580 case 2:
581 case 3:
582 default:
583 /* default mapping */
584 mc_shared_chremap = 0x00fac688;
585 break;
586 }
587
588 switch (rdev->family) {
589 case CHIP_CAYMAN:
590 default:
591 //tcp_chan_steer_lo = 0x54763210
592 tcp_chan_steer_lo = 0x76543210;
593 tcp_chan_steer_hi = 0x0000ba98;
594 break;
595 }
596
597 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
598 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
599 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
600}
601
602static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, 572static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
603 u32 disable_mask_per_se, 573 u32 disable_mask_per_se,
604 u32 max_disable_mask_per_se, 574 u32 max_disable_mask_per_se,
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev)
842 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 812 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
843 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 813 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
844 814
845 cayman_program_channel_remap(rdev);
846
847 /* primary versions */ 815 /* primary versions */
848 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 816 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
849 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 817 WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 5b1837b4aacf..7fcdbbbf2979 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -773,8 +773,8 @@ int r100_copy_blit(struct radeon_device *rdev,
773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 773 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
774 radeon_ring_write(rdev, 0); 774 radeon_ring_write(rdev, 0);
775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 775 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
776 radeon_ring_write(rdev, cur_pages); 776 radeon_ring_write(rdev, num_gpu_pages);
777 radeon_ring_write(rdev, cur_pages); 777 radeon_ring_write(rdev, num_gpu_pages);
778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 778 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
779 } 779 }
780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 780 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index c4b8741dbf58..bce63fd329d4 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm_connector *connector)
68 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 68 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
69 int saved_dpms = connector->dpms; 69 int saved_dpms = connector->dpms;
70 70
71 if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) && 71 /* Only turn off the display it it's physically disconnected */
72 radeon_dp_needs_link_train(radeon_connector)) 72 if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
73 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
74 else
75 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 73 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
74 else if (radeon_dp_needs_link_train(radeon_connector))
75 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
76 connector->dpms = saved_dpms; 76 connector->dpms = saved_dpms;
77 } 77 }
78} 78}
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index 3189a7efb2e9..fde25c0d65a0 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -208,23 +208,25 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
208 int xorigin = 0, yorigin = 0; 208 int xorigin = 0, yorigin = 0;
209 int w = radeon_crtc->cursor_width; 209 int w = radeon_crtc->cursor_width;
210 210
211 if (x < 0)
212 xorigin = -x + 1;
213 if (y < 0)
214 yorigin = -y + 1;
215 if (xorigin >= CURSOR_WIDTH)
216 xorigin = CURSOR_WIDTH - 1;
217 if (yorigin >= CURSOR_HEIGHT)
218 yorigin = CURSOR_HEIGHT - 1;
219
220 if (ASIC_IS_AVIVO(rdev)) { 211 if (ASIC_IS_AVIVO(rdev)) {
221 int i = 0;
222 struct drm_crtc *crtc_p;
223
224 /* avivo cursor are offset into the total surface */ 212 /* avivo cursor are offset into the total surface */
225 x += crtc->x; 213 x += crtc->x;
226 y += crtc->y; 214 y += crtc->y;
227 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 215 }
216 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
217
218 if (x < 0) {
219 xorigin = min(-x, CURSOR_WIDTH - 1);
220 x = 0;
221 }
222 if (y < 0) {
223 yorigin = min(-y, CURSOR_HEIGHT - 1);
224 y = 0;
225 }
226
227 if (ASIC_IS_AVIVO(rdev)) {
228 int i = 0;
229 struct drm_crtc *crtc_p;
228 230
229 /* avivo cursor image can't end on 128 pixel boundary or 231 /* avivo cursor image can't end on 128 pixel boundary or
230 * go past the end of the frame if both crtcs are enabled 232 * go past the end of the frame if both crtcs are enabled
@@ -253,16 +255,12 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
253 255
254 radeon_lock_cursor(crtc, true); 256 radeon_lock_cursor(crtc, true);
255 if (ASIC_IS_DCE4(rdev)) { 257 if (ASIC_IS_DCE4(rdev)) {
256 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, 258 WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
257 ((xorigin ? 0 : x) << 16) |
258 (yorigin ? 0 : y));
259 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 259 WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
260 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset, 260 WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
261 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 261 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
262 } else if (ASIC_IS_AVIVO(rdev)) { 262 } else if (ASIC_IS_AVIVO(rdev)) {
263 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, 263 WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
264 ((xorigin ? 0 : x) << 16) |
265 (yorigin ? 0 : y));
266 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin); 264 WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
267 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 265 WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
268 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1)); 266 ((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
@@ -276,8 +274,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
276 | yorigin)); 274 | yorigin));
277 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset, 275 WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
278 (RADEON_CUR_LOCK 276 (RADEON_CUR_LOCK
279 | ((xorigin ? 0 : x) << 16) 277 | (x << 16)
280 | (yorigin ? 0 : y))); 278 | y));
281 /* offset is from DISP(2)_BASE_ADDRESS */ 279 /* offset is from DISP(2)_BASE_ADDRESS */
282 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset + 280 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, (radeon_crtc->legacy_cursor_offset +
283 (yorigin * 256))); 281 (yorigin * 256)));
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 319d85d7e759..13690f3eb4a4 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -1507,7 +1507,14 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1507 switch (mode) { 1507 switch (mode) {
1508 case DRM_MODE_DPMS_ON: 1508 case DRM_MODE_DPMS_ON:
1509 args.ucAction = ATOM_ENABLE; 1509 args.ucAction = ATOM_ENABLE;
1510 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1510 /* workaround for DVOOutputControl on some RS690 systems */
1511 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1512 u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1513 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1514 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1515 WREG32(RADEON_BIOS_3_SCRATCH, reg);
1516 } else
1517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1511 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 1518 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1512 args.ucAction = ATOM_LCD_BLON; 1519 args.ucAction = ATOM_LCD_BLON;
1513 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1520 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4720d000d440..b13c2eedc321 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
536 return backend_map; 536 return backend_map;
537} 537}
538 538
539static void rv770_program_channel_remap(struct radeon_device *rdev)
540{
541 u32 tcp_chan_steer, mc_shared_chremap, tmp;
542 bool force_no_swizzle;
543
544 switch (rdev->family) {
545 case CHIP_RV770:
546 case CHIP_RV730:
547 force_no_swizzle = false;
548 break;
549 case CHIP_RV710:
550 case CHIP_RV740:
551 default:
552 force_no_swizzle = true;
553 break;
554 }
555
556 tmp = RREG32(MC_SHARED_CHMAP);
557 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
558 case 0:
559 case 1:
560 default:
561 /* default mapping */
562 mc_shared_chremap = 0x00fac688;
563 break;
564 case 2:
565 case 3:
566 if (force_no_swizzle)
567 mc_shared_chremap = 0x00fac688;
568 else
569 mc_shared_chremap = 0x00bbc298;
570 break;
571 }
572
573 if (rdev->family == CHIP_RV740)
574 tcp_chan_steer = 0x00ef2a60;
575 else
576 tcp_chan_steer = 0x00fac688;
577
578 /* RV770 CE has special chremap setup */
579 if (rdev->pdev->device == 0x944e) {
580 tcp_chan_steer = 0x00b08b08;
581 mc_shared_chremap = 0x00b08b08;
582 }
583
584 WREG32(TCP_CHAN_STEER, tcp_chan_steer);
585 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
586}
587
588static void rv770_gpu_init(struct radeon_device *rdev) 539static void rv770_gpu_init(struct radeon_device *rdev)
589{ 540{
590 int i, j, num_qd_pipes; 541 int i, j, num_qd_pipes;
@@ -785,8 +736,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
785 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 736 WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
786 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 737 WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
787 738
788 rv770_program_channel_remap(rdev);
789
790 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 739 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
791 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 740 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
792 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 741 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);