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authorRafał Miłecki <zajec5@gmail.com>2009-12-22 18:42:43 -0500
committerDave Airlie <airlied@redhat.com>2010-02-08 18:32:28 -0500
commit845db70da0bd285813b25bb522a0281f28efbf89 (patch)
treef9b48c667bb21f0c4b1b2e6cd4479d9b64d68def /drivers/gpu/drm/radeon
parent56278a8edacee9ae9e3bc9d8c8e2d37e9969f3eb (diff)
drm/radeon/kms: don't set pcie lanes for ignored power_state
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index adf900e368ac..e8fbae6395c7 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1593,10 +1593,6 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1593 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) + 1593 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1594 (power_state->ucNonClockStateIndex * 1594 (power_state->ucNonClockStateIndex *
1595 power_info->info_4.ucNonClockSize)); 1595 power_info->info_4.ucNonClockSize));
1596 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1597 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1598 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1599 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1600 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) { 1596 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1601 if (rdev->flags & RADEON_IS_IGP) { 1597 if (rdev->flags & RADEON_IS_IGP) {
1602 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info = 1598 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
@@ -1654,7 +1650,11 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1654 } 1650 }
1655 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 1651 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1656 if (mode_index) { 1652 if (mode_index) {
1653 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1657 misc2 = le16_to_cpu(non_clock_info->usClassification); 1654 misc2 = le16_to_cpu(non_clock_info->usClassification);
1655 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1656 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1657 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1658 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) { 1658 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1659 rdev->pm.default_power_state = &rdev->pm.power_state[state_index]; 1659 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1660 rdev->pm.current_power_state = &rdev->pm.power_state[state_index]; 1660 rdev->pm.current_power_state = &rdev->pm.power_state[state_index];