Merge tag 'v3.5'

Linux 3.5

* tag 'v3.5': (1242 commits)
  Linux 3.5
  Remove SYSTEM_SUSPEND_DISK system state
  kdb: Switch to nolock variants of kmsg_dump functions
  printk: Implement some unlocked kmsg_dump functions
  printk: Remove kdb_syslog_data
  kdb: Revive dmesg command
  dm raid1: set discard_zeroes_data_unsupported
  dm thin: do not send discards to shared blocks
  dm raid1: fix crash with mirror recovery and discard
  pnfs-obj: Fix __r4w_get_page when offset is beyond i_size
  pnfs-obj: don't leak objio_state if ore_write/read fails
  ore: Unlock r4w pages in exact reverse order of locking
  ore: Remove support of partial IO request (NFS crash)
  ore: Fix NFS crash by supporting any unaligned RAID IO
  UBIFS: fix a bug in empty space fix-up
  cx25821: Remove bad strcpy to read-only char*
  HID: hid-multitouch: add support for Zytronic panels
  MIPS: PCI: Move fixups from __init to __devinit.
  MIPS: Fix bug.h MIPS build regression
  MIPS: sync-r4k: remove redundant irq operation
  ...

21 files changed, 230 insertions, 30 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f4..3904d7964a4b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         }
 
         if (tiling_flags & RADEON_TILING_MACRO) {
-                if (rdev->family >= CHIP_CAYMAN)
+                if (rdev->family >= CHIP_TAHITI)
+                        tmp = rdev->config.si.tile_config;
+                else if (rdev->family >= CHIP_CAYMAN)
                         tmp = rdev->config.cayman.tile_config;
                 else
                         tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         } else if (tiling_flags & RADEON_TILING_MICRO)
                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
+        if ((rdev->family == CHIP_TAHITI) ||
+            (rdev->family == CHIP_PITCAIRN))
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+        else if (rdev->family == CHIP_VERDE)
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+
         switch (radeon_crtc->crtc_id) {
         case 0:
                 WREG32(AVIVO_D1VGA_CONTROL, 0);
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index e7b1ec5ae8c6..486ccdf4aacd 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1926,7 +1926,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
 
         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
                 r600_hdmi_enable(encoder);
-                if (ASIC_IS_DCE4(rdev))
+                if (ASIC_IS_DCE6(rdev))
+                        ; /* TODO (use pointers instead of if-s?) */
+                else if (ASIC_IS_DCE4(rdev))
                         evergreen_hdmi_setmode(encoder, adjusted_mode);
                 else
                         r600_hdmi_setmode(encoder, adjusted_mode);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 01550d05e273..7fb3d2e0434c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 
+        if (rdev->family <= CHIP_SUMO2)
+                WREG32(SMX_SAR_CTL0, 0x00010000);
+
         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 4e7dd2b4843d..c16554122ccd 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -52,6 +52,7 @@ struct evergreen_cs_track {
         u32                     cb_color_view[12];
         u32                     cb_color_pitch[12];
         u32                     cb_color_slice[12];
+        u32                     cb_color_slice_idx[12];
         u32                     cb_color_attrib[12];
         u32                     cb_color_cmask_slice[8];/* unused */
         u32                     cb_color_fmask_slice[8];/* unused */
@@ -127,12 +128,14 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
                 track->cb_color_info[i] = 0;
                 track->cb_color_view[i] = 0xFFFFFFFF;
                 track->cb_color_pitch[i] = 0;
-                track->cb_color_slice[i] = 0;
+                track->cb_color_slice[i] = 0xfffffff;
+                track->cb_color_slice_idx[i] = 0;
         }
         track->cb_target_mask = 0xFFFFFFFF;
         track->cb_shader_mask = 0xFFFFFFFF;
         track->cb_dirty = true;
 
+        track->db_depth_slice = 0xffffffff;
         track->db_depth_view = 0xFFFFC000;
         track->db_depth_size = 0xFFFFFFFF;
         track->db_depth_control = 0xFFFFFFFF;
@@ -250,10 +253,9 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 {
         struct evergreen_cs_track *track = p->track;
         unsigned palign, halign, tileb, slice_pt;
+        unsigned mtile_pr, mtile_ps, mtileb;
 
         tileb = 64 * surf->bpe * surf->nsamples;
-        palign = track->group_size / (8 * surf->bpe * surf->nsamples);
-        palign = MAX(8, palign);
         slice_pt = 1;
         if (tileb > surf->tsplit) {
                 slice_pt = tileb / surf->tsplit;
@@ -262,7 +264,10 @@ static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
         /* macro tile width & height */
         palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
         halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
-        surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
+        mtileb = (palign / 8) * (halign / 8) * tileb;;
+        mtile_pr = surf->nbx / palign;
+        mtile_ps = (mtile_pr * surf->nby) / halign;
+        surf->layer_size = mtile_ps * mtileb * slice_pt;
         surf->base_align = (palign / 8) * (halign / 8) * tileb;
         surf->palign = palign;
         surf->halign = halign;
@@ -434,6 +439,39 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
 
         offset += surf.layer_size * mslice;
         if (offset > radeon_bo_size(track->cb_color_bo[id])) {
+                /* old ddx are broken they allocate bo with w*h*bpp but
+                 * program slice with ALIGN(h, 8), catch this and patch
+                 * command stream.
+                 */
+                if (!surf.mode) {
+                        volatile u32 *ib = p->ib.ptr;
+                        unsigned long tmp, nby, bsize, size, min = 0;
+
+                        /* find the height the ddx wants */
+                        if (surf.nby > 8) {
+                                min = surf.nby - 8;
+                        }
+                        bsize = radeon_bo_size(track->cb_color_bo[id]);
+                        tmp = track->cb_color_bo_offset[id] << 8;
+                        for (nby = surf.nby; nby > min; nby--) {
+                                size = nby * surf.nbx * surf.bpe * surf.nsamples;
+                                if ((tmp + size * mslice) <= bsize) {
+                                        break;
+                                }
+                        }
+                        if (nby > min) {
+                                surf.nby = nby;
+                                slice = ((nby * surf.nbx) / 64) - 1;
+                                if (!evergreen_surface_check(p, &surf, "cb")) {
+                                        /* check if this one works */
+                                        tmp += surf.layer_size * mslice;
+                                        if (tmp <= bsize) {
+                                                ib[track->cb_color_slice_idx[id]] = slice;
+                                                goto old_ddx_ok;
+                                        }
+                                }
+                        }
+                }
                 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
                          "offset %d, max layer %d, bo size %ld, slice %d)\n",
                          __func__, __LINE__, id, surf.layer_size,
@@ -446,6 +484,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i
                         surf.tsplit, surf.mtilea);
                 return -EINVAL;
         }
+old_ddx_ok:
 
         return 0;
 }
@@ -1532,6 +1571,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR7_SLICE:
                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR8_SLICE:
@@ -1540,6 +1580,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case CB_COLOR11_SLICE:
                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
+                track->cb_color_slice_idx[tmp] = idx;
                 track->cb_dirty = true;
                 break;
         case CB_COLOR0_ATTRIB:
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index a51f880985f8..65c54160028b 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -156,9 +156,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 2773039b4902..b50b15c70498 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -503,6 +503,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3186522a4458..b7bf18e40215 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1303,6 +1303,10 @@ static int cayman_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
+        r = r600_audio_init(rdev);
+        if (r)
+                return r;
+
         return 0;
 }
 
@@ -1329,6 +1333,7 @@ int cayman_resume(struct radeon_device *rdev)
 
 int cayman_suspend(struct radeon_device *rdev)
 {
+        r600_audio_fini(rdev);
         /* FIXME: we should wait for ring to be empty */
         radeon_ib_pool_suspend(rdev);
         radeon_vm_manager_suspend(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index f30dc95f83b1..bff627293812 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                NUM_CLIP_SEQ(3)));
         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
+        WREG32(VC_ENHANCE, 0);
 }
 
 
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 7479a5c503e4..79b55916cf90 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,7 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
  */
 static int r600_audio_chipset_supported(struct radeon_device *rdev)
 {
-        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE5(rdev))
+        return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev))
                 || rdev->family == CHIP_RS600
                 || rdev->family == CHIP_RS690
                 || rdev->family == CHIP_RS740;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 0133f5f09bd6..ca87f7afaf23 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2079,6 +2079,48 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                         return -EINVAL;
                 }
                 break;
+        case PACKET3_STRMOUT_BASE_UPDATE:
+                if (p->family < CHIP_RV770) {
+                        DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
+                        return -EINVAL;
+                }
+                if (pkt->count != 1) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
+                        return -EINVAL;
+                }
+                if (idx_value > 3) {
+                        DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
+                        return -EINVAL;
+                }
+                {
+                        u64 offset;
+
+                        r = r600_cs_packet_next_reloc(p, &reloc);
+                        if (r) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
+                                return -EINVAL;
+                        }
+
+                        if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
+                                return -EINVAL;
+                        }
+
+                        offset = radeon_get_ib_value(p, idx+1) << 8;
+                        if (offset != track->vgt_strmout_bo_offset[idx_value]) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
+                                          offset, track->vgt_strmout_bo_offset[idx_value]);
+                                return -EINVAL;
+                        }
+
+                        if ((offset + 4) > radeon_bo_size(reloc->robj)) {
+                                DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
+                                          offset + 4, radeon_bo_size(reloc->robj));
+                                return -EINVAL;
+                        }
+                        ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
+                }
+                break;
         case PACKET3_SURFACE_BASE_UPDATE:
                 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
                         DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 969c27529dfe..82a0a4c919c0 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -322,9 +322,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
-                return;
-
         /* Silent, r600_hdmi_enable will raise WARN for us */
         if (!dig->afmt->enabled)
                 return;
@@ -483,7 +480,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
         uint32_t offset;
         u32 hdmi;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Silent, r600_hdmi_enable will raise WARN for us */
@@ -543,7 +540,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t offset;
 
-        if (ASIC_IS_DCE5(rdev))
+        if (ASIC_IS_DCE6(rdev))
                 return;
 
         /* Called for ATOM_ENCODER_MODE_HDMI only */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index a0dbf1fe6a40..025fd5b6c08c 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -485,6 +485,7 @@
 #define         TC_L2_SIZE(x)                                   ((x)<<5)
 #define         L2_DISABLE_LATE_HIT                             (1<<9)
 
+#define VC_ENHANCE                                      0x9714
 
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
@@ -1163,6 +1164,7 @@
 #define PACKET3_SET_CTL_CONST                           0x6F
 #define         PACKET3_SET_CTL_CONST_OFFSET                    0x0003cff0
 #define         PACKET3_SET_CTL_CONST_END                       0x0003e200
+#define PACKET3_STRMOUT_BASE_UPDATE                     0x72 /* r7xx */
 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
 
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index f0bb2b543b13..2c4d53fd20c5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -57,9 +57,11 @@
  *   2.13.0 - virtual memory support, streamout
  *   2.14.0 - add evergreen tiling informations
  *   2.15.0 - add max_pipes query
+ *   2.16.0 - fix evergreen 2D tiled surface calculation
+ *   2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        15
+#define KMS_DRIVER_MINOR        17
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 59d44937dd9f..84b648a7ddd8 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -289,8 +289,9 @@ int radeon_vm_manager_init(struct radeon_device *rdev)
         rdev->vm_manager.enabled = false;
 
         /* mark first vm as always in use, it's the system one */
+        /* allocate enough for 2 full VM pts */
         r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
-                                      rdev->vm_manager.max_pfn * 8,
+                                      rdev->vm_manager.max_pfn * 8 * 2,
                                       RADEON_GEM_DOMAIN_VRAM);
         if (r) {
                 dev_err(rdev->dev, "failed to allocate vm bo (%dKB)\n",
@@ -633,7 +634,15 @@ int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm)
         mutex_init(&vm->mutex);
         INIT_LIST_HEAD(&vm->list);
         INIT_LIST_HEAD(&vm->va);
-        vm->last_pfn = 0;
+        /* SI requires equal sized PTs for all VMs, so always set
+         * last_pfn to max_pfn.  cayman allows variable sized
+         * pts so we can grow then as needed.  Once we switch
+         * to two level pts we can unify this again.
+         */
+        if (rdev->family >= CHIP_TAHITI)
+                vm->last_pfn = rdev->vm_manager.max_pfn;
+        else
+                vm->last_pfn = 0;
         /* map the ib pool buffer at 0 in virtual address space, set
          * read only
          */
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index f28bd4b7ef98..21ec9f5653ce 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -292,6 +292,7 @@ int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
                           struct drm_file *filp)
 {
+        struct radeon_device *rdev = dev->dev_private;
         struct drm_radeon_gem_busy *args = data;
         struct drm_gem_object *gobj;
         struct radeon_bo *robj;
@@ -317,13 +318,14 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
                 break;
         }
         drm_gem_object_unreference_unlocked(gobj);
-        r = radeon_gem_handle_lockup(robj->rdev, r);
+        r = radeon_gem_handle_lockup(rdev, r);
         return r;
 }
 
 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
                               struct drm_file *filp)
 {
+        struct radeon_device *rdev = dev->dev_private;
         struct drm_radeon_gem_wait_idle *args = data;
         struct drm_gem_object *gobj;
         struct radeon_bo *robj;
@@ -336,10 +338,10 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
         robj = gem_to_radeon_bo(gobj);
         r = radeon_bo_wait(robj, NULL, false);
         /* callback hw specific functions if any */
-        if (robj->rdev->asic->ioctl_wait_idle)
-                robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
+        if (rdev->asic->ioctl_wait_idle)
+                robj->rdev->asic->ioctl_wait_idle(rdev, robj);
         drm_gem_object_unreference_unlocked(gobj);
-        r = radeon_gem_handle_lockup(robj->rdev, r);
+        r = radeon_gem_handle_lockup(rdev, r);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 08825548ee69..5b37e283ec38 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -801,9 +801,13 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work)
                 int i;
 
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
-                        not_processed += radeon_fence_count_emitted(rdev, i);
-                        if (not_processed >= 3)
-                                break;
+                        struct radeon_ring *ring = &rdev->ring[i];
+
+                        if (ring->ready) {
+                                not_processed += radeon_fence_count_emitted(rdev, i);
+                                if (not_processed >= 3)
+                                        break;
+                        }
                 }
 
                 if (not_processed >= 3) { /* should upclock */
diff --git a/drivers/gpu/drm/radeon/radeon_prime.c b/drivers/gpu/drm/radeon/radeon_prime.c
index 8ddab4c76710..6bef46ace831 100644
--- a/drivers/gpu/drm/radeon/radeon_prime.c
+++ b/drivers/gpu/drm/radeon/radeon_prime.c
@@ -169,11 +169,17 @@ struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
         struct radeon_bo *bo = gem_to_radeon_bo(obj);
         int ret = 0;
 
+        ret = radeon_bo_reserve(bo, false);
+        if (unlikely(ret != 0))
+                return ERR_PTR(ret);
+
         /* pin buffer into GTT */
         ret = radeon_bo_pin(bo, RADEON_GEM_DOMAIN_GTT, NULL);
-        if (ret)
+        if (ret) {
+                radeon_bo_unreserve(bo);
                 return ERR_PTR(ret);
-
+        }
+        radeon_bo_unreserve(bo);
         return dma_buf_export(bo, &radeon_dmabuf_ops, obj->size, flags);
 }
 
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 4ad0281fdc37..b4f51c569c36 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
                                        ACK_FLUSH_CTL(3) |
                                        SYNC_FLUSH_CTL));
 
+        if (rdev->family != CHIP_RV770)
+                WREG32(SMX_SAR_CTL0, 0x00003f3f);
+
         db_debug3 = RREG32(DB_DEBUG3);
         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
         switch (rdev->family) {
@@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
                                           NUM_CLIP_SEQ(3)));
-
+        WREG32(VC_ENHANCE, 0);
 }
 
 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index fdc089896011..b0adfc595d75 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -211,6 +211,7 @@
 #define SCRATCH_UMSK                                    0x8540
 #define SCRATCH_ADDR                                    0x8544
 
+#define SMX_SAR_CTL0                                    0xA008
 #define SMX_DC_CTL0                                     0xA020
 #define         USE_HASH_FUNCTION                               (1 << 0)
 #define         CACHE_DEPTH(x)                                  ((x) << 1)
@@ -310,6 +311,8 @@
 #define TCP_CNTL                                        0x9610
 #define TCP_CHAN_STEER                                  0x9614
 
+#define VC_ENHANCE                                      0x9714
+
 #define VGT_CACHE_INVALIDATION                          0x88C4
 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
 #define                 VC_ONLY                                         0
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index c7b61f16ecfd..0b0279291a73 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2365,12 +2365,12 @@ int si_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(0x15DC, 0);
 
         /* empty context1-15 */
-        /* FIXME start with 1G, once using 2 level pt switch to full
+        /* FIXME start with 4G, once using 2 level pt switch to full
          * vm size space
          */
         /* set vm size, must be a multiple of 4 */
         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
-        WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, (1 << 30) / RADEON_GPU_PAGE_SIZE);
+        WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
         for (i = 1; i < 16; i++) {
                 if (i < 8)
                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h
index eda938a7cb6e..501f9d431d57 100644
--- a/drivers/gpu/drm/radeon/si_reg.h
+++ b/drivers/gpu/drm/radeon/si_reg.h
@@ -30,4 +30,76 @@
 #define SI_DC_GPIO_HPD_EN                        0x65b8
 #define SI_DC_GPIO_HPD_Y                         0x65bc
 
+#define SI_GRPH_CONTROL                          0x6804
+#       define SI_GRPH_DEPTH(x)                  (((x) & 0x3) << 0)
+#       define SI_GRPH_DEPTH_8BPP                0
+#       define SI_GRPH_DEPTH_16BPP               1
+#       define SI_GRPH_DEPTH_32BPP               2
+#       define SI_GRPH_NUM_BANKS(x)              (((x) & 0x3) << 2)
+#       define SI_ADDR_SURF_2_BANK               0
+#       define SI_ADDR_SURF_4_BANK               1
+#       define SI_ADDR_SURF_8_BANK               2
+#       define SI_ADDR_SURF_16_BANK              3
+#       define SI_GRPH_Z(x)                      (((x) & 0x3) << 4)
+#       define SI_GRPH_BANK_WIDTH(x)             (((x) & 0x3) << 6)
+#       define SI_ADDR_SURF_BANK_WIDTH_1         0
+#       define SI_ADDR_SURF_BANK_WIDTH_2         1
+#       define SI_ADDR_SURF_BANK_WIDTH_4         2
+#       define SI_ADDR_SURF_BANK_WIDTH_8         3
+#       define SI_GRPH_FORMAT(x)                 (((x) & 0x7) << 8)
+/* 8 BPP */
+#       define SI_GRPH_FORMAT_INDEXED            0
+/* 16 BPP */
+#       define SI_GRPH_FORMAT_ARGB1555           0
+#       define SI_GRPH_FORMAT_ARGB565            1
+#       define SI_GRPH_FORMAT_ARGB4444           2
+#       define SI_GRPH_FORMAT_AI88               3
+#       define SI_GRPH_FORMAT_MONO16             4
+#       define SI_GRPH_FORMAT_BGRA5551           5
+/* 32 BPP */
+#       define SI_GRPH_FORMAT_ARGB8888           0
+#       define SI_GRPH_FORMAT_ARGB2101010        1
+#       define SI_GRPH_FORMAT_32BPP_DIG          2
+#       define SI_GRPH_FORMAT_8B_ARGB2101010     3
+#       define SI_GRPH_FORMAT_BGRA1010102        4
+#       define SI_GRPH_FORMAT_8B_BGRA1010102     5
+#       define SI_GRPH_FORMAT_RGB111110          6
+#       define SI_GRPH_FORMAT_BGR101111          7
+#       define SI_GRPH_BANK_HEIGHT(x)            (((x) & 0x3) << 11)
+#       define SI_ADDR_SURF_BANK_HEIGHT_1        0
+#       define SI_ADDR_SURF_BANK_HEIGHT_2        1
+#       define SI_ADDR_SURF_BANK_HEIGHT_4        2
+#       define SI_ADDR_SURF_BANK_HEIGHT_8        3
+#       define SI_GRPH_TILE_SPLIT(x)             (((x) & 0x7) << 13)
+#       define SI_ADDR_SURF_TILE_SPLIT_64B       0
+#       define SI_ADDR_SURF_TILE_SPLIT_128B      1
+#       define SI_ADDR_SURF_TILE_SPLIT_256B      2
+#       define SI_ADDR_SURF_TILE_SPLIT_512B      3
+#       define SI_ADDR_SURF_TILE_SPLIT_1KB       4
+#       define SI_ADDR_SURF_TILE_SPLIT_2KB       5
+#       define SI_ADDR_SURF_TILE_SPLIT_4KB       6
+#       define SI_GRPH_MACRO_TILE_ASPECT(x)      (((x) & 0x3) << 18)
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_1  0
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_2  1
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_4  2
+#       define SI_ADDR_SURF_MACRO_TILE_ASPECT_8  3
+#       define SI_GRPH_ARRAY_MODE(x)             (((x) & 0x7) << 20)
+#       define SI_GRPH_ARRAY_LINEAR_GENERAL      0
+#       define SI_GRPH_ARRAY_LINEAR_ALIGNED      1
+#       define SI_GRPH_ARRAY_1D_TILED_THIN1      2
+#       define SI_GRPH_ARRAY_2D_TILED_THIN1      4
+#       define SI_GRPH_PIPE_CONFIG(x)            (((x) & 0x1f) << 24)
+#       define SI_ADDR_SURF_P2                   0
+#       define SI_ADDR_SURF_P4_8x16              4
+#       define SI_ADDR_SURF_P4_16x16             5
+#       define SI_ADDR_SURF_P4_16x32             6
+#       define SI_ADDR_SURF_P4_32x32             7
+#       define SI_ADDR_SURF_P8_16x16_8x16        8
+#       define SI_ADDR_SURF_P8_16x32_8x16        9
+#       define SI_ADDR_SURF_P8_32x32_8x16        10
+#       define SI_ADDR_SURF_P8_16x32_16x16       11
+#       define SI_ADDR_SURF_P8_32x32_16x16       12
+#       define SI_ADDR_SURF_P8_32x32_16x32       13
+#       define SI_ADDR_SURF_P8_32x64_32x32       14
+
 #endif